AERIS-10 Docs

Engineering Journal

Implementation Timeline and Improvements

Consolidated record of key firmware, timing, debug and infrastructure changes.

Recent milestone timeline

Build 16 XDC cleanup validated on production target

Remote production XDC pass eliminated XDCB-5 warnings, collapsed the large TIMING-18 bucket to a single ft601_txe residue, and preserved timing at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.

Build 15 timing-clean integration baseline established

Production-target implementation completed with all timing constraints met after USB range-profile wiring and the CFAR sequential-assignment fix.

USB range profile path wired to matched-filter output

The top-level Doppler placeholder was removed from the USB range-profile path and replaced with the real matched-filter range output propagated through the receiver chain.

Firmware bug sweep closed with regression coverage

All 17 audited MCU firmware bugs were fixed, regression-tested, and pushed, including LO init ordering, SPI chip-select handling, PA calibration logic, TIM3 PWM bring-up, and stale diagnostic mismatches.

FPGA timing/resource cleanup phase completed

Chirp BRAM migration, Doppler DSP48 pipelining, CIC pipeline staging, matched-filter regression repair, and full FPGA regression brought the active baseline to 18/18 passing tests.

Build 13 frozen as earlier hardware candidate

Historical milestone retained for traceability: WNS +0.311 ns, TNS 0.000, WHS +0.060, THS 0.000 on the production target before the later DSP and integration work.

Codebase quality and verification upgrades

  • Added comprehensive DIAG instrumentation across MCU bring-up, LO, PA, USB, and safety paths before executing the bug-fix phase.
  • Built an STM32 HAL/mock regression harness and closed the audited firmware bug list with MCU regression passing.
  • Ran full FPGA regression with 18/18 passing suites, including matched filter, Doppler, CIC, CDC, USB, and system-top coverage.
  • Migrated the chirp LUT path toward BRAM, added DSP48 and CIC pipeline staging, and validated that the active FPGA baseline still meets timing.

Debug and infrastructure improvements

  • Completed Build 15 production-target analysis with timing, power, route, DRC, methodology, and CDC evidence captured in the internal engineering reports.
  • Validated a remote-only Build 16 XDC cleanup pass that removed XDCB-5, reduced TIMING-18 to a single ft601_txe methodology residue, and preserved post-route timing.
  • Kept separate Trenz development targets while prioritizing the in-stock TE0713 path for practical hardware execution.
  • Preserved remote Vivado baselines so timing-clean builds can be compared before and after constraint-only experiments.