Artifacts
Central access point for antenna simulations, implementation summaries, timing baselines, and board-day artifact references.
ft601_txe methodology residue, and routed timing remained clean at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.ft601_txe methodology item currently behaves like an async-status-observation residue rather than a proven unconstrained functional FT601 path.| Artifact | Source path | Day-0 use | Status / note |
|---|---|---|---|
| Production-target XDC | 9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc | Constraint source of truth for the production FPGA target | Tracked and validated after Build 16 cleanup port |
| FPGA programming flow | 9_Firmware/9_2_FPGA/scripts/program_fpga.tcl | Programs the device and reports DONE / INIT_COMPLETE / probes presence | Primary operator-facing programming script |
| Debug probe insertion flow | 9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl | Used when generating or refreshing debug-capable images | Keep matched with the selected debug bitstream |
| FPGA regression runner | 9_Firmware/9_2_FPGA/run_regression.sh | Pre-arrival regression evidence for the tracked FPGA baseline | 18 / 18 passing on the current tracked branch |
| MCU regression harness | 9_Firmware/9_1_Microcontroller/tests/Makefile | Pre-arrival firmware regression evidence before flashing hardware | 15 / 15 passing on the current tracked branch |
| Bring-up logging macros | 9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h | Defines the main first-power-on log vocabulary used over USART3 | Observation-only instrumentation layer |
| Board-day worksheet | docs/board-day-worksheet.html | Record pass/fail, measurements, and blockers during first sessions | Use with this page and the bring-up plan |
| Bring-up execution plan | docs/bring-up.html | Operator checklist, abort criteria, observability targets, and open risks | Primary readiness document |
Status: Mostly current (historical Phase-0 context)
File: AERIS_Antenna_Report.pdf
Notes: Valid for 10.5 GHz patch-element simulation and array projection context. Treat as element-level evidence, not full current hardware bring-up sign-off.
Status: Legacy (needs refresh)
File: AERIS_Simulation_Report.pdf
Notes: Contains older architecture assumptions (e.g., XC7A100T-centric narrative). Use as historical reference only until Simulation Report v2 is published.
Status: Current engineering baseline
Primary detailed write-up: internal Build 15 implementation analysis captured timing, power, route status, DRC, methodology, CDC, and utilization for the production-target design after USB range wiring and CFAR cleanup.
Follow-on Build 16 remote validation focused on production XDC cleanup only and confirmed no timing regression while reducing methodology noise substantially.
Status: Current baseline (v2)
File: AERIS_Simulation_Report_v2.pdf
Aligned to the active project baseline: XC7A200T target, firmware regression closure, FPGA regression/timing gates, USB range-profile integration, and TE0712/TE0713 split-target flow.
