Published Reports and Visuals

Current FPGA implementation status

• Build 24 is the current production baseline for the XC7A200T target. All timing constraints met. Includes CA-CFAR detector integration with pipelined noise computation.
• Build 24 reports are available on the remote Vivado host at ~/PLFM_RADAR_work/vivado_project/reports_build24/.
• Build 21 (v0.1.4-build21) retained as pre-CFAR reference at reports_build21/.

Build 24 — 15-Point Engineering Report

Status: PASS — Production-safe bitstream generated

Date: 2026-03-20  |  Commit: 0745cc4  |  Device: XC7A200T-2FBG484I  |  Vivado 2025.2

1. Timing Summary

TNS = 0.000 ns, THS = 0.000 ns across all domains. Zero failing endpoints.

2. Utilization (Post-Route)

CFAR added +1 BRAM18 (magnitude buffer, 2048×17), +3 DSP48E1 (alpha multiply + cross-multiply for GO/SO), +2,366 LUTs (sliding window logic, state machine, mode mux), +1,320 FFs (pipeline registers, counters, window sums).

3. DSP48E1 Breakdown by Module

4. BRAM Breakdown by Module

5. Power Estimate

+22 mW (+3%) from CFAR logic. Well within thermal budget.

6. Critical Path Analysis

The tightest path (WNS = +0.179 ns) is in the clk_mmcm_out0 (400 MHz) domain: NCO sine LUT index register → LUT6 → sin_abs_reg. This is the same path that was critical in Build 21 and is unrelated to CFAR.

The clk_100m domain (where CFAR operates) has +0.287 ns slack. The Build 23 critical path (cfar_inst/leading_sum → cross-multiply → alpha*noise DSP, WNS = -0.309 ns) has been completely eliminated by the pipeline fix.

7. Post-Synthesis vs Post-Route Comparison

Post-route phys_opt resolved all 29 hold violations and improved setup slack by 56 ps. LUT/FF count reduced slightly by optimization passes.

8. DRC (Design Rule Checks)

184 checks performed. 0 errors, 0 critical warnings. Advisory/warning breakdown:

• DPIP-1 (input pipelining advisory): 68 — DSP input pipeline suggestions, acceptable for our architecture
• DPOP-1/2 (output pipelining): 18 + 19 — DSP PREG/MREG advisory, non-critical
• REQP-1839/1840 (BRAM async control): 20 + 20 — expected with async-reset BRAMs
• RPBF-3 (IO buffering): 8 — intentional for differential pairs
• CHECK-3 (report rule limit): 2 — tool display limit, not design issue
• IOSR-1 (IOB set/reset sharing): 1 — non-critical

9. Methodology Report

• DPIR-1 (async driver): 91 — known from async-reset architecture, mitigated by CDC modules
• HPDR-1 (port direction inconsistency): 8 — bidir USB data bus, expected
• LUTAR-1 (LUT drives async reset): 1 — watchdog reset path, intentional
• PDRC-190 (suboptimal sync register placement): 3 — minor, does not affect timing
• SYNTH-6 (RAM timing sub-optimal): 18 — inferred RAMs, all meeting timing
• TIMING-9 (unknown CDC logic): 1 — covered by explicit CDC synchronizers
• TIMING-28 (auto-derived clock in constraint): 8 — expected with MMCM-derived clocks
• TIMING-47 (false path between sync clocks): 4 — intentional XDC false_path constraints

10. Congestion

No congestion windows found above level 5. The design is well-placed with no routing pressure. XC7A200T provides ample routing resources at 6.36% LUT utilization.

11. Route Status

• Total logical nets: 31,136
• Routable nets: 22,026 — 22,026 fully routed (100%)
• Nets with routing errors: 0

12. Logic Level Distribution (Top 1000 Worst Paths)

The clk_100m domain has only level-0 paths in the top-1000 worst — CFAR pipeline fix reduced logic depth to register-to-register transfers. The 400 MHz DDC domain remains the most timing-critical area.

13. Build-Over-Build Comparison

14. CFAR Integration Resource Cost

Total CFAR cost: 2.82% of device LUTs, 0.48% of FFs, 0.27% of BRAM, 0.41% of DSPs. Minimal impact on headroom.

15. Verification Summary

5,281 individual data checks across all RTL test suites. Zero failures. Real-data co-simulation confirms bit-exact match with Python golden reference across the entire signal processing chain.

Build 24 Artifacts

• Bitstream: ~/PLFM_RADAR_work/vivado_project/bitstream/radar_system_top_build24.bit (9.7 MB)
• Reports: ~/PLFM_RADAR_work/vivado_project/reports_build24/ (21 report files)
• Build log: ~/PLFM_RADAR_work/build24.log
• TCL script: ~/PLFM_RADAR_work/vivado_project/build24_cfar.tcl

Note: TCL crashed at step 13/15 (extract_files missing parameter) after all reports were generated. Non-critical scripting bug; all implementation, optimization, and bitstream generation completed successfully.

Board-day artifact inventory

FPGA implementation analysis

Status: Current engineering baseline — Build 24 (CFAR + pipeline fix)

Build 24 is the current production baseline. Includes CA-CFAR detector integration (CA/GO/SO modes) with pipelined noise computation for timing closure. Full 15-point report above. WNS +0.179 ns (improved from Build 21's +0.156 ns due to phys_opt improvements). DSP count 142 (+3 for CFAR alpha and cross-multiply). BRAM 17 (+1 for CFAR magnitude buffer).

Build 23 failed timing (WNS -0.309 ns) due to combinational critical path in CFAR noise computation. Root-caused and fixed by pipelining noise_sum_comb into a registered intermediate (noise_sum_reg), splitting the path across two clock cycles.

Build 21 (v0.1.4-build21) retained as pre-CFAR reference. Build 20 (v0.1.3-build20) and earlier retained for historical reference.

Latest Simulation Report (Recommended)

Status: Current baseline (v2)

File: AERIS_Simulation_Report_v2.pdf

Aligned to the active project baseline: XC7A200T target, firmware regression closure, FPGA regression/timing gates, USB range-profile integration, and TE0712/TE0713 split-target flow.

Open PDF Download

Report Currency Notice

• The current routed production-target baseline is Build 24 with all timing constraints met. WNS +0.179 ns, WHS +0.056 ns, 142 DSP48E1, 17 BRAM, 0.754 W.
• All architectural gaps are closed: Gap 1 (CFAR) integrated as CA-CFAR detector with CA/GO/SO modes. Gaps 2–7 were closed prior to Build 21.
• FPGA regression: 22/22 pass (includes CFAR standalone + E2E CFAR config tests). MCU regression: 20/20 pass. Real-data co-sim: 3/3 exact match (5,137 data checks).
• CFAR integration cost: +2,229 LUTs, +1,281 FFs, +1 BRAM, +3 DSPs. Backward-compatible: host_cfar_enable defaults to disabled.
• Detailed Build 24 engineering reports are on the remote Vivado host at ~/PLFM_RADAR_work/vivado_project/reports_build24/.
• The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.

Antenna concept snapshot