Execution Checklist

Hardware Bring-Up Plan

Pre-arrival completeness gates, board-day smoke tests, and fault-localization rules for the first FPGA module and carrier-board sessions.

Pre-arrival completeness gates

Gate	Objective	Pass Criteria	Evidence
1	Freeze known-good firmware and bitstream baselines	Tracked commit, named artifact set, and repeatable programming flow are available	Git commit, bitstream path, reports, programming TCL
2	Preserve clean implementation constraints	Positive WNS/WHS/WPWS, XDCB-5 cleared, only documented methodology residue remains	Timing summary and methodology report
3	Keep regressions green before board arrival	MCU host tests and FPGA regression/integration suites pass on the tracked tree	15/15 MCU and 18/18 FPGA logs
4	Make first-power-on behavior observable	Clock, LO, beamformer, PA, and USB status can be identified from logs or status outputs	DIAG coverage, status fields, ILA/debug plan
5	Prepare board-arrival execution checklist	Power order, abort criteria, and host-side capture steps are written and reviewed	This page plus reports and scripts references
6	Document unresolved pre-hardware risks	Open issues are explicitly listed so Day-0 findings are interpreted correctly	Known-open-risks section below

Inspect carrier defaults, regulator enables, jumpers, and any board-level clock source selections before power is applied.
Power the carrier and module in the safest configuration with RF transmit paths disabled and document current draw immediately.
Run the FPGA programming flow, verify JTAG enumeration, and confirm DONE and INIT_COMPLETE from the hardware manager script.
Check deterministic reset release and heartbeat/status outputs before enabling any analog or RF-dependent function.
Bring up MCU firmware logging, confirm AD9523 status pins, LO initialization results, and beamformer communication readback.
Use the debug-capable FPGA image and probes to confirm raw ADC, DDC, matched-filter, and USB-path activity in that order.
Exercise the FT601 path with known framing expectations before any long-duration streaming test.
Only after all previous steps pass, begin PA bias, calibration, and higher-risk RF activation.

Stop immediately on unexpected rail current, regulator instability, or thermal rise beyond the planned idle envelope.
Do not continue past LO bring-up if the lock GPIOs or lock-status reads disagree repeatedly.
Stop RF activation if beamformer scratchpad/readback checks fail on any device.
Do not continue USB stress testing if framing, backpressure, or bus-direction behavior is inconsistent.
Revert to the heartbeat or debug image if reset sequencing or clock presence is ambiguous.
Keep the production-target constraints and pinout source untouched while bring-up-specific targets are being adjusted.

Subsystem	What must be visible	Expected evidence
FPGA configuration	JTAG enumeration, DONE, INIT_COMPLETE, optional ILA probe presence	program_fpga.tcl summary and hardware-manager status
Clocking	AD9523 status pins and deterministic downstream reset release	DIAG clock messages and status GPIO snapshots
LO chain	ADF4382A init status, timed-sync path status, TX/RX lock state	USART3 DIAG log plus lock GPIO behavior
Beamformer control	Per-device communication sanity and basic temperature readback	ADAR1000 scratchpad/readback and temperature prints
PA biasing	DAC/ADC bring-up progression and IDQ calibration convergence bounds	Per-channel PA DIAG output with stop conditions
FPGA data path	ADC, DDC, matched-filter, and USB-path activity in sequence	ILA captures and system status outputs
USB/FT601 link	Stable framing, no obvious underrun/backpressure surprises, host decode sanity	Host capture script output and stable packet boundaries

Named firmware baseline commit and build instructions for the MCU image.
Named FPGA baseline bitstream and matching `.ltx` probes file for debug sessions.
Current production-target XDC, timing summary, and methodology report.
Programming and debug TCL scripts for baseline and debug images.
Regression evidence for the tracked branch: MCU host suite and FPGA regression/integration suite.
Day-0 measurement sheet covering supply currents, temperatures, and observed status outputs.

JTAG programming workflow using the checked-in Vivado TCL scripts.
Serial capture on USART3 with timestamps preserved for bring-up logs.
FT601 or host-side USB capture/decoder workflow to validate framing and payload stability.
ILA capture workflow for raw ADC, DDC, matched-filter, and USB-domain checkpoints.
Repeatable checklist for baseline image, debug image, and rollback image selection.

Risk	Current state	Day-0 handling
Residual FT601 methodology warning	Production-target XDC cleanup is validated, but one `ft601_txe` methodology residue remains documented.	Treat as a known observation item and verify real FT601 status behavior before attempting deeper constraint churn.
RF control-path realism	Firmware sequencing and diagnostics improved, but LO sync, phase behavior, and beamformer control still require physical validation.	Use readback-first bring-up and do not assume analog behavior from simulation or logs alone.
Prototype-grade top-level functional assumptions	The active FPGA baseline is regression-clean, but some radar-function behavior still needs real-board confirmation under actual I/O conditions.	Validate each data-path stage incrementally with ILA and host captures before full streaming claims.
PA calibration boundaries	IDQ calibration logic is much safer than before, but real-device convergence and margin limits are not yet board-proven.	Use conservative limits, observe every channel, and stop on abnormal current or non-convergent channels.
Board-specific integration unknowns	Carrier/module interaction, rails, clocks, and connector assumptions remain partially unproven until first assembly.	Begin with lowest-risk heartbeat and configuration checks before enabling higher-energy subsystems.