AERIS-10 Docs | Release Notes

Commit timeline

Commit	Title	Impact
`2763b4b`	CFAR sequential fix and Build 15 analysis capture	Replaced the clocked-block CFAR blocking assignment with sequential logic and published the Build 15 timing/DRC/methodology analysis baseline.
`3fa26c9`	USB range profile wiring completed	Removed the Doppler placeholder from the USB range path and propagated real matched-filter range data through the receiver/top-level interfaces.
`f4ff271`	Matched-filter regression repair	Corrected golden-case `$readmemh` paths so the matched-filter regression returned to 40/40 passing.
`463ebef`	CIC pipeline staging and regression runner	Added CIC comb pipeline staging, simulation guards, and an FPGA regression runner to preserve timing while tightening verification.
`c466021`	Firmware bug sweep closure (B12-B17)	Closed the PA calibration, ADC buffer, DIAG macro, TIM3 PWM, and stale-diagnostic issues with additional MCU regression coverage.
`49c9aa2`	SPI platform fix plus FPGA B2/B3 timing work	Fixed the legacy platform SPI transmit-only path and landed chirp BRAM migration plus Doppler DSP48 pipelining work.
`3b32f67`	ADF4382A SPI and chip-select correctness	Fixed platform SPI ops wiring, added software-managed CS behavior, and widened SPI chip-select storage to handle STM32 pin values correctly.
`3979693`	Initial 8-firmware-bug closure with tests	Closed the LO init ordering, AD9523 sequencing, sync trigger, temperature timer, GPIO mapping, and related MCU issues with regression coverage.

Build 16 remote production-XDC cleanup has been validated in the remote Vivado workspace but is not yet represented by a git commit.
The remote-only pass removed XDCB-5 warnings, reduced the large TIMING-18 bucket to a single ft601_txe methodology residue, and preserved timing at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.
The surviving ft601_txe item currently behaves like a methodology residue on an async status-observation path rather than a proven unconstrained functional FT601 interface.