Build 13 Timing
WNS +0.311 ns
TNS 0.000, WHS +0.060, THS 0.000
Open-Source Phased Array Radar
Engineering Documentation Site
This site tracks architecture, FPGA improvements, timing closure outcomes, and hardware bring-up readiness for AERIS-10.
Regression Status
13 / 13 Suites
Integration golden match: 2048 / 2048
Debug Instrumentation
4 ILA Cores
92 probe bits, 4096 depth
Current Phase
Hardware Bring-Up
TE0712/TE0713 split targets prepared
What changed recently
- Closed timing on XC7A200T target and froze Build 13 candidate.
- Added CDC waivers for 5 verified false positives.
- Created resilient ILA insertion flow with post-synthesis net discovery.
- Generated baseline and debug bitstreams for bring-up.
- Added TE0712/TE0701 and TE0713/TE0701 split build targets.