Build 13 frozen as hardware candidate
WNS +0.311 ns, TNS 0.000, WHS +0.060, THS 0.000 on production target.
Engineering Journal
Implementation Timeline and Improvements
Consolidated record of key firmware, timing, debug and infrastructure changes.
Recent milestone timeline
CDC analysis completed with waivers
5 critical warnings verified as false positives and documented as waivers.
ILA insertion flow hardened
Added net discovery pass, deferred core creation, and Vivado 2025.2 MU_CNT handling.
Bring-up scripts and bitstreams generated
Baseline + debug bitstreams, programming script, and ILA capture script prepared.
Target split for Trenz development path
Added TE0712 and TE0713 separate top wrappers/XDC/build scripts to isolate pinout differences.
Codebase quality and verification upgrades
- Expanded simulation and co-simulation coverage with golden comparison workflows.
- Formal verification executed across critical modules with passing results.
- Improved reset strategy in key blocks to reduce async-reset related methodology warnings.
- Renamed latency buffer module for maintainability and consistent references.
Debug and infrastructure improvements
- Post-synthesis net-name mapping documented to avoid brittle ILA net paths.
- Generated both no-ILA and ILA debug bitstreams for staged bring-up.
- Added dedicated scripts for TE0712/TE0713 split builds.
- Created community issue to crowdsource compatible hardware test execution.