Execution Checklist

Hardware Bring-Up Plan

Operational sequence and pass/fail gates for Day-1 and post-Day-1 validation.

Bring-up gates

Step	Objective	Pass Criteria
1	Program baseline bitstream	JTAG detect + successful configuration
2	Clock/reset sanity	Stable clocks and deterministic reset release
3	ADC front-end	Valid raw data visible in ILA on expected clock
4	DDC verification	Expected valid strobe and non-zero I/Q outputs
5	Matched filter stage	Range profile valid asserted and segment flow correct
6	Range/Doppler pipeline	Deterministic frame outputs with full bin coverage
7	USB host link	Sustained transfer and stable framing over soak window
8	Thermal/power screen	No rail anomalies or thermal runaway under load

Day-1 quick sequence

Mount SoM on carrier and verify supply/jumper defaults.
Program minimal heartbeat top for immediate hardware liveness check.
Program debug bitstream and attach LTX for ILA sessions.
Capture first ADC and DDC traces, compare with expected signatures.

Risk controls

Keep production target untouched; use split dev targets for carrier-specific pinouts.
Do not rely on RTL hierarchical net names in post-synth debug scripts.
Run timing/CDC/exceptions checks after every target migration update.
Use a repeatable program-capture checklist to detect intermittent reset/clock issues.