Traceability
Release Notes by Key Commit
Milestone notes keyed to major bring-up, debug, and documentation commits.
Commit timeline
| Commit | Title | Impact |
|---|---|---|
0773001 |
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring | New 46-check E2E testbench (tb_system_e2e.v) across 12 groups. RTL fixes: TX/RX mixer enables mutually exclusive by FSM state, USB write FSM data_pending sticky flags with stream-control reset default 3'b001, STM32 toggle signal wiring for mode-00, dynamic frame detection. USB tests 21/22/56 and regression script PASS/FAIL parsing fixed. 19/19 FPGA, 20/20 MCU. |
a3e1996 |
FFT engine: merge SHIFT into WRITE (4-cycle butterfly) + barrel-shift twiddle index | SHIFT state merged into WRITE for 5→4 cycle butterfly (20% throughput gain). Multiplier-based twiddle index replaced with barrel-shift (frees 1 DSP48). Verified via FFT testbench; no timing regression expected. |
7cdfa48 |
Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback | Runtime-configurable chirp timing (6 new opcodes 0x10-0x15), stream control gating (opcode 0x04 now gates USB write FSM), CFAR threshold wiring (opcode 0x03 replaces hardcoded value), status readback (opcode 0xFF returns 7-word packet). 4 new TB test groups. 18/18 FPGA, 20/20 MCU regression. |
e5d1b3c |
Gap 4 USB Read Path: host-to-FPGA command path with toggle CDC | Wired FT601 read FSM cmd_* outputs through toggle CDC to clk_100m command decode registers. Host can now set radar mode, trigger chirps, set CFAR threshold, and control data streaming. 3 new TB test groups (55 checks). 18/18 FPGA regression. |
c6103b3 v0.1.3-build20 |
Gap 7 MMCM jitter cleaner + CIC CREG pipeline + XDC clock-name fix | Added 400 MHz MMCM for ADC clock jitter cleaning, CIC comb DSP48E1 CREG pipeline, and fixed XDC conflicting generated clock. Build 20: WNS +0.426 ns (7x improvement over Build 18). All timing met. |
f3bbf77 |
Gap 3 Safety Architecture | IWDG watchdog, Emergency_Stop PA rail cutoff, temperature max guard, periodic IDQ re-read, emergency state ordering. 5 new MCU tests, 20/20 pass. |
c87dce0 |
Gap 5 BRAM async reset fix | Fixed chirp memory loader BRAM async reset to use synchronous reset pattern per Xilinx UG901 guidelines. |
3b7afba v0.1.2-build18 |
Build 18 production build | Production baseline: WNS +0.062 ns, WHS +0.059 ns. 6,088 LUTs, 8,946 FFs, 16 BRAM, 140 DSP48E1, 0.631 W. |
ed6f79c v0.1.1-build17 |
FIR DSP48 pipelining + matched filter BRAM migration | Build 17 production build with DSP48 pipelining improvements. |
c466021 |
Firmware bug sweep closure (B12-B17) | Closed the PA calibration, ADC buffer, DIAG macro, TIM3 PWM, and stale-diagnostic issues with additional MCU regression coverage. |
49c9aa2 |
SPI platform fix plus FPGA B2/B3 timing work | Fixed the legacy platform SPI transmit-only path and landed chirp BRAM migration plus Doppler DSP48 pipelining work. |
3b32f67 |
ADF4382A SPI and chip-select correctness | Fixed platform SPI ops wiring, added software-managed CS behavior, and widened SPI chip-select storage to handle STM32 pin values correctly. |
3979693 |
Initial 8-firmware-bug closure with tests | Closed the LO init ordering, AD9523 sequencing, sync trigger, temperature timer, GPIO mapping, and related MCU issues with regression coverage. |
Tagged releases
- v0.1.3-build20 (c6103b3) — Current production baseline. WNS +0.426 ns, all timing met. Includes Gaps 3, 5, 7.
- v0.1.2-build18 (3b7afba) — Prior production baseline. WNS +0.062 ns.
- v0.1.1-build17 (ed6f79c) — FIR DSP48 + BRAM migration build.
- v0.1.0-bringup — Initial bring-up tag.
Architectural gap status
| # | Gap | Status |
|---|---|---|
| 3 | Safety Architecture | Done (f3bbf77) |
| 5 | BRAM Async Reset | Done (c87dce0) |
| 7 | 400 MHz MMCM | Done (c6103b3, Build 20) |
| 4 | USB Read Path | Done (e5d1b3c) |
| 2 | GUI Settings | Done (7cdfa48) |
| 6 | CDC-15 USB Buses | Post-bring-up |
| 1 | CFAR Real Implementation | Post-bring-up |
Open in GitHub
- 0773001 E2E test + RTL fixes
- a3e1996 FFT engine optimizations
- 7cdfa48 Gap 2 GUI Settings
- e5d1b3c Gap 4 USB Read Path
- c6103b3 Gap 7 MMCM + CREG (v0.1.3-build20)
- f3bbf77 Gap 3 Safety Architecture
- c87dce0 Gap 5 BRAM Reset
- c466021 Firmware bugs B12-B17
- 49c9aa2 SPI + FPGA timing
- 3b32f67 ADF4382A SPI
- 3979693 Initial 8-bug closure