Artifacts

Published Reports and Visuals

Central access point for antenna simulations, implementation summaries, timing baselines, and board-day artifact references.

Open Board-Day Worksheet Open Bring-Up Plan

Current FPGA implementation status

Build 20 (v0.1.3-build20) is the current production baseline for the XC7A200T target. All timing constraints met: WNS +0.426 ns, WHS +0.058 ns, WPWS +0.361 ns.
Utilization: 6,092 LUTs (4.5%), 9,024 FFs (3.4%), 16 BRAM (4.4%), 140 DSP48E1 (18.9%), 0.730 W total power.
Key improvements over Build 18: 400 MHz MMCM jitter cleaner, CIC comb DSP48E1 CREG pipeline, XDC clock-name fix. Setup slack improved 7x.
Build 20 reports are available on the remote Vivado host at ~/PLFM_RADAR_work/vivado_project/reports_build20/.

Board-day artifact inventory

Artifact	Source path	Day-0 use	Status / note
Production-target XDC	`9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc`	Constraint source of truth for the production FPGA target	Tracked and validated after Build 16 cleanup port
FPGA programming flow	`9_Firmware/9_2_FPGA/scripts/program_fpga.tcl`	Programs the device and reports DONE / INIT_COMPLETE / probes presence	Primary operator-facing programming script
Debug probe insertion flow	`9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl`	Used when generating or refreshing debug-capable images	Keep matched with the selected debug bitstream
FPGA regression runner	`9_Firmware/9_2_FPGA/run_regression.sh`	Pre-arrival regression evidence for the tracked FPGA baseline	19 / 19 passing on the current tracked branch (includes E2E test)
MCU regression harness	`9_Firmware/9_1_Microcontroller/tests/Makefile`	Pre-arrival firmware regression evidence before flashing hardware	20 / 20 passing on the current tracked branch
Bring-up logging macros	`9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h`	Defines the main first-power-on log vocabulary used over USART3	Observation-only instrumentation layer
Board-day worksheet	`docs/board-day-worksheet.html`	Record pass/fail, measurements, and blockers during first sessions	Use with this page and the bring-up plan
Bring-up execution plan	`docs/bring-up.html`	Operator checklist, abort criteria, observability targets, and open risks	Primary readiness document

Antenna Simulation Report

Status: Mostly current (historical Phase-0 context)

File: AERIS_Antenna_Report.pdf

Notes: Valid for 10.5 GHz patch-element simulation and array projection context. Treat as element-level evidence, not full current hardware bring-up sign-off.

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Python Simulation Report

Status: Legacy (needs refresh)

File: AERIS_Simulation_Report.pdf

Notes: Contains older architecture assumptions (e.g., XC7A100T-centric narrative). Use as historical reference only until Simulation Report v2 is published.

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FPGA implementation analysis

Status: Current engineering baseline — Build 20 (v0.1.3-build20)

Build 20 is the current production baseline. Full timing, utilization, power, DRC, methodology, CDC, and route reports are available on the remote Vivado host. Setup slack improved 7x from Build 18 (+0.062 ns to +0.426 ns) via MMCM jitter cleaner, CIC CREG pipeline, and XDC clock-name fix.

Build 18 (v0.1.2-build18) retained as prior reference. Build 19 failed timing (WNS -0.011 ns) due to conflicting XDC generated clock, root-caused and fixed in Build 20.

Latest Simulation Report (Recommended)

Status: Current baseline (v2)

File: AERIS_Simulation_Report_v2.pdf

Aligned to the active project baseline: XC7A200T target, firmware regression closure, FPGA regression/timing gates, USB range-profile integration, and TE0712/TE0713 split-target flow.

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Report Currency Notice

The current routed production-target baseline is Build 20 (v0.1.3-build20) with all timing constraints met and 7x setup slack improvement over Build 18.
Architectural gaps 2 (GUI Settings), 3 (Safety), 4 (USB Read Path), 5 (BRAM Reset), and 7 (MMCM) are closed. Gaps 1 (CFAR) and 6 (CDC-15) remain for post-bring-up.
FPGA regression: 19/19 pass (includes new E2E integration test). MCU regression: 20/20 pass (15 bug-fix + 5 Gap-3 safety).
FFT engine optimized: 4-cycle butterfly (20% throughput gain) + barrel-shift twiddle index (frees 1 DSP48). Pending Vivado build verification.
Detailed Build 20 engineering reports are on the remote Vivado host at ~/PLFM_RADAR_work/vivado_project/reports_build20/.
The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.

Antenna concept snapshot