Artifacts
Central access point for antenna simulations, implementation summaries, timing baselines, and visuals.
ft601_txe methodology residue, and routed timing remained clean at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.ft601_txe methodology item currently behaves like an async-status-observation residue rather than a proven unconstrained functional FT601 path.Status: Mostly current (historical Phase-0 context)
File: AERIS_Antenna_Report.pdf
Notes: Valid for 10.5 GHz patch-element simulation and array projection context. Treat as element-level evidence, not full current hardware bring-up sign-off.
Status: Legacy (needs refresh)
File: AERIS_Simulation_Report.pdf
Notes: Contains older architecture assumptions (e.g., XC7A100T-centric narrative). Use as historical reference only until Simulation Report v2 is published.
Status: Current engineering baseline
Primary detailed write-up: internal Build 15 implementation analysis captured timing, power, route status, DRC, methodology, CDC, and utilization for the production-target design after USB range wiring and CFAR cleanup.
Follow-on Build 16 remote validation focused on production XDC cleanup only and confirmed no timing regression while reducing methodology noise substantially.
Status: Current baseline (v2)
File: AERIS_Simulation_Report_v2.pdf
Aligned to the active project baseline: XC7A200T target, firmware regression closure, FPGA regression/timing gates, USB range-profile integration, and TE0712/TE0713 split-target flow.
