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merge into: FlintyLemming/PLFM_RADAR:fix/invariant-p0-signal-processing
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FlintyLemming/PLFM_RADAR:main FlintyLemming/PLFM_RADAR:develop FlintyLemming/PLFM_RADAR:fix/mcu-fault-ack-emergency-clear FlintyLemming/PLFM_RADAR:fix/mcu-volatile-emergency-state-agc-holdoff FlintyLemming/PLFM_RADAR:fix/agc-gain-arithmetic-overflow FlintyLemming/PLFM_RADAR:fix/pre-bringup-audit-p0 FlintyLemming/PLFM_RADAR:fix/xdc-hardening-and-adc-pin-anchors FlintyLemming/PLFM_RADAR:fix/adar1000-channel-rotation FlintyLemming/PLFM_RADAR:fix/adar1000-vm-tables FlintyLemming/PLFM_RADAR:fix/invariant-p0-signal-processing FlintyLemming/PLFM_RADAR:fix/agc-cross-layer-enable FlintyLemming/PLFM_RADAR:feat/fft-2048-upgrade FlintyLemming/PLFM_RADAR:feat/ft2232h-default-ft601-option FlintyLemming/PLFM_RADAR:feat/um982-gps-driver FlintyLemming/PLFM_RADAR:revert-68-feature/add-um982-gps-driver FlintyLemming/PLFM_RADAR:feat/agc-fpga-gui FlintyLemming/PLFM_RADAR:fix/ruff-lint-full-repo
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pull from: FlintyLemming/PLFM_RADAR:fix/pre-bringup-audit-p0
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FlintyLemming/PLFM_RADAR:main FlintyLemming/PLFM_RADAR:develop FlintyLemming/PLFM_RADAR:fix/mcu-fault-ack-emergency-clear FlintyLemming/PLFM_RADAR:fix/mcu-volatile-emergency-state-agc-holdoff FlintyLemming/PLFM_RADAR:fix/agc-gain-arithmetic-overflow FlintyLemming/PLFM_RADAR:fix/pre-bringup-audit-p0 FlintyLemming/PLFM_RADAR:fix/xdc-hardening-and-adc-pin-anchors FlintyLemming/PLFM_RADAR:fix/adar1000-channel-rotation FlintyLemming/PLFM_RADAR:fix/adar1000-vm-tables FlintyLemming/PLFM_RADAR:fix/invariant-p0-signal-processing FlintyLemming/PLFM_RADAR:fix/agc-cross-layer-enable FlintyLemming/PLFM_RADAR:feat/fft-2048-upgrade FlintyLemming/PLFM_RADAR:feat/ft2232h-default-ft601-option FlintyLemming/PLFM_RADAR:feat/um982-gps-driver FlintyLemming/PLFM_RADAR:revert-68-feature/add-um982-gps-driver FlintyLemming/PLFM_RADAR:feat/agc-fpga-gui FlintyLemming/PLFM_RADAR:fix/ruff-lint-full-repo

60 Commits
fix/invariant-p0-signal-processing .. fix/pre-bringup-audit-p0

Author SHA1 Message Date
Jason f0f0f1477f Merge remote-tracking branch 'origin/main' into fix/pre-bringup-audit-p0 2026-04-21 01:33:19 +05:45
Jason ca8c5862a7 chore: regenerate uv.lock 2026-04-21 01:09:38 +05:45
Jason 25a280c200 refactor(mcu): remove redundant ADAR1000 T/R SPI paths (FPGA-owned) 
Per-chirp T/R switching is owned by the FPGA plfm_chirp_controller
driving adar_tr_x pins (TR_SOURCE=1 in REG_SW_CONTROL, already set by
initializeSingleDevice). The MCU's SPI RMW path via fastTXMode/
fastRXMode/pulseTXMode/pulseRXMode/setADTR1107Control was:
  (a) architecturally redundant — raced the FPGA-driven TR line,
  (b) toggled the wrong bit (TR_SOURCE instead of TR_SPI),
  (c) in setFastSwitchMode(true) bundled a datasheet-violating
      PA+LNA-simultaneously-biased side effect.

Removed methods and their backing state (fast_switch_mode_,
switch_settling_time_us_). Call sites in executeChirpSequence /
runRadarPulseSequence updated to rely on the FPGA chirp FSM (GPIOD_8
new_chirp trigger unchanged).

Tests: adds CMSIS-Core DWT/CoreDebug/SystemCoreClock stubs to
stm32_hal_mock so F-4.7's DWT-based delayUs() compiles under the host
mock build. SystemCoreClock=0 makes the busy-wait exit immediately.
 2026-04-21 01:09:38 +05:45
NawfalMotii79 33d21da7f2 Remove radar system image from README 
Removed the AERIS-10 Radar System image from the README.
 2026-04-20 19:04:08 +01:00
Jason 1a7bd7e971 Merge branch 'NawfalMotii79:fix/pre-bringup-audit-p0' into fix/pre-bringup-audit-p0 2026-04-20 20:51:30 +03:00
Jason 8b4de5f9ee fix(fpga): extend ADC hold waiver to include adc_or_p (F-0.1 follow-up) 
adc_or_p (overrange pin, added in commit 70067c6 for audit finding F-0.1)
uses the same IBUFDS→BUFIO source-synchronous capture topology as the 8
data pins adc_d_p[*]. STA reports identical -1.913 ns hold on this path
for the same reason (clock insertion ~4.0 ns via BUFIO vs data IBUFDS
~0.9 ns). External PCB layout guarantees hold, not FPGA clock tree.

Extends the existing adc_d_p[*] false_path waiver to cover adc_or_p.
Post-route now clean: WNS +0.034 ns, WHS positive.
 2026-04-20 23:28:58 +05:45
Jason 0496291fc5 fix(fpga): F-0.9 option B — FT2232H output_delay 11.667→3.5 ns (TN_167) 
Previous output_delay of 11.667 ns was a synthetic back-calculation
(period − 5 ns), not a datasheet number. It over-constrained FPGA
launch by ~8 ns vs the actual FT2232H 245-Sync FIFO setup requirement.

Per FTDI TN_167:
- t_su (data to CLKOUT rising):  3.5 ns  (was 11.667 — too tight)
- t_h  (data hold after CLKOUT): 1.0 ns  (was 0.0 — no hold check)
- t_co (CLKOUT to data valid):   10.0 ns (was 9.667 — close)
- t_coh (CLKOUT to data hold):   0.5 ns  (was 0.0 — no hold check)

NB: values must be verified against the exact TN_167 revision in use
before shipping. If the engineer's revision differs, numbers change
but the direction (big relaxation of output_delay_max) is correct.
 2026-04-20 21:47:26 +05:45
Jason bec578a5e7 Revert "fix(fpga): F-0.9 option A — BUFIO+BUFR for 50T ft_clkout (SRCC pin)" 
This reverts commit 30279e8c4d.
 2026-04-20 21:47:19 +05:45
Jason 3b666ac47f Revert "fix(fpga): move IBUF+BUFIO+BUFR into 50T wrapper (same scope as pad)" 
This reverts commit 813ee4c962.
 2026-04-20 21:47:19 +05:45
Jason 813ee4c962 fix(fpga): move IBUF+BUFIO+BUFR into 50T wrapper (same scope as pad) 
The previous attempt put BUFIO inside u_core/gen_ft_bufr, but the pad
(ft_clkout) and its inferred IBUF live at the top wrapper level. Vivado
shape-packs IBUF↔BUFIO into the same IOB tile, and it couldn't do that
across the wrapper→u_core hierarchy boundary — producing CRITICAL
WARNING [12-1411] "Illegal to place BUFIO on TIEOFF site" and WNS=-5.737
(worse than the CLOCK_DEDICATED_ROUTE=FALSE baseline).

Fix: instantiate IBUF+BUFIO+BUFR explicitly in radar_system_top_50t.v
and pass the BUFR output into u_core.ft601_clk_in. radar_system_top.v
now does a pass-through wire assign for USB_MODE=1 (no BUFG) so the
clock net doesn't get double-buffered.
 2026-04-20 21:02:56 +05:45
Jason 30279e8c4d fix(fpga): F-0.9 option A — BUFIO+BUFR for 50T ft_clkout (SRCC pin) 
C4 is an SRCC pin (IS_CLK_CAPABLE=1, IS_MASTER=0 in the Vivado device
model), not an MRCC as earlier comments claimed. SRCC cannot drive BUFG
through dedicated routing, so the previous CLOCK_DEDICATED_ROUTE=FALSE
override forced fabric routing and burned ~5 ns on the ft_clkout path
(WNS -5.362 ns in the d36a4c9 build).

Swap to BUFIO + BUFR for USB_MODE=1 (50T/FT2232H): SRCC → BUFIO → BUFR
is the standard 7-series path for regional clock distribution. All
ft_clkout-domain logic (FT2232H FSM, toggle CDCs, USB FIFO flops) is
contained in bank 35 / one clock region, so regional distribution is
sufficient. USB_MODE=0 (200T/FT601) keeps the BUFG because D17 is a
proper MRCC pin.

Removed CLOCK_DEDICATED_ROUTE=FALSE from both the XDC and the build
script — no longer needed with dedicated BUFIO/BUFR routing.
 2026-04-20 20:53:49 +05:45
Jason d36a4c93e2 fix(fpga): audit F-2026-04-20-A/B — CIC reset fan-out + BUFIO→BUFG max_delay 
A: cic_decimator_4x_enhanced.v reset_h max_fanout 50→25. More replicas
mean each drives fewer DSP48 RSTB loads, letting Vivado place each
closer to its consumers. Targets the rep__24 → comb_reg[4]/RSTB path
that failed clk_mmcm_out0 intra by -10 ps (1.4 ns of pure routing).

B: adc_clk_mmcm.xdc BUFIO↔BUFG max_delay 2.500→2.700 ns. The 2.5 ns
target was tighter than achievable for the IDDR (ILOGIC) → FDRE (fabric
SLICE) re-registration. The effective window is the BUFIO↔BUFG phase
relationship (not the clock period), so 2.7 ns remains safe. Fixes the
adc_dco_p→clk_mmcm_out0 inter path -113 ps failure on lane 7.
 2026-04-20 20:20:43 +05:45
Jason bf89984f04 Revert "fix(fpga): IOB=TRUE on FT2232H pads to meet 5 ns FPGA launch budget" 
This reverts commit 94bf6944a3.
 2026-04-20 20:20:02 +05:45
Jason 94bf6944a3 fix(fpga): IOB=TRUE on FT2232H pads to meet 5 ns FPGA launch budget 
Post-route WNS = -5.355 ns on path group ft_clkout, net
  u_core/gen_ft2232h.usb_inst/ft_data_TRI[0]_repN_1

FT2232H 245-sync FIFO input setup (t_su = 11.667 ns on a 16.667 ns
CLKOUT) leaves the FPGA only ~5 ns from clock edge to pad. Without
IOB=TRUE, the output / tristate FFs live in fabric and FF→OBUFT
routing eats 2–3 ns, forcing Vivado to replicate the tristate
driver (ft_data_TRI[*]_repN) and still miss timing.

The FSM in usb_data_interface_ft2232h.v already registers
ft_data_out / ft_data_oe / ft_{rd,wr,oe}_n at the output boundary
in the ft_clk domain, so packing them into the IOB is safe with
no RTL change.
 2026-04-20 16:43:12 +05:45
Jason 0067969ee7 fix(fpga): wire F-0.1 adc_or_p/n through 50T wrapper + remove xdc control-flow 
Build-blocking fixes surfaced by gpu-server synth:

1. radar_system_top_50t.v wrapper was missing adc_or_p/n ports and the
   u_core instantiation left them unconnected. Every XDC line in the 50T
   anchor block (PACKAGE_PIN M6/N6, IOSTANDARD, DIFF_TERM, set_input_delay)
   therefore matched no ports and emitted CRITICAL WARNINGs, leaving the
   overrange pin effectively tied off. Added the two inputs and wired them
   through to the core.

2. adc_clk_mmcm.xdc used foreach / unset — Vivado's XDC parser only
   accepts a restricted Tcl subset and rejected them as
   [Designutils 20-1307]. Moved the clk_mmcm_out0 ↔ USB-clock false paths
   into each board XDC (ft_clkout for 50T, ft601_clk_in for 200T) where
   the clock name is already known.
 2026-04-20 16:08:13 +05:45
Jason 51740fd6f5 test(fpga): F-3.2 add DDC cosim fuzz runner with seed sweep 
A new SCENARIO_FUZZ branch in tb_ddc_cosim.v accepts +hex / +csv / +tag
plusargs so an external runner can pick stimulus and output paths per
iteration. The three path registers are widened to 4 kbit each so long
temp-directory paths (e.g. /private/var/folders/...) do not overflow
the MSB and emerge truncated — a real failure mode caught while writing
this runner.

test_ddc_cosim_fuzz.py is a pytest-driven fuzz harness:
 - Generates a random plausible radar scene per seed (1-4 targets with
   random range/velocity/RCS/phase, random noise level 0.5-6.0 LSB
   stddev) via radar_scene.generate_adc_samples, fully deterministic.
 - Compiles tb_ddc_cosim.v once per session (module-scope fixture),
   then runs vvp per seed.
 - Asserts sample-count bounds consistent with 4x CIC decimation,
   signed-18 range on every baseband I/Q word, and non-zero output
   (catches silent pipeline stalls).
 - Ships with two tiers: test_ddc_fuzz_fast (8 seeds, default CI) and
   test_ddc_fuzz_full (100 seeds, opt-in via -m slow) matching the
   audit ask.

Registers the "slow" marker in pyproject.toml for the 100-seed opt-in.
 2026-04-20 15:48:34 +05:45
Jason b588e89f67 test(fpga): F-2.2 adversarial mid-frame reset sweep + F-0.1 TB plumbing 
G9B adds a 4-iteration reset sweep on top of the existing e2e harness:
- Reset is injected at four offsets (3/7/12/18 us) into a steady-state
  auto-scan burst, with mixed short/long hold durations (20-120 clk_100m)
  to exercise asynchronous assert paths through the FSM + CDCs.
- Each iteration asserts: system_status drops to 0 during reset,
  new_chirp_frame resumes post-release, and obs_range_valid_count
  advances — proving the full DDC->MF chain recovers, not just the
  transmitter FSM.

The stub and three existing testbenches are updated to drive the new
adc_or_p/n ports tied to 1'b0/1'b1, matching the F-0.1 RTL change.
 2026-04-20 15:48:34 +05:45
Jason 70067c6121 fix(fpga): F-0.1 wire AD9484 OR overrange pin into diagnostics 
The AD9484 OR (overrange) LVDS pair is routed on the 50T main board to
xc7a50t-ftg256 bank-14 pins M6/N6 but was previously left unconnected at
the top level. Plumb it through the full stack so saturation at the raw
ADC boundary shows up in the existing overflow aggregation:

- ad9484_interface_400m: add adc_or_p/n inputs, IBUFDS + IDDR capture of
  both phases in the BUFIO domain, re-register into the clk_400m BUFG
  domain, OR rise|fall into adc_overrange_400m output.
- radar_receiver_final: stickify adc_overrange_400m in clk_400m, CDC to
  clk_100m via a 2FF ASYNC_REG chain (same reasoning as F-1.2's
  cdc_cic_fir_overrun — single-bit, latched low→high, GPIO-class
  diagnostic), OR into the existing ddc_overflow_any aggregation.
- radar_system_top: expose adc_or_p/n top-level ports and pass through.
- xc7a50t_ftg256.xdc: anchor M6/N6 as LVDS_25 DIFF_TERM, with the same
  DCO-relative input-delay constraints as adc_d_p[*].
- xc7a200t_fbg484.xdc: IOSTANDARD/DIFF_TERM set; PACKAGE_PIN left as a
  documented TODO — the 200T dev-board schematic has not been checked
  and the 200T build will need the anchor filled in before place/route.
 2026-04-20 15:48:34 +05:45
Jason 356acea314 fix(adar): F-4.1 lower broadcast writes to per-device unicast loop 
The `broadcast=1` path on adarWrite() emitted the 0x08 broadcast opcode
but setChipSelect() only asserts one device's CS line, so only the single
selected chip ever saw the frame. The opcode path has also never been
validated on silicon. Until a HIL test confirms multi-CS semantics, route
broadcast=1 through a unicast loop over all devices so caller intent
(all four take the write) is preserved and the dead opcode path becomes
unreachable. Logs a DIAG_WARN on entry for visibility.
 2026-04-20 15:48:34 +05:45
Jason b250eff978 test(fpga): F-3.2 add DDC cosim fuzz runner with seed sweep 
A new SCENARIO_FUZZ branch in tb_ddc_cosim.v accepts +hex / +csv / +tag
plusargs so an external runner can pick stimulus and output paths per
iteration. The three path registers are widened to 4 kbit each so long
temp-directory paths (e.g. /private/var/folders/...) do not overflow
the MSB and emerge truncated — a real failure mode caught while writing
this runner.

test_ddc_cosim_fuzz.py is a pytest-driven fuzz harness:
 - Generates a random plausible radar scene per seed (1-4 targets with
   random range/velocity/RCS/phase, random noise level 0.5-6.0 LSB
   stddev) via radar_scene.generate_adc_samples, fully deterministic.
 - Compiles tb_ddc_cosim.v once per session (module-scope fixture),
   then runs vvp per seed.
 - Asserts sample-count bounds consistent with 4x CIC decimation,
   signed-18 range on every baseband I/Q word, and non-zero output
   (catches silent pipeline stalls).
 - Ships with two tiers: test_ddc_fuzz_fast (8 seeds, default CI) and
   test_ddc_fuzz_full (100 seeds, opt-in via -m slow) matching the
   audit ask.

Registers the "slow" marker in pyproject.toml for the 100-seed opt-in.
 2026-04-20 15:45:09 +05:45
Jason 40c5cabdcf test(fpga): F-2.2 adversarial mid-frame reset sweep + F-0.1 TB plumbing 
G9B adds a 4-iteration reset sweep on top of the existing e2e harness:
- Reset is injected at four offsets (3/7/12/18 us) into a steady-state
  auto-scan burst, with mixed short/long hold durations (20-120 clk_100m)
  to exercise asynchronous assert paths through the FSM + CDCs.
- Each iteration asserts: system_status drops to 0 during reset,
  new_chirp_frame resumes post-release, and obs_range_valid_count
  advances — proving the full DDC->MF chain recovers, not just the
  transmitter FSM.

The stub and three existing testbenches are updated to drive the new
adc_or_p/n ports tied to 1'b0/1'b1, matching the F-0.1 RTL change.
 2026-04-20 15:37:06 +05:45
Jason 951390f678 fix(fpga): F-0.1 wire AD9484 OR overrange pin into diagnostics 
The AD9484 OR (overrange) LVDS pair is routed on the 50T main board to
xc7a50t-ftg256 bank-14 pins M6/N6 but was previously left unconnected at
the top level. Plumb it through the full stack so saturation at the raw
ADC boundary shows up in the existing overflow aggregation:

- ad9484_interface_400m: add adc_or_p/n inputs, IBUFDS + IDDR capture of
  both phases in the BUFIO domain, re-register into the clk_400m BUFG
  domain, OR rise|fall into adc_overrange_400m output.
- radar_receiver_final: stickify adc_overrange_400m in clk_400m, CDC to
  clk_100m via a 2FF ASYNC_REG chain (same reasoning as F-1.2's
  cdc_cic_fir_overrun — single-bit, latched low→high, GPIO-class
  diagnostic), OR into the existing ddc_overflow_any aggregation.
- radar_system_top: expose adc_or_p/n top-level ports and pass through.
- xc7a50t_ftg256.xdc: anchor M6/N6 as LVDS_25 DIFF_TERM, with the same
  DCO-relative input-delay constraints as adc_d_p[*].
- xc7a200t_fbg484.xdc: IOSTANDARD/DIFF_TERM set; PACKAGE_PIN left as a
  documented TODO — the 200T dev-board schematic has not been checked
  and the 200T build will need the anchor filled in before place/route.
 2026-04-20 15:32:23 +05:45
Jason eb8189a7f1 fix(adar): F-4.1 lower broadcast writes to per-device unicast loop 
The `broadcast=1` path on adarWrite() emitted the 0x08 broadcast opcode
but setChipSelect() only asserts one device's CS line, so only the single
selected chip ever saw the frame. The opcode path has also never been
validated on silicon. Until a HIL test confirms multi-CS semantics, route
broadcast=1 through a unicast loop over all devices so caller intent
(all four take the write) is preserved and the dead opcode path becomes
unreachable. Logs a DIAG_WARN on entry for visibility.
 2026-04-20 15:27:00 +05:45
Jason 902f88a8df Merge branch 'NawfalMotii79:main' into fix/pre-bringup-audit-p0 2026-04-20 12:01:28 +03:00
Jason 675b1c0015 fix(pre-bringup): second-batch P1/P2/P3 audit findings 
Addresses the remaining actionable items from
docs/DEVELOP_AUDIT_2026-04-19.md after commit 3f47d1e.

XDC (dead waivers — F-0.4, F-0.5, F-0.6, F-0.7):
- ft_clkout_IBUF CLOCK_DEDICATED_ROUTE now uses hierarchical filter;
  flat net name did not exist post-synth.
- reset_sync_reg[*] false-path rewritten to walk hierarchy and filter
  on CLR/PRE pins.
- adc_clk_mmcm.xdc ft601_clk_in references replaced with foreach-loop
  over real USB clock names, gated on -quiet existence.
- MMCM LOCKED waiver uses REF_PIN_NAME filter instead of the
  previously-missing u_core/ literal path.

CDC (F-1.1, F-1.2, F-1.3):
- Documented the quasi-static-bus stability invariant above the
  FT601 cmd_valid toggle block.
- cdc_adc_to_processing gains an `overrun` output; the two CIC->FIR
  instances feed a sticky cdc_cic_fir_overrun flag surfaced on
  gpio_dig5 so silent sample drops become visible to the MCU.
- Removed the dead mixers_enable synchronizer in ddc_400m.v; the _sync
  output was unused and every caller ties the port to 1'b1.

Diagnostics (F-6.4):
- range_bin_decimator watchdog_timeout plumbed through receiver
  and top-level, OR'd into gpio_dig5.

ADAR (F-4.7):
- delayUs() replaced with DWT cycle counter; self-initialising
  TRCENA/CYCCNTENA, overflow-safe unsigned subtraction.

Regression: tb_cdc_modules.v 57/57 passes under iverilog after
the cdc_modules.v change. Remote Vivado verification in progress.
 2026-04-20 14:28:22 +05:45
Jason 3f47d1ef71 fix(pre-bringup): resolve P0 + quick-win P1 findings from 2026-04-19 audit 
Addresses findings from docs/DEVELOP_AUDIT_2026-04-19.md:

P0 source-level:
- F-4.3 ADAR1000_Manager::adarSetTxPhase now writes REG_LOAD_WORKING
  with LD_WRK_REGS_LDTX_OVERRIDE (0x02) instead of 0x01. Previous value
  toggled the LDRX latch on a TX-phase write, so host TX phase updates
  never reached the working registers.
- F-6.1 DDC mixer_saturation / filter_overflow / diagnostics were deleted
  at the receiver boundary. Now plumbed to new outputs on
  radar_receiver_final (ddc_overflow_any, ddc_saturation_count) and
  aggregated into gpio_dig5 in radar_system_top. Added mark_debug
  attributes for ILA visibility. Test/debug inputs tied low explicitly.
- F-0.8 adc_clk_mmcm.xdc set_clock_uncertainty: removed invalid -add
  flag (Vivado silently rejected it, applying zero guardband). Now uses
  absolute 0.150 ns which covers 53 ps jitter + ~100 ps PVT margin.

P1:
- F-4.2 adarSetBit / adarResetBit reject broadcast=ON — the RMW sampled
  a single device but wrote to all four, clobbering the other three's
  state.
- F-4.4 initializeSingleDevice returns false and leaves initialized=false
  when scratchpad verification fails; previously marked the device
  initialized anyway so downstream PA enable could drive a dead bus.
- F-6.2 FIR I/Q filter_overflow ports, previously unconnected, now OR'd
  into the module-level filter_overflow output.
- F-6.3 mti_canceller exposes 8-bit saturation counter. Saturation was
  previously invisible and produces spurious Doppler harmonics.

Verification:
- 27/27 iverilog testbenches pass
- 228/228 pytest pass (cross-layer contract + cosim)
- MCU unit tests 51/51 + 24/24 pass
- Remote Vivado 2025.2 build: bitstream writes; 400 MHz mixer pipeline
  now shows WNS -0.109 ns which MATCHES the audit's F-0.9 prediction
  that the design only closed because F-0.8's guardband was silently
  dropped. ft_clkout F-0.9 remains a show-stopper (requires MRCC pin
  move), tracked separately.

Not addressed in this PR (larger scope, follow-up tickets):
F-0.4, F-0.5, F-0.6, F-0.7, F-0.9, F-1.1, F-1.2, F-2.2, F-3.2, F-4.1,
F-4.7, F-6.4, F-6.5.
 2026-04-20 13:48:36 +05:45
NawfalMotii79 18901be04a Fix image link and update mixer model in README 
Updated image link and corrected mixer model in specifications.
 2026-04-19 19:06:44 +01:00
NawfalMotii79 9f899b96e9 Add files via upload 2026-04-19 19:04:48 +01:00
Jason c82b25f7a0 Merge pull request #113 from NawfalMotii79/fix/adar1000-channel-rotation 
fix: ADAR1000 channel indexing + 400 MHz reset fan-out
 2026-04-19 14:05:50 +03:00
Jason 2539d46d93 merge: resolve conflicts with develop (supersede by PR #89 / #107) 
Three conflicts — all resolved in favor of develop, which has a more
refined version of the same work this branch introduced:

- radar_system_top.v: develop's cleaner USB_MODE=1 comment (same value).
- run_regression.sh: develop's ${SYSTEM_RTL[@]} refactor + added
  USB_MODE=1 test variants.
- tb/radar_system_tb.v: develop's ifdef USB_MODE_1 to dump the correct
  USB instance based on mode.

The 400 MHz reset fan-out fix (nco_400m_enhanced, cic_decimator_4x_enhanced,
ddc_400m) and ADAR1000 channel-indexing fix remain intact on this branch.
 2026-04-19 16:28:07 +05:45
NawfalMotii79 88ca1910ec Merge pull request #109 from NawfalMotii79/develop 
Release: merge develop into main
 2026-04-19 01:27:15 +01:00
Jason d0b3a4c969 fix(fpga): registered reset fan-out at 400 MHz; default USB to FT2232H 
Replace direct !reset_n async sense with a registered active-high reset_h
(max_fanout=50) in nco_400m_enhanced, cic_decimator_4x_enhanced, and
ddc_400m.  The prior single-LUT1 / 700+ load net was the root cause of
WNS=-0.626 ns in the 400 MHz clock domain on the xc7a50t build.  Vivado
replicates the constrained register into ≈14 regional copies, each driving
≤50 loads, closing timing at 2.5 ns.

Change radar_system_top default USB_MODE from 0 (FT601) to 1 (FT2232H).
FT601 remains available for the 200T premium board via explicit parameter
override; the 50T production wrapper already hard-codes USB_MODE=1.

Regression: add usb_data_interface_ft2232h.v to PROD_RTL lint list and
both system-top TB compile commands; fix legacy radar_system_tb hierarchical
probe from gen_ft601.usb_inst to gen_ft2232h.usb_inst.

Golden reference files (rtl_bb_dc.csv, rx_final_doppler_out.csv,
golden_doppler.mem) regenerated to reflect the +1-cycle registered-reset
boundary behaviour; Receiver golden-compare passes 18/18 checks.

All 25 regression tests pass (0 failures, 0 skipped).

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
 2026-04-18 20:34:52 +05:45
Jason 2f5ddbd8a3 Merge pull request #110 from joyshmitz/docs/contributing-ai-usage-policy 
docs(contributing): add AI usage policy section (from #106)
 2026-04-18 16:46:30 +03:00
Serhii aa5d712aea docs(contributing): add AI usage policy section (closes #106 discussion) 
Surfaces the three-point AI usage policy Jason articulated in #106 by
placing it in CONTRIBUTING.md between "Code Standards & Tooling" and
"Running the Test Suites", so first-time AI-assisted contributors see
the expectation in the onboarding doc rather than having to discover
it via issue archaeology. Text is the #106 comment verbatim with two
small typo fixes only (use if AI -> use of AI; doesnt -> doesn't); no
structural or stylistic rewriting.

Per Jason's green light to open this PR in
NawfalMotii79/PLFM_RADAR#106 (comment-4273144522).
 2026-04-18 10:51:36 +03:00
Jason 475f390a13 docs: rewrite CONTRIBUTING.md with updated workflow and standards 2026-04-18 09:45:34 +05:45
Jason 0731aae2bc docs(readme): update features to list Hybrid AGC 2026-04-18 09:30:17 +05:45
Jason e62abc9170 fix(readme): point dashboard image to existing GUI_V6.gif 2026-04-18 09:28:26 +05:45
Jason 582476fa0d fix(adar1000): correct 1-based channel indexing in setters (issue #90) 
The four channel-indexed ADAR1000 setters (adarSetRxPhase, adarSetTxPhase,
adarSetRxVgaGain, adarSetTxVgaGain) computed their register offset as
`(channel & 0x03) * stride`, which silently aliased CH4 (channel=4 ->
mask=0) onto CH1 and shifted CH1..CH3 by one. The API contract (1-based
CH1..CH4) is documented in ADAR1000_AGC.cpp:76 and matches the ADI
datasheet; every existing caller already passes `ch + 1`.

Fix: subtract 1 before masking -- `((channel - 1) & 0x03) * stride` --
and reject `channel < 1 || channel > 4` early with a DIAG message so a
future stale 0-based caller fails loudly instead of writing to CH4.

Adds TestTier1Adar1000ChannelRegisterRoundTrip (9 tests) which closes
the loop independently of the driver:
  - parses the ADI register map directly from ADAR1000_Manager.h,
  - verifies the datasheet stride invariants (gain=1, phase=2),
  - auto-discovers every C++ TU under MCU_LIB_DIR / MCU_CODE_DIR so a
    new caller cannot silently escape the round-trip check,
  - asserts every caller's channel argument evaluates to {1,2,3,4} for
    ch in {0,1,2,3} (catches bare 0-based or literal-0 callers at CI
    time before the runtime bounds-check would silently drop them),
  - round-trips each (caller, ch) through the helper arithmetic and
    checks the final address equals REG_CH{ch+1}_*.

Adversarially validated: reverting any one helper, all four helpers,
corrupting the parsed register map, injecting a bare-ch caller, and
auto-discovering a literal-0 caller in a fresh TU each cause the
expected (and only the expected) test to fail.

Stacked on fix/adar1000-vm-tables (PR #107).
 2026-04-18 06:39:07 +05:45
NawfalMotii79 d3476139e3 Merge pull request #89 from NawfalMotii79/feat/ft2232h-default-ft601-option 
feat: make FT2232H default USB interface, add FT601 premium option, deprecate GUI V6
 2026-04-17 22:21:58 +01:00
NawfalMotii79 8fac1cc1a0 Merge pull request #107 from NawfalMotii79/fix/adar1000-vm-tables 
fix(adar1000): populate VM_I/VM_Q phase tables; remove dead VM_GAIN
 2026-04-17 21:58:59 +01:00
Jason 7c91a3e0b9 fix(adar1000): populate VM_I/VM_Q phase tables; remove dead VM_GAIN 
The ADAR1000 vector-modulator I/Q lookup tables VM_I[128] and VM_Q[128]
were declared but defined as empty initialiser lists since the first
commit (5fbe97f). Every call to adarSetRxPhase / adarSetTxPhase therefore
wrote (I=0x00, Q=0x00) to registers 0x21/0x23 (Rx) and 0x32/0x34 (Tx)
regardless of the requested phase state, leaving beam steering completely
non-functional in firmware.

This commit:

* Populates VM_I[128] and VM_Q[128] from ADAR1000 datasheet Rev. B
  Tables 13-16 (p.34) on a uniform 2.8125 deg grid (360 / 128 states).
  Byte format: bits[7:6] reserved 0, bit[5] polarity (1 = positive
  lobe), bits[4:0] 5-bit unsigned magnitude - exactly as specified.
* Removes VM_GAIN[128] declaration and (empty) definition. The
  ADAR1000 has no separate VM gain register; per-channel VGA gain is
  set via CHx_RX_GAIN (0x10-0x13) / CHx_TX_GAIN (0x1C-0x1F) by
  adarSetRxVgaGain / adarSetTxVgaGain. VM_GAIN was never populated,
  never read anywhere in the firmware, and its presence falsely
  suggested a missing scaling step in the signal path.
* Adds 9_Firmware/tests/cross_layer/adar1000_vm_reference.py: an
  independently-derived ground-truth module containing the full
  datasheet table plus byte-format / uniform-grid / quadrant-symmetry
  / cardinal-point invariant checkers and a tolerant C array parser.
* Adds TestTier2Adar1000VmTableGroundTruth (9 tests) to
  test_cross_layer_contract.py, including a tokenising C/C++
  comment+string stripper used by the VM_GAIN reintroduction guard,
  and an adversarial self-test that corrupts one byte and asserts
  the comparison detects it (defends against silent bypass via
  future fixture/parser refactors).

Adversarially validated: removing the firmware definitions, flipping
a single byte, or reintroducing VM_GAIN as code each cause the suite
to fail; restoring causes it to pass. VM_GAIN appearing inside string
literals or comments correctly does NOT trip the guard.

Closes the empty-table half of the ADAR1000 phase-control bug class.
The separate channel-rotation issue (#90) will be addressed in a
follow-up PR.

Refs: 7_Components Datasheets and Application notes/ADAR1000.pdf
      Rev. B Tables 13-16 p.34
 2026-04-18 02:02:07 +05:45
Jason fd6cff5b2b Merge pull request #102 from JJassonn69/chore/sync-main-into-develop 
chore: sync main → develop (schematic updates + README + project doc)
 2026-04-17 19:31:31 +03:00
Jason 964f1903f3 chore: sync main → develop (schematic updates, README, project doc) 
Brings in main-only commits that never reached develop:
  754d919 Added silk screen and headers description (MainBoard .brd)
  0443516 Added thermal vias (RF_PA .brd)
  5fbe051 Added ABAC INDUSTRY web site (Project_Description.docx)
  12b549d / 5d5e9ff Merge PR #101: README BOM sensor counts fix

No conflicts expected: develop has not touched any of these paths.
 2026-04-17 22:12:26 +05:45
Jason 12b549dafb Merge pull request #101 from JJassonn69/fix/readme-bom-sensor-counts 
docs(readme): correct STM32 peripheral counts and locations to match production BOM
 2026-04-17 17:21:59 +03:00
Jason 5d5e9ff297 docs(readme): correct BOM sensor counts and locations 
The STM32 peripheral list in the README disagreed with the production
BOM (4_7_Production Files/Gerber_Main_Board/RADAR_Main_Board_BOM_csv)
and with the firmware (9_1_Microcontroller/.../main.cpp). Corrections
based on origin/main commit 754d919:

- ADS7830 Idq ADCs: placed on the Main Board (U88 @ 0x48, U89 @ 0x4A),
  not on the Power Amplifier Boards. Added the INA241A3 (x50) and 5 mOhm
  shunt detail that completes the current-sense chain.
- DAC5578 Vg DACs: placed on the Main Board (U7 @ 0x48, U69 @ 0x49),
  not on the Power Amplifier Boards. Noted closed-loop Idq calibration
  at boot (main.cpp powerUpSequence).
- Temperature sensors: 1x ADS7830 (U10) with 8 single-ended channels
  reading 8 thermistors -- not 8 separate ADS7830 chips. Cooling is a
  single GPIO (EN_DIS_COOLING), bang-bang, not PWM.
- GPS: reflect the UM982 driver merged in #79 and its role in
  per-detection position tagging beyond map centering.

Counts now match the 3x ADS7830 / 2x DAC5578 / 16x INA241A3 population
in the production BOM.
 2026-04-17 20:04:01 +05:45
NawfalMotii79 754d919e44 Added silk screen and headers description 2026-04-16 23:48:23 +01:00
NawfalMotii79 0443516cc9 Added thermal vias 2026-04-16 23:47:24 +01:00
NawfalMotii79 5fbe0513b5 Added ABAC INDUSTRY web site 2026-04-16 23:46:08 +01:00
Jason c3db8a9122 Merge pull request #96 from joyshmitz/chore/remove-dead-adar1000-c-api 
chore(mcu): remove dead C-style adar1000 driver
 2026-04-16 23:51:22 +03:00
Jason ec8256e25a Merge pull request #95 from joyshmitz/test/agc-debounce-enforce 
test(cross-layer): enforce 2-frame DIG_6 debounce guard on outerAgc.enabled (follow-up to #93)
 2026-04-16 23:42:12 +03:00
Serhii 8e1b3f22d2 chore(mcu): remove dead C-style adar1000 driver 
The firmware uses the C++ ADAR1000_Manager class exclusively. The C-style
driver pair (adar1000.c, 693 LoC; adar1000.h, 294 LoC) has no external
call sites:

  grep -rn "Adar_Set|Adar_Read|Adar_Write|Adar_Soft" 9_Firmware
  grep -rn "AdarDevice|AdarBiasCurrents|AdarDeviceInfo" 9_Firmware

Both return hits only inside adar1000.c/h themselves. ADAR1000_Manager.h
has its own copies of REG_CH1_*, REG_INTERFACE_CONFIG_A, etc. and does
not include adar1000.h. main.cpp had a lone #include "adar1000.h" but
referenced no symbols from it; the REG_* macros it uses resolve through
ADAR1000_Manager.h on the next line.

No behaviour change: the deleted code was unreachable.

Side note on #90: adar1000.c contained a second copy of the
REG_CH1_* + (channel & 0x03) channel-rotation pattern tracked in #90
(lines 349, 397-398, 472, 520-521). This commit does not fix #90 --
the live path in ADAR1000_Manager.cpp still needs the channel-index
fix -- but it removes the dormant copy so the bug has one less place
to hide.

Verification:
- 9_Firmware/9_1_Microcontroller/tests: make clean && make -> all passing
  (51/51 UM982 GPS, 24/24 driver, 13/13 ADAR1000_AGC, bugs #1-15, Gap-3
  fixes 1-5, safety fixes)
- 9_Firmware/tests/cross_layer: 29 passed
- grep -rn "adar1000\.h|adar1000\.c|Adar_|AdarDevice" 9_Firmware: 0 hits
 2026-04-16 22:12:23 +03:00
Serhii 15ae940be5 test(cross-layer): enforce 2-frame DIG_6 debounce guard on outerAgc.enabled 
PR #93 added a 2-frame confirmation debounce so a single-sample GPIO
glitch cannot flip MCU outer-loop AGC state. The debounce is load-bearing
for the "prevents a single-sample glitch" guarantee in the PR body, but
no existing test enforces its structure — test_mcu_reads_dig6_before_agc_gate
only checks that HAL_GPIO_ReadPin(FPGA_DIG6, ...) and `outerAgc.enabled =`
appear somewhere in main.cpp, which a naive direct assignment would still
pass.

Add test_mcu_dig6_debounce_guards_enable_assignment to
TestTier1AgcCrossLayerInvariant, verifying four structural invariants of
the debounce:

  1. Current DIG_6 sample captured in a local variable
  2. Static previous-frame variable defaulting to false (matches FPGA
     boot: host_agc_enable resets 0)
  3. outerAgc.enabled assignment gated by `now == prev`
  4. Previous-frame variable advanced each frame

Verified test fails on a naive patch that removes the guard and passes
on the current PR #93 implementation. Full cross-layer suite stays at
0 failures (36/36 pass locally).
 2026-04-16 21:29:37 +03:00
Jason 658752abb7 fix: propagate FPGA AGC enable to MCU outer loop via DIG_6 GPIO 
Resolve cross-layer AGC control mismatch where opcode 0x28 only
controlled the FPGA inner-loop AGC but the STM32 outer-loop AGC
(ADAR1000_AGC) ran independently with its own enable state.

FPGA: Drive gpio_dig6 from host_agc_enable instead of tied low,
making the FPGA register the single source of truth for AGC state.

MCU: Change ADAR1000_AGC constructor default from enabled(true) to
enabled(false) so boot state matches FPGA reset default (AGC off).
Read DIG_6 GPIO every frame with 2-frame confirmation debounce to
sync outerAgc.enabled — prevents single-sample glitch from causing
spurious AGC state transitions.

Tests: Update MCU unit tests for new default, add 6 cross-layer
contract tests verifying the FPGA-MCU-GUI AGC invariant chain.
 2026-04-17 00:04:37 +05:45
Jason 76cfc71b19 fix(gui): align radar parameters to FPGA truth (radar_scene.py) 
- Bandwidth 500 MHz -> 20 MHz, sample rate 4 MHz -> 100 MHz (DDC output)
- Range formula: deramped FMCW -> matched-filter c/(2*Fs)*decimation
- Velocity formula: use PRI (167 us) and chirps_per_subframe (16)
- Carrier frequency: 10.525 GHz -> 10.5 GHz per radar_scene.py
- Range per bin: 4.8 m -> 24 m, max range: 307 m -> 1536 m
- Fix simulator target spawn range to match new coverage (50-1400 m)
- Remove dead BANDWIDTH constant, add SAMPLE_RATE to V65 Tk
- All 174 tests pass, ruff clean
 2026-04-16 21:35:01 +05:45
Jason 161e9a66e4 fix: clarify comments — AGC width, dual-USB docstring, BE datasheet ref 2026-04-16 17:51:09 +05:45
Jason 7a35f42e61 refactor(fpga): deduplicate RTL file lists in run_regression.sh 
Extract RECEIVER_RTL and SYSTEM_RTL shared arrays to replace 6
near-identical file lists. New modules now only need adding once.
 2026-04-16 17:07:01 +05:45
Jason a03dd1329a fix(tests): update cross-layer tests for frame_start bit and stream-gated mux 
- TB byte 9 check: expect 0x81 (frame_start=1 after reset + cfar=1)
- contract_parser: handle ternary expressions in data_pkt_byte mux
  (stream_doppler_en ? doppler_real_cap : 8'd0 pattern)
- contract_parser: handle intermediate variable pattern for detection
  field (det_byte = raw[9]; detection = det_byte & 0x01)
 2026-04-16 16:48:43 +05:45
Jason 6a11d33ef7 docs: deprecate GUI V6, update docs for FT2232H production default 
- Add deprecation headers to GUI_V6.py and GUI_V6_Demo.py
- Mark V6 as deprecated in GUI_versions.txt
- Update README.md: replace V6 GIF reference with V65 PNG
- Add FT2232H production notice banner to docs/index.html
 2026-04-16 16:19:30 +05:45
Jason b22cadb429 feat(gui): add FT601Connection class, USB interface selection in V65/V7 
- Add FT601Connection in radar_protocol.py using ftd3xx library with
  proper setChipConfiguration re-enumeration handling (close, wait 2s,
  re-open) and 4-byte write alignment
- Add USB Interface dropdown to V65 Tk GUI (FT2232H default, FT601 option)
- Add USB Interface combo to V7 PyQt dashboard with Live/File mode toggle
- Fix mock frame_start bit 7 in both FT2232H and FT601 connections
- Use FPGA range data from USB packets instead of recomputing in Python
- Export FT601Connection from v7/hardware.py and v7/__init__.py
- Add 7 FT601Connection tests (91 total in test_GUI_V65_Tk.py)
 2026-04-16 16:19:13 +05:45
Jason f393e96d69 feat(fpga): make FT2232H default USB interface, rewrite FT601 write FSM, add clock-loss watchdog 
- Set USB_MODE default to 1 (FT2232H) in radar_system_top.v; 200T build
  overrides to USB_MODE=0 via build_200t.tcl generic property
- Rewrite FT601 write FSM: 4-state architecture with 3-word packed data,
  pending-flag gating, and frame sync counter
- Add FT2232H read FSM rd_cmd_complete flag, stream field zeroing, and
  range_data_ready 1-cycle pipeline delay in both USB modules
- Implement clock-loss watchdog: ft_heartbeat toggle + 16-bit timeout
  counter drives ft_clk_lost, feeding ft_effective_reset_n via 2-stage
  ASYNC_REG synchronizer chain
- Fix sample_counter reset literal width (11'd0 -> 12'd0)
- Add FT2232H I/O timing constraints to 50T XDC; fix dac_clk comments
- Document vestigial ft601_txe_n/rxf_n ports (needed for 200T XDC)
- Tie off AGC ports on TE0713 dev wrapper
- Rewrite tb_usb_data_interface.v for new 4-state FSM (89 checks)
- Add USB_MODE=1 regression runs; remove dead CHECK 5/6 loop
- Update diag_log.h USB interface comment
 2026-04-16 16:18:52 +05:45
69 changed files with 13112 additions and 10869 deletions
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1_Project_Description/Project_Description.docx
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4_Schematics and Boards Layout/4_6_Schematics/MainBoard/RADAR_Main_Board.brd
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4_Schematics and Boards Layout/4_6_Schematics/PowerAmplifierBoard/RF_PA.brd
+2380 -127
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8_Utils/AERIS-10_RADAR.png
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9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_AGC.cpp
+1 -1
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@@ -18,7 +18,7 @@ ADAR1000_AGC::ADAR1000_AGC()
, min_gain(0)
, max_gain(127)
, holdoff_frames(4)
, enabled(true)
, enabled(false)
, holdoff_counter(0)
, last_saturated(false)
, saturation_event_count(0)
9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp
+212 -134
View File
@@ -10,28 +10,81 @@ extern SPI_HandleTypeDef hspi1;
extern UART_HandleTypeDef huart3;
// Chip Select GPIO definitions
static const struct {
GPIO_TypeDef* port;
uint16_t pin;
} CHIP_SELECTS[4] = {
{ADAR_1_CS_3V3_GPIO_Port, ADAR_1_CS_3V3_Pin}, // ADAR1000 #1
{ADAR_2_CS_3V3_GPIO_Port, ADAR_2_CS_3V3_Pin}, // ADAR1000 #2
{ADAR_3_CS_3V3_GPIO_Port, ADAR_3_CS_3V3_Pin}, // ADAR1000 #3
{ADAR_4_CS_3V3_GPIO_Port, ADAR_4_CS_3V3_Pin} // ADAR1000 #4
};
static const struct {
GPIO_TypeDef* port;
uint16_t pin;
} CHIP_SELECTS[4] = {
{ADAR_1_CS_3V3_GPIO_Port, ADAR_1_CS_3V3_Pin}, // ADAR1000 #1
{ADAR_2_CS_3V3_GPIO_Port, ADAR_2_CS_3V3_Pin}, // ADAR1000 #2
{ADAR_3_CS_3V3_GPIO_Port, ADAR_3_CS_3V3_Pin}, // ADAR1000 #3
{ADAR_4_CS_3V3_GPIO_Port, ADAR_4_CS_3V3_Pin} // ADAR1000 #4
};
// Vector Modulator lookup tables
// ADAR1000 Vector Modulator lookup tables (128-state phase grid, 2.8125 deg step).
//
// Source: Analog Devices ADAR1000 datasheet Rev. B, Tables 13-16, page 34
// (7_Components Datasheets and Application notes/ADAR1000.pdf)
// Cross-checked against the ADI Linux mainline driver (GPL-2.0, NOT vendored):
// https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/
// drivers/iio/beamformer/adar1000.c (adar1000_phase_values[])
// The 128 byte values themselves are factual data from the datasheet and are
// not subject to copyright; only the ADI driver code is GPL.
//
// Byte format (per datasheet):
// bit [7:6] reserved (0)
// bit [5] polarity: 1 = positive lobe (sign(I) or sign(Q) >= 0)
// 0 = negative lobe
// bits [4:0] 5-bit unsigned magnitude (0..31)
// At magnitude=0 the polarity bit is physically meaningless; the datasheet
// uses POL=1 (e.g. VM_Q at 0 deg = 0x20, VM_I at 90 deg = 0x21).
//
// Index mapping is uniform: VM_I[k] / VM_Q[k] correspond to phase angle
// k * 360/128 = k * 2.8125 degrees. Callers index as VM_*[phase % 128].
const uint8_t ADAR1000Manager::VM_I[128] = {
// ... (same as in your original file)
0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3E, 0x3E, 0x3D, // [ 0] 0.0000 deg
0x3D, 0x3C, 0x3C, 0x3B, 0x3A, 0x39, 0x38, 0x37, // [ 8] 22.5000 deg
0x36, 0x35, 0x34, 0x33, 0x32, 0x30, 0x2F, 0x2E, // [ 16] 45.0000 deg
0x2C, 0x2B, 0x2A, 0x28, 0x27, 0x25, 0x24, 0x22, // [ 24] 67.5000 deg
0x21, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A, // [ 32] 90.0000 deg
0x0B, 0x0D, 0x0E, 0x0F, 0x11, 0x12, 0x13, 0x14, // [ 40] 112.5000 deg
0x16, 0x17, 0x18, 0x19, 0x19, 0x1A, 0x1B, 0x1C, // [ 48] 135.0000 deg
0x1C, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F, // [ 56] 157.5000 deg
0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1E, 0x1E, 0x1D, // [ 64] 180.0000 deg
0x1D, 0x1C, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, // [ 72] 202.5000 deg
0x16, 0x15, 0x14, 0x13, 0x12, 0x10, 0x0F, 0x0E, // [ 80] 225.0000 deg
0x0C, 0x0B, 0x0A, 0x08, 0x07, 0x05, 0x04, 0x02, // [ 88] 247.5000 deg
0x01, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A, // [ 96] 270.0000 deg
0x2B, 0x2D, 0x2E, 0x2F, 0x31, 0x32, 0x33, 0x34, // [104] 292.5000 deg
0x36, 0x37, 0x38, 0x39, 0x39, 0x3A, 0x3B, 0x3C, // [112] 315.0000 deg
0x3C, 0x3D, 0x3E, 0x3E, 0x3E, 0x3F, 0x3F, 0x3F, // [120] 337.5000 deg
};
const uint8_t ADAR1000Manager::VM_Q[128] = {
// ... (same as in your original file)
0x20, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A, // [ 0] 0.0000 deg
0x2B, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x33, 0x34, // [ 8] 22.5000 deg
0x35, 0x36, 0x37, 0x38, 0x38, 0x39, 0x3A, 0x3A, // [ 16] 45.0000 deg
0x3B, 0x3C, 0x3C, 0x3C, 0x3D, 0x3D, 0x3D, 0x3D, // [ 24] 67.5000 deg
0x3D, 0x3D, 0x3D, 0x3D, 0x3D, 0x3C, 0x3C, 0x3C, // [ 32] 90.0000 deg
0x3B, 0x3A, 0x3A, 0x39, 0x38, 0x38, 0x37, 0x36, // [ 40] 112.5000 deg
0x35, 0x34, 0x33, 0x31, 0x30, 0x2F, 0x2E, 0x2D, // [ 48] 135.0000 deg
0x2B, 0x2A, 0x28, 0x27, 0x26, 0x24, 0x23, 0x21, // [ 56] 157.5000 deg
0x20, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A, // [ 64] 180.0000 deg
0x0B, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x13, 0x14, // [ 72] 202.5000 deg
0x15, 0x16, 0x17, 0x18, 0x18, 0x19, 0x1A, 0x1A, // [ 80] 225.0000 deg
0x1B, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1D, // [ 88] 247.5000 deg
0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1C, 0x1C, 0x1C, // [ 96] 270.0000 deg
0x1B, 0x1A, 0x1A, 0x19, 0x18, 0x18, 0x17, 0x16, // [104] 292.5000 deg
0x15, 0x14, 0x13, 0x11, 0x10, 0x0F, 0x0E, 0x0D, // [112] 315.0000 deg
0x0B, 0x0A, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, // [120] 337.5000 deg
};
const uint8_t ADAR1000Manager::VM_GAIN[128] = {
// ... (same as in your original file)
};
// NOTE: a VM_GAIN[128] table previously existed here as a placeholder but was
// never populated and never read. The ADAR1000 vector modulator has no
// separate gain register: phase-state magnitude is encoded directly in
// bits [4:0] of the VM_I/VM_Q bytes above. Per-channel VGA gain is a
// distinct register (CHx_RX_GAIN at 0x10-0x13, CHx_TX_GAIN at 0x1C-0x1F)
// written with the user-supplied byte directly by adarSetRxVgaGain() /
// adarSetTxVgaGain(). Do not reintroduce a VM_GAIN[] array.
ADAR1000Manager::ADAR1000Manager() {
for (int i = 0; i < 4; ++i) {
@@ -110,8 +163,10 @@ void ADAR1000Manager::switchToTXMode() {
DIAG("BF", "Step 3: PA bias ON");
setPABias(true);
delayUs(50);
DIAG("BF", "Step 4: ADTR1107 -> TX");
setADTR1107Control(true);
// Step 4 (former setADTR1107Control(true)) removed: TR pin is FPGA-owned.
// Chip follows adar_tr_x; TX path is asserted by the FPGA chirp FSM, not
// by SPI here. Write per-channel TX enables so the FPGA TR override has
// something to gate.
for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
adarWrite(dev, REG_RX_ENABLES, 0x00, BROADCAST_OFF);
@@ -132,8 +187,7 @@ void ADAR1000Manager::switchToRXMode() {
DIAG("BF", "Step 2: Disable PA supplies");
disablePASupplies();
delayUs(10);
DIAG("BF", "Step 3: ADTR1107 -> RX");
setADTR1107Control(false);
// Step 3 (former setADTR1107Control(false)) removed: FPGA owns TR pin.
DIAG("BF", "Step 4: Enable LNA supplies");
enableLNASupplies();
delayUs(50);
@@ -151,39 +205,11 @@ void ADAR1000Manager::switchToRXMode() {
DIAG("BF", "switchToRXMode() complete");
}
void ADAR1000Manager::fastTXMode() {
DIAG("BF", "fastTXMode(): ADTR1107 -> TX (no bias sequencing)");
setADTR1107Control(true);
for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
adarWrite(dev, REG_RX_ENABLES, 0x00, BROADCAST_OFF);
adarWrite(dev, REG_TX_ENABLES, 0x0F, BROADCAST_OFF);
devices_[dev]->current_mode = BeamDirection::TX;
}
current_mode_ = BeamDirection::TX;
}
void ADAR1000Manager::fastRXMode() {
DIAG("BF", "fastRXMode(): ADTR1107 -> RX (no bias sequencing)");
setADTR1107Control(false);
for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
adarWrite(dev, REG_TX_ENABLES, 0x00, BROADCAST_OFF);
adarWrite(dev, REG_RX_ENABLES, 0x0F, BROADCAST_OFF);
devices_[dev]->current_mode = BeamDirection::RX;
}
current_mode_ = BeamDirection::RX;
}
void ADAR1000Manager::pulseTXMode() {
DIAG("BF", "pulseTXMode(): TR switch only");
setADTR1107Control(true);
last_switch_time_us_ = HAL_GetTick() * 1000;
}
void ADAR1000Manager::pulseRXMode() {
DIAG("BF", "pulseRXMode(): TR switch only");
setADTR1107Control(false);
last_switch_time_us_ = HAL_GetTick() * 1000;
}
// fastTXMode, fastRXMode, pulseTXMode, pulseRXMode: REMOVED.
// The chirp hot path owns T/R switching via the FPGA adar_tr_x pins
// (see 9_Firmware/9_2_FPGA/plfm_chirp_controller.v). The old SPI-RMW per
// chirp was architecturally redundant, raced the FPGA, and toggled the
// wrong bit of REG_SW_CONTROL (TR_SOURCE instead of TR_SPI).
// Beam Steering
bool ADAR1000Manager::setBeamAngle(float angle_degrees, BeamDirection direction) {
@@ -202,15 +228,15 @@ bool ADAR1000Manager::setBeamAngle(float angle_degrees, BeamDirection direction)
for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
for (uint8_t ch = 0; ch < 4; ++ch) {
if (direction == BeamDirection::TX) {
adarSetTxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
adarSetTxVgaGain(dev, ch + 1, kDefaultTxVgaGain, BROADCAST_OFF);
} else {
adarSetRxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
adarSetRxVgaGain(dev, ch + 1, kDefaultRxVgaGain, BROADCAST_OFF);
}
}
}
if (direction == BeamDirection::TX) {
adarSetTxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
adarSetTxVgaGain(dev, ch + 1, kDefaultTxVgaGain, BROADCAST_OFF);
} else {
adarSetRxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
adarSetRxVgaGain(dev, ch + 1, kDefaultRxVgaGain, BROADCAST_OFF);
}
}
}
return true;
}
@@ -315,25 +341,10 @@ void ADAR1000Manager::writeRegister(uint8_t deviceIndex, uint32_t address, uint8
}
// Configuration
void ADAR1000Manager::setSwitchSettlingTime(uint32_t us) {
switch_settling_time_us_ = us;
}
void ADAR1000Manager::setFastSwitchMode(bool enable) {
DIAG("BF", "setFastSwitchMode(%s)", enable ? "ON" : "OFF");
fast_switch_mode_ = enable;
if (enable) {
switch_settling_time_us_ = 10;
DIAG("BF", " settling time = 10 us, enabling PA+LNA supplies and bias simultaneously");
enablePASupplies();
enableLNASupplies();
setPABias(true);
setLNABias(true);
} else {
switch_settling_time_us_ = 50;
DIAG("BF", " settling time = 50 us");
}
}
// setSwitchSettlingTime, setFastSwitchMode: REMOVED.
// Their only reader was the deleted setADTR1107Control; setFastSwitchMode(true)
// also violated the ADTR1107 datasheet bias sequence (PA + LNA biased to
// operational simultaneously). Per-chirp T/R is FPGA-owned now.
void ADAR1000Manager::setBeamDwellTime(uint32_t ms) {
beam_dwell_time_ms_ = ms;
@@ -375,15 +386,30 @@ bool ADAR1000Manager::initializeSingleDevice(uint8_t deviceIndex) {
DIAG("BF", " dev[%u] set RAM bypass (bias+beam)", deviceIndex);
adarSetRamBypass(deviceIndex, BROADCAST_OFF);
// Hand per-chirp T/R switching to the FPGA.
// Set TR_SOURCE (REG_SW_CONTROL bit 2) = 1 so the chip's internal
// RX_EN_OVERRIDE / TX_EN_OVERRIDE follow the external TR pin (driven by
// plfm_chirp_controller's adar_tr_x output). See ADAR1000 datasheet
// "Theory of Operation" -- SPI Control vs TR Pin Control.
// Without this write, the FPGA's TR pin is ignored and the chip stays
// in RX state (TR_SPI POR default).
DIAG("BF", " dev[%u] SW_CONTROL: TR_SOURCE=1 (FPGA owns TR pin)", deviceIndex);
adarWrite(deviceIndex, REG_SW_CONTROL, (1 << 2), BROADCAST_OFF);
// Initialize ADC
DIAG("BF", " dev[%u] enable ADC (2MHz clk)", deviceIndex);
adarWrite(deviceIndex, REG_ADC_CONTROL, ADAR1000_ADC_2MHZ_CLK | ADAR1000_ADC_EN, BROADCAST_OFF);
// Verify communication with scratchpad test
// Audit F-4.4: on SPI failure, previously marked the device initialized
// anyway, so downstream (e.g. PA enable) could drive PA gates out-of-spec
// on a dead bus. Now propagate the failure so initializeAllDevices aborts.
DIAG("BF", " dev[%u] verifying SPI communication...", deviceIndex);
bool comms_ok = verifyDeviceCommunication(deviceIndex);
if (!comms_ok) {
DIAG_WARN("BF", " dev[%u] scratchpad verify FAILED but marking initialized anyway", deviceIndex);
DIAG_ERR("BF", " dev[%u] scratchpad verify FAILED -- device NOT marked initialized", deviceIndex);
devices_[deviceIndex]->initialized = false;
return false;
}
devices_[deviceIndex]->initialized = true;
@@ -411,9 +437,11 @@ bool ADAR1000Manager::initializeADTR1107Sequence() {
HAL_GPIO_WritePin(EN_P_3V3_SW_GPIO_Port, EN_P_3V3_SW_Pin, GPIO_PIN_SET);
HAL_Delay(1);
// Step 4: Set CTRL_SW to RX mode initially via GPIO
DIAG("BF", "Step 4: CTRL_SW -> RX (initial safe mode)");
setADTR1107Control(false); // RX mode
// Step 4: CTRL_SW safe-default is RX.
// FPGA-owned path: with TR_SOURCE=1 (set in initializeSingleDevice) the
// chip follows adar_tr_x, which is 0 in the FPGA FSM's IDLE state = RX.
// No SPI write needed here.
DIAG("BF", "Step 4: CTRL_SW -> RX (FPGA adar_tr_x idle-low == RX)");
HAL_Delay(1);
// Step 5: Set VGG_LNA to 0
@@ -469,7 +497,7 @@ bool ADAR1000Manager::initializeADTR1107Sequence() {
HAL_UART_Transmit(&huart3, success, sizeof(success) - 1, 1000);
return true;
}
}
bool ADAR1000Manager::setAllDevicesTXMode() {
DIAG("BF", "setAllDevicesTXMode(): ADTR1107 -> TX, then configure ADAR1000s");
@@ -515,7 +543,7 @@ bool ADAR1000Manager::setAllDevicesRXMode() {
void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
if (direction == BeamDirection::TX) {
DIAG_SECTION("ADTR1107 -> TX MODE");
setADTR1107Control(true); // TX mode
// setADTR1107Control(true) removed: TR pin is FPGA-driven.
// Step 1: Disable LNA power first
DIAG("BF", " Disable LNA supplies");
@@ -545,10 +573,11 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
}
HAL_Delay(5);
// Step 5: Set TR switch to TX mode
DIAG("BF", " TR switch -> TX (TR_SOURCE=1, BIAS_EN)");
// Step 5: TR switch state is FPGA-driven. TR_SOURCE=1 is set once in
// initializeSingleDevice, so the chip already follows adar_tr_x.
// Only BIAS_EN needs to be asserted here.
DIAG("BF", " BIAS_EN (TR source still = FPGA adar_tr_x)");
for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
adarSetBit(dev, REG_SW_CONTROL, 2, BROADCAST_OFF); // TR_SOURCE = 1 (TX)
adarSetBit(dev, REG_MISC_ENABLES, 5, BROADCAST_OFF); // BIAS_EN
}
DIAG("BF", " ADTR1107 TX mode complete");
@@ -556,7 +585,7 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
} else {
// RECEIVE MODE: Enable LNA, Disable PA
DIAG_SECTION("ADTR1107 -> RX MODE");
setADTR1107Control(false); // RX mode
// setADTR1107Control(false) removed: TR pin is FPGA-driven.
// Step 1: Disable PA power first
DIAG("BF", " Disable PA supplies");
@@ -587,34 +616,21 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
}
HAL_Delay(5);
// Step 5: Set TR switch to RX mode
DIAG("BF", " TR switch -> RX (TR_SOURCE=0, LNA_BIAS_OUT_EN)");
// Step 5: TR switch state is FPGA-driven (TR_SOURCE left at 1).
// Only LNA_BIAS_OUT_EN needs to be asserted here.
DIAG("BF", " LNA_BIAS_OUT_EN (TR source still = FPGA adar_tr_x)");
for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
adarResetBit(dev, REG_SW_CONTROL, 2, BROADCAST_OFF); // TR_SOURCE = 0 (RX)
adarSetBit(dev, REG_MISC_ENABLES, 4, BROADCAST_OFF); // LNA_BIAS_OUT_EN
}
DIAG("BF", " ADTR1107 RX mode complete");
}
}
void ADAR1000Manager::setADTR1107Control(bool tx_mode) {
DIAG("BF", "setADTR1107Control(%s): setting TR switch on all %u devices, settling %lu us",
tx_mode ? "TX" : "RX", (unsigned)devices_.size(), (unsigned long)switch_settling_time_us_);
for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
setTRSwitchPosition(dev, tx_mode);
}
delayUs(switch_settling_time_us_);
}
void ADAR1000Manager::setTRSwitchPosition(uint8_t deviceIndex, bool tx_mode) {
if (tx_mode) {
// TX mode: Set TR_SOURCE = 1
adarSetBit(deviceIndex, REG_SW_CONTROL, 2, BROADCAST_OFF);
} else {
// RX mode: Set TR_SOURCE = 0
adarResetBit(deviceIndex, REG_SW_CONTROL, 2, BROADCAST_OFF);
}
}
// setADTR1107Control, setTRSwitchPosition: REMOVED.
// The per-device SPI RMW of REG_SW_CONTROL bit 2 (TR_SOURCE) was both wrong
// (it toggled the *control source*, not the TX/RX state -- TR_SPI is bit 1)
// and redundant with the FPGA's plfm_chirp_controller adar_tr_x output.
// TR_SOURCE is now set to 1 exactly once in initializeSingleDevice.
// Add the new public method
bool ADAR1000Manager::setCustomBeamPattern16(const uint8_t phase_pattern[16], BeamDirection direction) {
@@ -674,13 +690,24 @@ void ADAR1000Manager::setLNABias(bool enable) {
for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
adarWrite(dev, REG_LNA_BIAS_ON, lna_bias, BROADCAST_OFF);
}
}
}
void ADAR1000Manager::delayUs(uint32_t microseconds) {
// Simple implementation - for F7 @ 216MHz, each loop ~7 cycles ≈ 0.032us
volatile uint32_t cycles = microseconds * 10; // Adjust this multiplier for your clock
while (cycles--) {
__NOP();
// Audit F-4.7: the prior implementation was a calibrated __NOP() busy-loop
// that silently drifted with compiler optimization, cache state, and flash
// wait-states. The ADAR1000 PLL/TX settling times require a real clock, so
// we poll the DWT cycle counter instead. One-time TRCENA/CYCCNTENA enable
// is idempotent; subsequent calls skip the init branch via DWT->CTRL read.
if ((DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk) == 0U) {
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
DWT->CYCCNT = 0U;
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
}
const uint32_t cycles_per_us = SystemCoreClock / 1000000U;
const uint32_t start = DWT->CYCCNT;
const uint32_t target = microseconds * cycles_per_us;
while ((DWT->CYCCNT - start) < target) {
/* CYCCNT wraps cleanly modulo 2^32 — subtraction stays correct. */
}
}
@@ -742,14 +769,25 @@ void ADAR1000Manager::setChipSelect(uint8_t deviceIndex, bool state) {
}
void ADAR1000Manager::adarWrite(uint8_t deviceIndex, uint32_t mem_addr, uint8_t data, uint8_t broadcast) {
uint8_t instruction[3];
if (broadcast) {
instruction[0] = 0x08;
} else {
instruction[0] = ((devices_[deviceIndex]->dev_addr & 0x03) << 5);
// Audit F-4.1: the broadcast SPI opcode path (`instruction[0] = 0x08`)
// has never been exercised on silicon and is structurally questionable —
// setChipSelect() only toggles ONE device's CS line, so even if a caller
// opts into the broadcast opcode today, only the single selected chip
// actually sees the frame. Until a HIL test confirms multi-CS semantics,
// route every broadcast write through a per-device unicast loop. This
// preserves caller intent (all four devices take the write) and makes
// the dead opcode-0x08 path unreachable at runtime.
if (broadcast == BROADCAST_ON) {
DIAG_WARN("BF", "adarWrite: broadcast=1 lowered to per-device unicast (addr=0x%03lX data=0x%02X)",
(unsigned long)mem_addr, data);
for (uint8_t d = 0; d < devices_.size(); ++d) {
adarWrite(d, mem_addr, data, BROADCAST_OFF);
}
return;
}
uint8_t instruction[3];
instruction[0] = ((devices_[deviceIndex]->dev_addr & 0x03) << 5);
instruction[0] |= (0x1F00 & mem_addr) >> 8;
instruction[1] = (0xFF & mem_addr);
instruction[2] = data;
@@ -782,12 +820,26 @@ uint8_t ADAR1000Manager::adarRead(uint8_t deviceIndex, uint32_t mem_addr) {
}
void ADAR1000Manager::adarSetBit(uint8_t deviceIndex, uint32_t mem_addr, uint8_t bit, uint8_t broadcast) {
// Audit F-4.2: broadcast-RMW is unsafe. The read samples a single device
// but the write fans out to all four, overwriting the other three with
// deviceIndex's state. Reject and surface the mistake.
if (broadcast == BROADCAST_ON) {
DIAG_ERR("BF", "adarSetBit: broadcast RMW is unsafe, ignored (dev=%u addr=0x%03lX bit=%u)",
deviceIndex, (unsigned long)mem_addr, bit);
return;
}
uint8_t temp = adarRead(deviceIndex, mem_addr);
uint8_t data = temp | (1 << bit);
adarWrite(deviceIndex, mem_addr, data, broadcast);
}
void ADAR1000Manager::adarResetBit(uint8_t deviceIndex, uint32_t mem_addr, uint8_t bit, uint8_t broadcast) {
// Audit F-4.2: see adarSetBit.
if (broadcast == BROADCAST_ON) {
DIAG_ERR("BF", "adarResetBit: broadcast RMW is unsafe, ignored (dev=%u addr=0x%03lX bit=%u)",
deviceIndex, (unsigned long)mem_addr, bit);
return;
}
uint8_t temp = adarRead(deviceIndex, mem_addr);
uint8_t data = temp & ~(1 << bit);
adarWrite(deviceIndex, mem_addr, data, broadcast);
@@ -815,11 +867,22 @@ void ADAR1000Manager::adarSetRamBypass(uint8_t deviceIndex, uint8_t broadcast) {
}
void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
// channel is 1-based (CH1..CH4) per API contract documented in
// ADAR1000_AGC.cpp and matching ADI datasheet terminology.
// Reject out-of-range early so a stale 0-based caller does not
// silently wrap to ((0-1) & 0x03) == 3 and write to CH4.
// See issue #90.
if (channel < 1 || channel > 4) {
DIAG("BF", "adarSetRxPhase: channel %u out of range [1..4], ignored", channel);
return;
}
uint8_t i_val = VM_I[phase % 128];
uint8_t q_val = VM_Q[phase % 128];
uint32_t mem_addr_i = REG_CH1_RX_PHS_I + (channel & 0x03) * 2;
uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + (channel & 0x03) * 2;
// Subtract 1 to convert 1-based channel to 0-based register offset
// before masking. See issue #90.
uint32_t mem_addr_i = REG_CH1_RX_PHS_I + ((channel - 1) & 0x03) * 2;
uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + ((channel - 1) & 0x03) * 2;
adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
@@ -827,34 +890,49 @@ void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8
}
void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
// channel is 1-based (CH1..CH4). See issue #90.
if (channel < 1 || channel > 4) {
DIAG("BF", "adarSetTxPhase: channel %u out of range [1..4], ignored", channel);
return;
}
uint8_t i_val = VM_I[phase % 128];
uint8_t q_val = VM_Q[phase % 128];
uint32_t mem_addr_i = REG_CH1_TX_PHS_I + (channel & 0x03) * 2;
uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + (channel & 0x03) * 2;
uint32_t mem_addr_i = REG_CH1_TX_PHS_I + ((channel - 1) & 0x03) * 2;
uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + ((channel - 1) & 0x03) * 2;
adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
adarWrite(deviceIndex, REG_LOAD_WORKING, 0x1, broadcast);
adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
}
void ADAR1000Manager::adarSetRxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
uint32_t mem_addr = REG_CH1_RX_GAIN + (channel & 0x03);
// channel is 1-based (CH1..CH4). See issue #90.
if (channel < 1 || channel > 4) {
DIAG("BF", "adarSetRxVgaGain: channel %u out of range [1..4], ignored", channel);
return;
}
uint32_t mem_addr = REG_CH1_RX_GAIN + ((channel - 1) & 0x03);
adarWrite(deviceIndex, mem_addr, gain, broadcast);
adarWrite(deviceIndex, REG_LOAD_WORKING, 0x1, broadcast);
}
void ADAR1000Manager::adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
uint32_t mem_addr = REG_CH1_TX_GAIN + (channel & 0x03);
// channel is 1-based (CH1..CH4). See issue #90.
if (channel < 1 || channel > 4) {
DIAG("BF", "adarSetTxVgaGain: channel %u out of range [1..4], ignored", channel);
return;
}
uint32_t mem_addr = REG_CH1_TX_GAIN + ((channel - 1) & 0x03);
adarWrite(deviceIndex, mem_addr, gain, broadcast);
adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
}
void ADAR1000Manager::adarSetTxBias(uint8_t deviceIndex, uint8_t broadcast) {
adarWrite(deviceIndex, REG_BIAS_CURRENT_TX, kTxBiasCurrent, broadcast);
adarWrite(deviceIndex, REG_BIAS_CURRENT_TX_DRV, kTxDriverBiasCurrent, broadcast);
adarWrite(deviceIndex, REG_LOAD_WORKING, 0x2, broadcast);
}
void ADAR1000Manager::adarSetTxBias(uint8_t deviceIndex, uint8_t broadcast) {
adarWrite(deviceIndex, REG_BIAS_CURRENT_TX, kTxBiasCurrent, broadcast);
adarWrite(deviceIndex, REG_BIAS_CURRENT_TX_DRV, kTxDriverBiasCurrent, broadcast);
adarWrite(deviceIndex, REG_LOAD_WORKING, 0x2, broadcast);
}
uint8_t ADAR1000Manager::adarAdcRead(uint8_t deviceIndex, uint8_t broadcast) {
adarWrite(deviceIndex, REG_ADC_CONTROL, ADAR1000_ADC_ST_CONV, broadcast);
9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.h
+36 -29
View File
@@ -48,10 +48,11 @@ public:
// Mode Switching
void switchToTXMode();
void switchToRXMode();
void fastTXMode();
void fastRXMode();
void pulseTXMode();
void pulseRXMode();
// fastTXMode/fastRXMode/pulseTXMode/pulseRXMode were removed: per-chirp T/R
// switching is owned by the FPGA (plfm_chirp_controller -> adar_tr_x pins,
// requires TR_SOURCE=1 in REG_SW_CONTROL, set in initializeSingleDevice).
// The old SPI RMW path was architecturally redundant and also toggled the
// wrong bit (TR_SOURCE instead of TR_SPI). See PR for details.
// Beam Steering
bool setBeamAngle(float angle_degrees, BeamDirection direction);
@@ -69,7 +70,8 @@ public:
bool setAllDevicesTXMode();
bool setAllDevicesRXMode();
void setADTR1107Mode(BeamDirection direction);
void setADTR1107Control(bool tx_mode);
// setADTR1107Control removed -- it only wrapped the now-deleted
// setTRSwitchPosition SPI path. FPGA drives the TR pin directly.
// Monitoring and Diagnostics
float readTemperature(uint8_t deviceIndex);
@@ -78,8 +80,11 @@ public:
void writeRegister(uint8_t deviceIndex, uint32_t address, uint8_t value);
// Configuration
void setSwitchSettlingTime(uint32_t us);
void setFastSwitchMode(bool enable);
// setSwitchSettlingTime / setFastSwitchMode removed: their only reader was
// the deleted setADTR1107Control SPI path, and setFastSwitchMode(true)
// also bundled a datasheet-violating PA+LNA-biased-simultaneously side
// effect. Per-chirp settling is now FPGA-owned. Callers that need a
// warm-up bias state should use switchToTXMode / switchToRXMode instead.
void setBeamDwellTime(uint32_t ms);
// Getters
@@ -100,8 +105,8 @@ public:
};
// Configuration
bool fast_switch_mode_ = false;
uint32_t switch_settling_time_us_ = 50;
// fast_switch_mode_ / switch_settling_time_us_ removed: both had no
// readers after the FPGA-owned TR refactor.
uint32_t beam_dwell_time_ms_ = 100;
uint32_t last_switch_time_us_ = 0;
@@ -116,25 +121,27 @@ public:
bool beam_sweeping_active_ = false;
uint32_t last_beam_update_time_ = 0;
// Lookup tables
static const uint8_t VM_I[128];
static const uint8_t VM_Q[128];
static const uint8_t VM_GAIN[128];
// Named defaults for the ADTR1107 and ADAR1000 power sequence.
static constexpr uint8_t kDefaultTxVgaGain = 0x7F;
static constexpr uint8_t kDefaultRxVgaGain = 30;
static constexpr uint8_t kLnaBiasOff = 0x00;
static constexpr uint8_t kLnaBiasOperational = 0x30;
static constexpr uint8_t kPaBiasTxSafe = 0x5D;
static constexpr uint8_t kPaBiasIdqCalibration = 0x0D;
static constexpr uint8_t kPaBiasOperational = 0x7F;
static constexpr uint8_t kPaBiasRxSafe = 0x20;
static constexpr uint8_t kTxBiasCurrent = 0x2D;
static constexpr uint8_t kTxDriverBiasCurrent = 0x06;
// Private Methods
bool initializeSingleDevice(uint8_t deviceIndex);
// Vector Modulator lookup tables (see ADAR1000_Manager.cpp for provenance).
// Indexed as VM_*[phase % 128] on a uniform 2.8125 deg grid.
// No VM_GAIN[] table exists: VM magnitude is bits [4:0] of the I/Q bytes
// themselves; per-channel VGA gain uses a separate register.
static const uint8_t VM_I[128];
static const uint8_t VM_Q[128];
// Named defaults for the ADTR1107 and ADAR1000 power sequence.
static constexpr uint8_t kDefaultTxVgaGain = 0x7F;
static constexpr uint8_t kDefaultRxVgaGain = 30;
static constexpr uint8_t kLnaBiasOff = 0x00;
static constexpr uint8_t kLnaBiasOperational = 0x30;
static constexpr uint8_t kPaBiasTxSafe = 0x5D;
static constexpr uint8_t kPaBiasIdqCalibration = 0x0D;
static constexpr uint8_t kPaBiasOperational = 0x7F;
static constexpr uint8_t kPaBiasRxSafe = 0x20;
static constexpr uint8_t kTxBiasCurrent = 0x2D;
static constexpr uint8_t kTxDriverBiasCurrent = 0x06;
// Private Methods
bool initializeSingleDevice(uint8_t deviceIndex);
bool initializeADTR1107Sequence();
void calculatePhaseSettings(float angle_degrees, uint8_t phase_settings[4]);
void delayUs(uint32_t microseconds);
@@ -165,7 +172,7 @@ public:
void adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast);
void adarSetTxBias(uint8_t deviceIndex, uint8_t broadcast);
uint8_t adarAdcRead(uint8_t deviceIndex, uint8_t broadcast);
void setTRSwitchPosition(uint8_t deviceIndex, bool tx_mode);
// setTRSwitchPosition removed -- FPGA owns TR pin. See PR.
private:
9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/adar1000.c
-693
View File
@@ -1,693 +0,0 @@
/**
* MIT License
*
* Copyright (c) 2020 Jimmy Pentz
*
* Reach me at: github.com/jgpentz, jpentz1(at)gmail.com
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sells
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/* ADAR1000 4-Channel, X Band and Ku Band Beamformer */
// ----------------------------------------------------------------------------
// Includes
// ----------------------------------------------------------------------------
#include "main.h"
#include "stm32f7xx_hal.h"
#include "stm32f7xx_hal_spi.h"
#include "stm32f7xx_hal_gpio.h"
#include "adar1000.h"
// ----------------------------------------------------------------------------
// Preprocessor Definitions and Constants
// ----------------------------------------------------------------------------
// VM_GAIN is 15 dB of gain in 128 steps. ~0.12 dB per step.
// A 15 dB attenuator can be applied on top of these values.
const uint8_t VM_GAIN[128] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
};
// VM_I and VM_Q are the settings for the vector modulator. 128 steps in 360 degrees. ~2.813 degrees per step.
const uint8_t VM_I[128] = {
0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3E, 0x3E, 0x3D, 0x3D, 0x3C, 0x3C, 0x3B, 0x3A, 0x39, 0x38, 0x37,
0x36, 0x35, 0x34, 0x33, 0x32, 0x30, 0x2F, 0x2E, 0x2C, 0x2B, 0x2A, 0x28, 0x27, 0x25, 0x24, 0x22,
0x21, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A, 0x0B, 0x0D, 0x0E, 0x0F, 0x11, 0x12, 0x13, 0x14,
0x16, 0x17, 0x18, 0x19, 0x19, 0x1A, 0x1B, 0x1C, 0x1C, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F,
0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1E, 0x1E, 0x1D, 0x1D, 0x1C, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17,
0x16, 0x15, 0x14, 0x13, 0x12, 0x10, 0x0F, 0x0E, 0x0C, 0x0B, 0x0A, 0x08, 0x07, 0x05, 0x04, 0x02,
0x01, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A, 0x2B, 0x2D, 0x2E, 0x2F, 0x31, 0x32, 0x33, 0x34,
0x36, 0x37, 0x38, 0x39, 0x39, 0x3A, 0x3B, 0x3C, 0x3C, 0x3D, 0x3E, 0x3E, 0x3E, 0x3F, 0x3F, 0x3F,
};
const uint8_t VM_Q[128] = {
0x20, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A, 0x2B, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x33, 0x34,
0x35, 0x36, 0x37, 0x38, 0x38, 0x39, 0x3A, 0x3A, 0x3B, 0x3C, 0x3C, 0x3C, 0x3D, 0x3D, 0x3D, 0x3D,
0x3D, 0x3D, 0x3D, 0x3D, 0x3D, 0x3C, 0x3C, 0x3C, 0x3B, 0x3A, 0x3A, 0x39, 0x38, 0x38, 0x37, 0x36,
0x35, 0x34, 0x33, 0x31, 0x30, 0x2F, 0x2E, 0x2D, 0x2B, 0x2A, 0x28, 0x27, 0x26, 0x24, 0x23, 0x21,
0x20, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A, 0x0B, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x13, 0x14,
0x15, 0x16, 0x17, 0x18, 0x18, 0x19, 0x1A, 0x1A, 0x1B, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1D,
0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1C, 0x1C, 0x1C, 0x1B, 0x1A, 0x1A, 0x19, 0x18, 0x18, 0x17, 0x16,
0x15, 0x14, 0x13, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0B, 0x0A, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01,
};
// ----------------------------------------------------------------------------
// Function Definitions
// ----------------------------------------------------------------------------
/**
* @brief Initialize the ADC on the ADAR by setting the ADC with a 2 MHz clk,
* and then enable it.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @warning This is setup to only read temperature sensor data, not the power detectors.
*/
void Adar_AdcInit(const AdarDevice * p_adar, uint8_t broadcast)
{
uint8_t data;
data = ADAR1000_ADC_2MHZ_CLK | ADAR1000_ADC_EN;
Adar_Write(p_adar, REG_ADC_CONTROL, data, broadcast);
}
/**
* @brief Read a byte of data from the ADAR.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns a byte of data that has been converted from the temperature sensor.
*
* @warning This is setup to only read temperature sensor data, not the power detectors.
*/
uint8_t Adar_AdcRead(const AdarDevice * p_adar, uint8_t broadcast)
{
uint8_t data;
// Start the ADC conversion
Adar_Write(p_adar, REG_ADC_CONTROL, ADAR1000_ADC_ST_CONV, broadcast);
// This is blocking for now... wait until data is converted, then read it
while (!(Adar_Read(p_adar, REG_ADC_CONTROL) & 0x01))
{
}
data = Adar_Read(p_adar, REG_ADC_OUT);
return(data);
}
/**
* @brief Requests the device info from a specific ADAR and stores it in the
* provided AdarDeviceInfo struct.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param info[out] Struct that contains the device info fields.
*
* @return Returns ADAR_ERROR_NOERROR if information was successfully received and stored in the struct.
*/
uint8_t Adar_GetDeviceInfo(const AdarDevice * p_adar, AdarDeviceInfo * info)
{
*((uint8_t *)info) = Adar_Read(p_adar, 0x002);
info->chip_type = Adar_Read(p_adar, 0x003);
info->product_id = ((uint16_t)Adar_Read(p_adar, 0x004)) << 8;
info->product_id |= ((uint16_t)Adar_Read(p_adar, 0x005)) & 0x00ff;
info->scratchpad = Adar_Read(p_adar, 0x00A);
info->spi_rev = Adar_Read(p_adar, 0x00B);
info->vendor_id = ((uint16_t)Adar_Read(p_adar, 0x00C)) << 8;
info->vendor_id |= ((uint16_t)Adar_Read(p_adar, 0x00D)) & 0x00ff;
info->rev_id = Adar_Read(p_adar, 0x045);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Read the data that is stored in a single ADAR register.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param mem_addr Memory address of the register you wish to read from.
*
* @return Returns the byte of data that is stored in the desired register.
*
* @warning This function will clear ADDR_ASCN bits.
* @warning The ADAR does not allow for block reads.
*/
uint8_t Adar_Read(const AdarDevice * p_adar, uint32_t mem_addr)
{
uint8_t instruction[3];
// Set SDO active
Adar_Write(p_adar, REG_INTERFACE_CONFIG_A, INTERFACE_CONFIG_A_SDO_ACTIVE, 0);
instruction[0] = 0x80 | ((p_adar->dev_addr & 0x03) << 5);
instruction[0] |= ((0xff00 & mem_addr) >> 8);
instruction[1] = (0xff & mem_addr);
instruction[2] = 0x00;
p_adar->Transfer(instruction, p_adar->p_rx_buffer, ADAR1000_RD_SIZE);
// Set SDO Inactive
Adar_Write(p_adar, REG_INTERFACE_CONFIG_A, 0, 0);
return(p_adar->p_rx_buffer[2]);
}
/**
* @brief Block memory write to an ADAR device.
*
* @pre ADDR_ASCN bits in register zero must be set!
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param mem_addr Memory address of the register you wish to read from.
* @param p_data Pointer to block of data to transfer (must have two unused bytes preceding the data for instruction).
* @param size Size of data in bytes, including the two additional leading bytes.
*
* @warning First two bytes of data will be corrupted if you do not provide two unused leading bytes!
*/
void Adar_ReadBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size)
{
// Set SDO active
Adar_Write(p_adar, REG_INTERFACE_CONFIG_A, INTERFACE_CONFIG_A_SDO_ACTIVE | INTERFACE_CONFIG_A_ADDR_ASCN, 0);
// Prepare command
p_data[0] = 0x80 | ((p_adar->dev_addr & 0x03) << 5);
p_data[0] |= ((mem_addr) >> 8) & 0x1F;
p_data[1] = (0xFF & mem_addr);
// Start the transfer
p_adar->Transfer(p_data, p_data, size);
Adar_Write(p_adar, REG_INTERFACE_CONFIG_A, 0, 0);
// Return nothing since we assume this is non-blocking and won't wait around
}
/**
* @brief Sets the Rx/Tx bias currents for the LNA, VM, and VGA to be in either
* low power setting or nominal setting.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param p_bias[in] An AdarBiasCurrents struct filled with bias settings
* as seen in the datasheet Table 6. SPI Settings for
* Different Power Modules
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERR_NOERROR if the bias currents were set
*/
uint8_t Adar_SetBiasCurrents(const AdarDevice * p_adar, AdarBiasCurrents * p_bias, uint8_t broadcast)
{
uint8_t bias = 0;
// RX LNA/VGA/VM bias
bias = (p_bias->rx_lna & 0x0f);
Adar_Write(p_adar, REG_BIAS_CURRENT_RX_LNA, bias, broadcast); // RX LNA bias
bias = (p_bias->rx_vga & 0x07 << 3) | (p_bias->rx_vm & 0x07);
Adar_Write(p_adar, REG_BIAS_CURRENT_RX, bias, broadcast); // RX VM/VGA bias
// TX VGA/VM/DRV bias
bias = (p_bias->tx_vga & 0x07 << 3) | (p_bias->tx_vm & 0x07);
Adar_Write(p_adar, REG_BIAS_CURRENT_TX, bias, broadcast); // TX VM/VGA bias
bias = (p_bias->tx_drv & 0x07);
Adar_Write(p_adar, REG_BIAS_CURRENT_TX_DRV, bias, broadcast); // TX DRV bias
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Set the bias ON and bias OFF voltages for the four PA's and one LNA.
*
* @pre This will set all 5 bias ON values and all 5 bias OFF values at once.
* To enable these bias values, please see the data sheet and ensure that the BIAS_CTRL,
* LNA_BIAS_OUT_EN, TR_SOURCE, TX_EN, RX_EN, TR (input to chip), and PA_ON (input to chip)
* bits have all been properly set.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param bias_on_voltage Array that contains the bias ON voltages.
* @param bias_off_voltage Array that contains the bias OFF voltages.
*
* @return Returns ADAR_ERR_NOERROR if the bias currents were set
*/
uint8_t Adar_SetBiasVoltages(const AdarDevice * p_adar, uint8_t bias_on_voltage[5], uint8_t bias_off_voltage[5])
{
Adar_SetBit(p_adar, 0x30, 6, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x31, 2, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x38, 5, BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH1_BIAS_ON,bias_on_voltage[0], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH2_BIAS_ON,bias_on_voltage[1], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH3_BIAS_ON,bias_on_voltage[2], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH4_BIAS_ON,bias_on_voltage[3], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH1_BIAS_OFF,bias_off_voltage[0], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH2_BIAS_OFF,bias_off_voltage[1], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH3_BIAS_OFF,bias_off_voltage[2], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH4_BIAS_OFF,bias_off_voltage[3], BROADCAST_OFF);
Adar_SetBit(p_adar, 0x30, 4, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x30, 6, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x31, 2, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x38, 5, BROADCAST_OFF);
Adar_Write(p_adar, REG_LNA_BIAS_ON,bias_on_voltage[4], BROADCAST_OFF);
Adar_Write(p_adar, REG_LNA_BIAS_OFF,bias_off_voltage[4], BROADCAST_OFF);
Adar_ResetBit(p_adar, 0x30, 7, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x31, 2, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x31, 4, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x31, 7, BROADCAST_OFF);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Setup the ADAR to use settings that are transferred over SPI.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERR_NOERROR if the bias currents were set
*/
uint8_t Adar_SetRamBypass(const AdarDevice * p_adar, uint8_t broadcast)
{
uint8_t data;
data = (MEM_CTRL_BIAS_RAM_BYPASS | MEM_CTRL_BEAM_RAM_BYPASS);
Adar_Write(p_adar, REG_MEM_CTL, data, broadcast);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Set the VGA gain value of a Receive channel in dB.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param channel Channel in which to set the gain (1-4).
* @param vga_gain_db Gain to be applied to the channel, ranging from 0 - 30 dB.
* (Intended operation >16 dB).
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERROR_NOERROR if the gain was successfully set.
* ADAR_ERROR_FAILED if an invalid channel was selected.
*
* @warning 0 dB or 15 dB step attenuator may also be turned on, which is why intended operation is >16 dB.
*/
uint8_t Adar_SetRxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t vga_gain_db, uint8_t broadcast)
{
uint8_t vga_gain_bits = (uint8_t)(255*vga_gain_db/16);
uint32_t mem_addr = 0;
if((channel == 0) || (channel > 4))
{
return(ADAR_ERROR_FAILED);
}
mem_addr = REG_CH1_RX_GAIN + (channel & 0x03);
// Set gain
Adar_Write(p_adar, mem_addr, vga_gain_bits, broadcast);
// Load the new setting
Adar_Write(p_adar, REG_LOAD_WORKING, 0x1, broadcast);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Set the phase of a given receive channel using the I/Q vector modulator.
*
* @pre According to the given @param phase, this sets the polarity (bit 5) and gain (bits 4-0)
* of the @param channel, and then loads them into the working register.
* A vector modulator I/Q look-up table has been provided at the beginning of this library.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param channel Channel in which to set the gain (1-4).
* @param phase Byte that is used to set the polarity (bit 5) and gain (bits 4-0).
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERROR_NOERROR if the phase was successfully set.
* ADAR_ERROR_FAILED if an invalid channel was selected.
*
* @note To obtain your phase:
* phase = degrees * 128;
* phase /= 360;
*/
uint8_t Adar_SetRxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast)
{
uint8_t i_val = 0;
uint8_t q_val = 0;
uint32_t mem_addr_i, mem_addr_q;
if((channel == 0) || (channel > 4))
{
return(ADAR_ERROR_FAILED);
}
//phase = phase % 128;
i_val = VM_I[phase];
q_val = VM_Q[phase];
mem_addr_i = REG_CH1_RX_PHS_I + (channel & 0x03) * 2;
mem_addr_q = REG_CH1_RX_PHS_Q + (channel & 0x03) * 2;
Adar_Write(p_adar, mem_addr_i, i_val, broadcast);
Adar_Write(p_adar, mem_addr_q, q_val, broadcast);
Adar_Write(p_adar, REG_LOAD_WORKING, 0x1, broadcast);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Set the VGA gain value of a Tx channel in dB.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERROR_NOERROR if the bias was successfully set.
* ADAR_ERROR_FAILED if an invalid channel was selected.
*
* @warning 0 dB or 15 dB step attenuator may also be turned on, which is why intended operation is >16 dB.
*/
uint8_t Adar_SetTxBias(const AdarDevice * p_adar, uint8_t broadcast)
{
uint8_t vga_bias_bits;
uint8_t drv_bias_bits;
uint32_t mem_vga_bias;
uint32_t mem_drv_bias;
mem_vga_bias = REG_BIAS_CURRENT_TX;
mem_drv_bias = REG_BIAS_CURRENT_TX_DRV;
// Set bias to nom
vga_bias_bits = 0x2D;
drv_bias_bits = 0x06;
// Set bias
Adar_Write(p_adar, mem_vga_bias, vga_bias_bits, broadcast);
// Set bias
Adar_Write(p_adar, mem_drv_bias, drv_bias_bits, broadcast);
// Load the new setting
Adar_Write(p_adar, REG_LOAD_WORKING, 0x2, broadcast);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Set the VGA gain value of a Tx channel.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param channel Tx channel in which to set the gain, ranging from 1 - 4.
* @param gain Gain to be applied to the channel, ranging from 0 - 127,
* plus the MSb 15dB attenuator (Intended operation >16 dB).
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERROR_NOERROR if the gain was successfully set.
* ADAR_ERROR_FAILED if an invalid channel was selected.
*
* @warning 0 dB or 15 dB step attenuator may also be turned on, which is why intended operation is >16 dB.
*/
uint8_t Adar_SetTxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t gain, uint8_t broadcast)
{
uint32_t mem_addr;
if((channel == 0) || (channel > 4))
{
return(ADAR_ERROR_FAILED);
}
mem_addr = REG_CH1_TX_GAIN + (channel & 0x03);
// Set gain
Adar_Write(p_adar, mem_addr, gain, broadcast);
// Load the new setting
Adar_Write(p_adar, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Set the phase of a given transmit channel using the I/Q vector modulator.
*
* @pre According to the given @param phase, this sets the polarity (bit 5) and gain (bits 4-0)
* of the @param channel, and then loads them into the working register.
* A vector modulator I/Q look-up table has been provided at the beginning of this library.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param channel Channel in which to set the gain (1-4).
* @param phase Byte that is used to set the polarity (bit 5) and gain (bits 4-0).
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERROR_NOERROR if the phase was successfully set.
* ADAR_ERROR_FAILED if an invalid channel was selected.
*
* @note To obtain your phase:
* phase = degrees * 128;
* phase /= 360;
*/
uint8_t Adar_SetTxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast)
{
uint8_t i_val = 0;
uint8_t q_val = 0;
uint32_t mem_addr_i, mem_addr_q;
if((channel == 0) || (channel > 4))
{
return(ADAR_ERROR_FAILED);
}
//phase = phase % 128;
i_val = VM_I[phase];
q_val = VM_Q[phase];
mem_addr_i = REG_CH1_TX_PHS_I + (channel & 0x03) * 2;
mem_addr_q = REG_CH1_TX_PHS_Q + (channel & 0x03) * 2;
Adar_Write(p_adar, mem_addr_i, i_val, broadcast);
Adar_Write(p_adar, mem_addr_q, q_val, broadcast);
Adar_Write(p_adar, REG_LOAD_WORKING, 0x1, broadcast);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Reset the whole ADAR device.
*
* @param p_adar[in] ADAR pointer Which specifies the device and what function
* to use for SPI transfer.
*/
void Adar_SoftReset(const AdarDevice * p_adar)
{
uint8_t instruction[3];
instruction[0] = ((p_adar->dev_addr & 0x03) << 5);
instruction[1] = 0x00;
instruction[2] = 0x81;
p_adar->Transfer(instruction, NULL, sizeof(instruction));
}
/**
* @brief Reset ALL ADAR devices in the SPI chain.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
*/
void Adar_SoftResetAll(const AdarDevice * p_adar)
{
uint8_t instruction[3];
instruction[0] = 0x08;
instruction[1] = 0x00;
instruction[2] = 0x81;
p_adar->Transfer(instruction, NULL, sizeof(instruction));
}
/**
* @brief Write a byte of @param data to the register located at @param mem_addr.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param mem_addr Memory address of the register you wish to read from.
* @param data Byte of data to be stored in the register.
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
if this set to BROADCAST_ON.
*
* @warning If writing the same data to multiple registers, use ADAR_WriteBlock.
*/
void Adar_Write(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data, uint8_t broadcast)
{
uint8_t instruction[3];
if (broadcast)
{
instruction[0] = 0x08;
}
else
{
instruction[0] = ((p_adar->dev_addr & 0x03) << 5);
}
instruction[0] |= (0x1F00 & mem_addr) >> 8;
instruction[1] = (0xFF & mem_addr);
instruction[2] = data;
p_adar->Transfer(instruction, NULL, sizeof(instruction));
}
/**
* @brief Block memory write to an ADAR device.
*
* @pre ADDR_ASCN BITS IN REGISTER ZERO MUST BE SET!
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param mem_addr Memory address of the register you wish to read from.
* @param p_data[in] Pointer to block of data to transfer (must have two unused bytes
preceding the data for instruction).
* @param size Size of data in bytes, including the two additional leading bytes.
*
* @warning First two bytes of data will be corrupted if you do not provide two unused leading bytes!
*/
void Adar_WriteBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size)
{
// Prepare command
p_data[0] = ((p_adar->dev_addr & 0x03) << 5);
p_data[0] |= ((mem_addr) >> 8) & 0x1F;
p_data[1] = (0xFF & mem_addr);
// Start the transfer
p_adar->Transfer(p_data, NULL, size);
// Return nothing since we assume this is non-blocking and won't wait around
}
/**
* @brief Set contents of the INTERFACE_CONFIG_A register.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param flags #INTERFACE_CONFIG_A_SOFTRESET, #INTERFACE_CONFIG_A_LSB_FIRST,
* #INTERFACE_CONFIG_A_ADDR_ASCN, #INTERFACE_CONFIG_A_SDO_ACTIVE
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*/
void Adar_WriteConfigA(const AdarDevice * p_adar, uint8_t flags, uint8_t broadcast)
{
Adar_Write(p_adar, 0x00, flags, broadcast);
}
/**
* @brief Write a byte of @param data to the register located at @param mem_addr and
* then read from the device and verify that the register was correctly set.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param mem_addr Memory address of the register you wish to read from.
* @param data Byte of data to be stored in the register.
*
* @return Returns the number of attempts that it took to successfully write to a register,
* starting from zero.
* @warning This function currently only supports writes to a single regiter in a single ADAR.
*/
uint8_t Adar_WriteVerify(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data)
{
uint8_t rx_data;
for (uint8_t ii = 0; ii < 3; ii++)
{
Adar_Write(p_adar, mem_addr, data, 0);
// Can't read back from an ADAR with HW address 0
if (!((p_adar->dev_addr) % 4))
{
return(ADAR_ERROR_INVALIDADDR);
}
rx_data = Adar_Read(p_adar, mem_addr);
if (rx_data == data)
{
return(ii);
}
}
return(ADAR_ERROR_FAILED);
}
void Adar_SetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast)
{
uint8_t temp = Adar_Read(p_adar, mem_addr);
uint8_t data = temp|(1<<bit);
Adar_Write(p_adar,mem_addr, data,broadcast);
}
void Adar_ResetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast)
{
uint8_t temp = Adar_Read(p_adar, mem_addr);
uint8_t data = temp&~(1<<bit);
Adar_Write(p_adar,mem_addr, data,broadcast);
}
9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/adar1000.h
-294
View File
@@ -1,294 +0,0 @@
/**
* MIT License
*
* Copyright (c) 2020 Jimmy Pentz
*
* Reach me at: github.com/jgpentz, jpentz1( at )gmail.com
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sells
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/* ADAR1000 4-Channel, X Band and Ku Band Beamformer */
#ifndef LIB_ADAR1000_H_
#define LIB_ADAR1000_H_
#ifndef NULL
#define NULL (0)
#endif
// ----------------------------------------------------------------------------
// Includes
// ----------------------------------------------------------------------------
#include "main.h"
#include "stm32f7xx_hal.h"
#include "stm32f7xx_hal_spi.h"
#include "stm32f7xx_hal_gpio.h"
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#ifdef __cplusplus
extern "C" { // Prevent C++ name mangling
#endif
// ----------------------------------------------------------------------------
// Datatypes
// ----------------------------------------------------------------------------
extern SPI_HandleTypeDef hspi1;
extern const uint8_t VM_GAIN[128];
extern const uint8_t VM_I[128];
extern const uint8_t VM_Q[128];
/// A function pointer prototype for a SPI transfer, the 3 parameters would be
/// p_txData, p_rxData, and size (number of bytes to transfer), respectively.
typedef uint32_t (*Adar_SpiTransfer)( uint8_t *, uint8_t *, uint32_t);
typedef struct
{
uint8_t dev_addr; ///< 2-bit device hardware address, 0x00, 0x01, 0x10, 0x11
Adar_SpiTransfer Transfer; ///< Function pointer to the function used for SPI transfers
uint8_t * p_rx_buffer; ///< Data buffer to store received bytes into
}const AdarDevice;
/// Use this to store bias current values into, as seen in the datasheet
/// Table 6. SPI Settings for Different Power Modules
typedef struct
{
uint8_t rx_lna; ///< nominal: 8, low power: 5
uint8_t rx_vm; ///< nominal: 5, low power: 2
uint8_t rx_vga; ///< nominal: 10, low power: 3
uint8_t tx_vm; ///< nominal: 5, low power: 2
uint8_t tx_vga; ///< nominal: 5, low power: 5
uint8_t tx_drv; ///< nominal: 6, low power: 3
} AdarBiasCurrents;
/// Useful for queries regarding the device info
typedef struct
{
uint8_t norm_operating_mode : 2;
uint8_t cust_operating_mode : 2;
uint8_t dev_status : 4;
uint8_t chip_type;
uint16_t product_id;
uint8_t scratchpad;
uint8_t spi_rev;
uint16_t vendor_id;
uint8_t rev_id;
} AdarDeviceInfo;
/// Return types for functions in this library
typedef enum {
ADAR_ERROR_NOERROR = 0,
ADAR_ERROR_FAILED = 1,
ADAR_ERROR_INVALIDADDR = 2,
} AdarErrorCodes;
// ----------------------------------------------------------------------------
// Function Prototypes
// ----------------------------------------------------------------------------
void Adar_AdcInit(const AdarDevice * p_adar, uint8_t broadcast_bit);
uint8_t Adar_AdcRead(const AdarDevice * p_adar, uint8_t broadcast_bit);
uint8_t Adar_GetDeviceInfo(const AdarDevice * p_adar, AdarDeviceInfo * info);
uint8_t Adar_Read(const AdarDevice * p_adar, uint32_t mem_addr);
void Adar_ReadBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size);
uint8_t Adar_SetBiasCurrents(const AdarDevice * p_adar, AdarBiasCurrents * p_bias, uint8_t broadcast_bit);
uint8_t Adar_SetBiasVoltages(const AdarDevice * p_adar, uint8_t bias_on_voltage[5], uint8_t bias_off_voltage[5]);
uint8_t Adar_SetRamBypass(const AdarDevice * p_adar, uint8_t broadcast_bit);
uint8_t Adar_SetRxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t vga_gain_db, uint8_t broadcast_bit);
uint8_t Adar_SetRxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast_bit);
uint8_t Adar_SetTxBias(const AdarDevice * p_adar, uint8_t broadcast_bit);
uint8_t Adar_SetTxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t vga_gain_db, uint8_t broadcast_bit);
uint8_t Adar_SetTxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast_bit);
void Adar_SoftReset(const AdarDevice * p_adar);
void Adar_SoftResetAll(const AdarDevice * p_adar);
void Adar_Write(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data, uint8_t broadcast_bit);
void Adar_WriteBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size);
void Adar_WriteConfigA(const AdarDevice * p_adar, uint8_t flags, uint8_t broadcast);
uint8_t Adar_WriteVerify(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data);
void Adar_SetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast);
void Adar_ResetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast);
// ----------------------------------------------------------------------------
// Preprocessor Definitions and Constants
// ----------------------------------------------------------------------------
// Using BROADCAST_ON will send a command to all ADARs that share a bus
#define BROADCAST_OFF 0
#define BROADCAST_ON 1
// The minimum size of a read from the ADARs consists of 3 bytes
#define ADAR1000_RD_SIZE 3
// Address at which the TX RAM starts
#define ADAR_TX_RAM_START_ADDR 0x1800
// ADC Defines
#define ADAR1000_ADC_2MHZ_CLK 0x00
#define ADAR1000_ADC_EN 0x60
#define ADAR1000_ADC_ST_CONV 0x70
/* REGISTER DEFINITIONS */
#define REG_INTERFACE_CONFIG_A 0x000
#define REG_INTERFACE_CONFIG_B 0x001
#define REG_DEV_CONFIG 0x002
#define REG_SCRATCHPAD 0x00A
#define REG_TRANSFER 0x00F
#define REG_CH1_RX_GAIN 0x010
#define REG_CH2_RX_GAIN 0x011
#define REG_CH3_RX_GAIN 0x012
#define REG_CH4_RX_GAIN 0x013
#define REG_CH1_RX_PHS_I 0x014
#define REG_CH1_RX_PHS_Q 0x015
#define REG_CH2_RX_PHS_I 0x016
#define REG_CH2_RX_PHS_Q 0x017
#define REG_CH3_RX_PHS_I 0x018
#define REG_CH3_RX_PHS_Q 0x019
#define REG_CH4_RX_PHS_I 0x01A
#define REG_CH4_RX_PHS_Q 0x01B
#define REG_CH1_TX_GAIN 0x01C
#define REG_CH2_TX_GAIN 0x01D
#define REG_CH3_TX_GAIN 0x01E
#define REG_CH4_TX_GAIN 0x01F
#define REG_CH1_TX_PHS_I 0x020
#define REG_CH1_TX_PHS_Q 0x021
#define REG_CH2_TX_PHS_I 0x022
#define REG_CH2_TX_PHS_Q 0x023
#define REG_CH3_TX_PHS_I 0x024
#define REG_CH3_TX_PHS_Q 0x025
#define REG_CH4_TX_PHS_I 0x026
#define REG_CH4_TX_PHS_Q 0x027
#define REG_LOAD_WORKING 0x028
#define REG_PA_CH1_BIAS_ON 0x029
#define REG_PA_CH2_BIAS_ON 0x02A
#define REG_PA_CH3_BIAS_ON 0x02B
#define REG_PA_CH4_BIAS_ON 0x02C
#define REG_LNA_BIAS_ON 0x02D
#define REG_RX_ENABLES 0x02E
#define REG_TX_ENABLES 0x02F
#define REG_MISC_ENABLES 0x030
#define REG_SW_CONTROL 0x031
#define REG_ADC_CONTROL 0x032
#define REG_ADC_CONTROL_TEMP_EN 0xf0
#define REG_ADC_OUT 0x033
#define REG_BIAS_CURRENT_RX_LNA 0x034
#define REG_BIAS_CURRENT_RX 0x035
#define REG_BIAS_CURRENT_TX 0x036
#define REG_BIAS_CURRENT_TX_DRV 0x037
#define REG_MEM_CTL 0x038
#define REG_RX_CHX_MEM 0x039
#define REG_TX_CHX_MEM 0x03A
#define REG_RX_CH1_MEM 0x03D
#define REG_RX_CH2_MEM 0x03E
#define REG_RX_CH3_MEM 0x03F
#define REG_RX_CH4_MEM 0x040
#define REG_TX_CH1_MEM 0x041
#define REG_TX_CH2_MEM 0x042
#define REG_TX_CH3_MEM 0x043
#define REG_TX_CH4_MEM 0x044
#define REG_PA_CH1_BIAS_OFF 0x046
#define REG_PA_CH2_BIAS_OFF 0x047
#define REG_PA_CH3_BIAS_OFF 0x048
#define REG_PA_CH4_BIAS_OFF 0x049
#define REG_LNA_BIAS_OFF 0x04A
#define REG_TX_BEAM_STEP_START 0x04D
#define REG_TX_BEAM_STEP_STOP 0x04E
#define REG_RX_BEAM_STEP_START 0x04F
#define REG_RX_BEAM_STEP_STOP 0x050
// REGISTER CONSTANTS
#define INTERFACE_CONFIG_A_SOFTRESET ((1 << 7) | (1 << 0))
#define INTERFACE_CONFIG_A_LSB_FIRST ((1 << 6) | (1 << 1))
#define INTERFACE_CONFIG_A_ADDR_ASCN ((1 << 5) | (1 << 2))
#define INTERFACE_CONFIG_A_SDO_ACTIVE ((1 << 4) | (1 << 3))
#define LD_WRK_REGS_LDRX_OVERRIDE (1 << 0)
#define LD_WRK_REGS_LDTX_OVERRIDE (1 << 1)
#define RX_ENABLES_TX_VGA_EN (1 << 0)
#define RX_ENABLES_TX_VM_EN (1 << 1)
#define RX_ENABLES_TX_DRV_EN (1 << 2)
#define RX_ENABLES_CH3_TX_EN (1 << 3)
#define RX_ENABLES_CH2_TX_EN (1 << 4)
#define RX_ENABLES_CH1_TX_EN (1 << 5)
#define RX_ENABLES_CH0_TX_EN (1 << 6)
#define TX_ENABLES_TX_VGA_EN (1 << 0)
#define TX_ENABLES_TX_VM_EN (1 << 1)
#define TX_ENABLES_TX_DRV_EN (1 << 2)
#define TX_ENABLES_CH3_TX_EN (1 << 3)
#define TX_ENABLES_CH2_TX_EN (1 << 4)
#define TX_ENABLES_CH1_TX_EN (1 << 5)
#define TX_ENABLES_CH0_TX_EN (1 << 6)
#define MISC_ENABLES_CH4_DET_EN (1 << 0)
#define MISC_ENABLES_CH3_DET_EN (1 << 1)
#define MISC_ENABLES_CH2_DET_EN (1 << 2)
#define MISC_ENABLES_CH1_DET_EN (1 << 3)
#define MISC_ENABLES_LNA_BIAS_OUT_EN (1 << 4)
#define MISC_ENABLES_BIAS_EN (1 << 5)
#define MISC_ENABLES_BIAS_CTRL (1 << 6)
#define MISC_ENABLES_SW_DRV_TR_MODE_SEL (1 << 7)
#define SW_CTRL_POL (1 << 0)
#define SW_CTRL_TR_SPI (1 << 1)
#define SW_CTRL_TR_SOURCE (1 << 2)
#define SW_CTRL_SW_DRV_EN_POL (1 << 3)
#define SW_CTRL_SW_DRV_EN_TR (1 << 4)
#define SW_CTRL_RX_EN (1 << 5)
#define SW_CTRL_TX_EN (1 << 6)
#define SW_CTRL_SW_DRV_TR_STATE (1 << 7)
#define MEM_CTRL_RX_CHX_RAM_BYPASS (1 << 0)
#define MEM_CTRL_TX_CHX_RAM_BYPASS (1 << 1)
#define MEM_CTRL_RX_BEAM_STEP_EN (1 << 2)
#define MEM_CTRL_TX_BEAM_STEP_EN (1 << 3)
#define MEM_CTRL_BIAS_RAM_BYPASS (1 << 5)
#define MEM_CTRL_BEAM_RAM_BYPASS (1 << 6)
#define MEM_CTRL_SCAN_MODE_EN (1 << 7)
#ifdef __cplusplus
} // End extern "C"
#endif
#endif /* LIB_ADAR1000_H_ */
9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h
+1 -1
View File
@@ -112,7 +112,7 @@ extern "C" {
* "BF" -- ADAR1000 beamformer
* "PA" -- Power amplifier bias/monitoring
* "FPGA" -- FPGA communication and handshake
* "USB" -- FT601 USB data path
* "USB" -- USB data path (FT2232H production / FT601 premium)
* "PWR" -- Power sequencing and rail monitoring
* "IMU" -- IMU/GPS/barometer sensors
* "MOT" -- Stepper motor/scan mechanics
9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp
+109 -95
View File
@@ -21,7 +21,6 @@
#include "usb_device.h"
#include "USBHandler.h"
#include "usbd_cdc_if.h"
#include "adar1000.h"
#include "ADAR1000_Manager.h"
#include "ADAR1000_AGC.h"
extern "C" {
@@ -484,11 +483,14 @@ void executeChirpSequence(int num_chirps, float T1, float PRI1, float T2, float
DIAG("SYS", "executeChirpSequence: num_chirps=%d T1=%.2f PRI1=%.2f T2=%.2f PRI2=%.2f",
num_chirps, T1, PRI1, T2, PRI2);
// First chirp sequence (microsecond timing)
// T/R switching is owned by the FPGA plfm_chirp_controller: its chirp
// FSM drives adar_tr_x high during LONG_CHIRP/SHORT_CHIRP and low during
// listen/guard. new_chirp (GPIOD_8) triggers the FSM out of IDLE.
// The MCU's old pulseTXMode/pulseRXMode SPI path was redundant and raced
// the FPGA -- removed.
for(int i = 0; i < num_chirps; i++) {
HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_8); // New chirp signal to FPGA
adarManager.pulseTXMode();
delay_us((uint32_t)T1);
adarManager.pulseRXMode();
delay_us((uint32_t)(PRI1 - T1));
}
@@ -497,11 +499,8 @@ void executeChirpSequence(int num_chirps, float T1, float PRI1, float T2, float
// Second chirp sequence (nanosecond timing)
for(int i = 0; i < num_chirps; i++) {
HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_8); // New chirp signal to FPGA
adarManager.pulseTXMode();
delay_ns((uint32_t)(T2 * 1000));
adarManager.pulseRXMode();
delay_ns((uint32_t)((PRI2 - T2) * 1000));
}
}
@@ -514,9 +513,9 @@ void runRadarPulseSequence() {
DIAG("SYS", "runRadarPulseSequence #%d: m_max=%d n_max=%d y_max=%d",
sequence_count, m_max, n_max, y_max);
// Configure for fast switching
DIAG("BF", "Enabling fast-switch mode for beam sweep");
adarManager.setFastSwitchMode(true);
// Fast per-chirp switching is now FPGA-owned (plfm_chirp_controller
// adar_tr_x), not MCU-driven. setFastSwitchMode(true) call removed.
DIAG("BF", "Beam sweep start (FPGA owns per-chirp T/R switching)");
int m = 1; // Chirp counter
int n = 1; // Beam Elevation position counter
@@ -657,18 +656,18 @@ SystemError_t checkSystemHealth(void) {
// 1. Check AD9523 Clock Generator
static uint32_t last_clock_check = 0;
if (HAL_GetTick() - last_clock_check > 5000) {
GPIO_PinState s0 = HAL_GPIO_ReadPin(AD9523_STATUS0_GPIO_Port, AD9523_STATUS0_Pin);
GPIO_PinState s1 = HAL_GPIO_ReadPin(AD9523_STATUS1_GPIO_Port, AD9523_STATUS1_Pin);
DIAG_GPIO("CLK", "AD9523 STATUS0", s0);
DIAG_GPIO("CLK", "AD9523 STATUS1", s1);
if (s0 == GPIO_PIN_RESET || s1 == GPIO_PIN_RESET) {
current_error = ERROR_AD9523_CLOCK;
DIAG_ERR("CLK", "AD9523 clock health check FAILED (STATUS0=%d STATUS1=%d)", s0, s1);
return current_error;
}
last_clock_check = HAL_GetTick();
}
if (HAL_GetTick() - last_clock_check > 5000) {
GPIO_PinState s0 = HAL_GPIO_ReadPin(AD9523_STATUS0_GPIO_Port, AD9523_STATUS0_Pin);
GPIO_PinState s1 = HAL_GPIO_ReadPin(AD9523_STATUS1_GPIO_Port, AD9523_STATUS1_Pin);
DIAG_GPIO("CLK", "AD9523 STATUS0", s0);
DIAG_GPIO("CLK", "AD9523 STATUS1", s1);
if (s0 == GPIO_PIN_RESET || s1 == GPIO_PIN_RESET) {
current_error = ERROR_AD9523_CLOCK;
DIAG_ERR("CLK", "AD9523 clock health check FAILED (STATUS0=%d STATUS1=%d)", s0, s1);
return current_error;
}
last_clock_check = HAL_GetTick();
}
// 2. Check ADF4382 Lock Status
bool tx_locked, rx_locked;
@@ -703,34 +702,34 @@ SystemError_t checkSystemHealth(void) {
// 4. Check IMU Communication
static uint32_t last_imu_check = 0;
if (HAL_GetTick() - last_imu_check > 10000) {
if (!GY85_Update(&imu)) {
current_error = ERROR_IMU_COMM;
DIAG_ERR("IMU", "Health check: GY85_Update() FAILED");
return current_error;
}
last_imu_check = HAL_GetTick();
}
if (HAL_GetTick() - last_imu_check > 10000) {
if (!GY85_Update(&imu)) {
current_error = ERROR_IMU_COMM;
DIAG_ERR("IMU", "Health check: GY85_Update() FAILED");
return current_error;
}
last_imu_check = HAL_GetTick();
}
// 5. Check BMP180 Communication
static uint32_t last_bmp_check = 0;
if (HAL_GetTick() - last_bmp_check > 15000) {
double pressure = myBMP.getPressure();
if (pressure < 30000.0 || pressure > 110000.0 || isnan(pressure)) {
current_error = ERROR_BMP180_COMM;
DIAG_ERR("SYS", "Health check: BMP180 pressure out of range: %.0f", pressure);
return current_error;
}
last_bmp_check = HAL_GetTick();
}
if (HAL_GetTick() - last_bmp_check > 15000) {
double pressure = myBMP.getPressure();
if (pressure < 30000.0 || pressure > 110000.0 || isnan(pressure)) {
current_error = ERROR_BMP180_COMM;
DIAG_ERR("SYS", "Health check: BMP180 pressure out of range: %.0f", pressure);
return current_error;
}
last_bmp_check = HAL_GetTick();
}
// 6. Check GPS Communication (30s grace period from boot / last valid fix)
uint32_t gps_fix_age = um982_position_age(&um982);
if (gps_fix_age > 30000) {
current_error = ERROR_GPS_COMM;
DIAG_WARN("SYS", "Health check: GPS no fix for >30s (age=%lu ms)", (unsigned long)gps_fix_age);
return current_error;
}
// 6. Check GPS Communication (30s grace period from boot / last valid fix)
uint32_t gps_fix_age = um982_position_age(&um982);
if (gps_fix_age > 30000) {
current_error = ERROR_GPS_COMM;
DIAG_WARN("SYS", "Health check: GPS no fix for >30s (age=%lu ms)", (unsigned long)gps_fix_age);
return current_error;
}
// 7. Check RF Power Amplifier Current
if (PowerAmplifier) {
@@ -761,7 +760,7 @@ SystemError_t checkSystemHealth(void) {
DIAG_ERR("SYS", "checkSystemHealth returning error code %d", current_error);
}
return current_error;
}
}
// Error recovery function
void attemptErrorRecovery(SystemError_t error) {
@@ -906,22 +905,22 @@ void handleSystemError(SystemError_t error) {
HAL_Delay(200);
}
// Critical errors trigger emergency shutdown.
//
// Safety-critical range: any fault that can damage the PAs or leave the
// system in an undefined state must cut the RF rails via Emergency_Stop().
// This covers:
// ERROR_RF_PA_OVERCURRENT .. ERROR_POWER_SUPPLY (9..13) -- PA/supply faults
// ERROR_TEMPERATURE_HIGH (14) -- >75 C on the PA thermal sensors;
// without cutting bias + 5V/5V5/RFPA rails
// the GaN QPA2962 stage can thermal-runaway.
// ERROR_WATCHDOG_TIMEOUT (16) -- health-check loop has stalled (>60 s);
// transmitter state is unknown, safest to
// latch Emergency_Stop rather than rely on
// IWDG reset (which re-energises the rails).
if ((error >= ERROR_RF_PA_OVERCURRENT && error <= ERROR_POWER_SUPPLY) ||
error == ERROR_TEMPERATURE_HIGH ||
error == ERROR_WATCHDOG_TIMEOUT) {
// Critical errors trigger emergency shutdown.
//
// Safety-critical range: any fault that can damage the PAs or leave the
// system in an undefined state must cut the RF rails via Emergency_Stop().
// This covers:
// ERROR_RF_PA_OVERCURRENT .. ERROR_POWER_SUPPLY (9..13) -- PA/supply faults
// ERROR_TEMPERATURE_HIGH (14) -- >75 C on the PA thermal sensors;
// without cutting bias + 5V/5V5/RFPA rails
// the GaN QPA2962 stage can thermal-runaway.
// ERROR_WATCHDOG_TIMEOUT (16) -- health-check loop has stalled (>60 s);
// transmitter state is unknown, safest to
// latch Emergency_Stop rather than rely on
// IWDG reset (which re-energises the rails).
if ((error >= ERROR_RF_PA_OVERCURRENT && error <= ERROR_POWER_SUPPLY) ||
error == ERROR_TEMPERATURE_HIGH ||
error == ERROR_WATCHDOG_TIMEOUT) {
DIAG_ERR("SYS", "CRITICAL ERROR (code %d: %s) -- initiating Emergency_Stop()", error, err_name);
snprintf(error_msg, sizeof(error_msg),
"CRITICAL ERROR! Initiating emergency shutdown.\r\n");
@@ -1484,8 +1483,8 @@ int main(void)
HAL_GPIO_WritePin(EN_P_3V3_FPGA_GPIO_Port,EN_P_3V3_FPGA_Pin,GPIO_PIN_SET);
HAL_Delay(100);
DIAG("PWR", "FPGA power sequencing complete -- 1.0V -> 1.8V -> 3.3V");
// Initialize module IMU
DIAG_SECTION("IMU INIT (GY-85)");
DIAG("IMU", "Initializing GY-85 IMU...");
@@ -1494,12 +1493,12 @@ int main(void)
Error_Handler();
}
DIAG("IMU", "GY-85 initialized OK, running 10 calibration samples");
for(int i=0; i<10;i++){
if (!GY85_Update(&imu)) {
Error_Handler();
}
ax = imu.ax;
for(int i=0; i<10;i++){
if (!GY85_Update(&imu)) {
Error_Handler();
}
ax = imu.ax;
ay = imu.ay;
az = imu.az;
gx = -imu.gx;
@@ -1794,20 +1793,20 @@ int main(void)
HAL_Delay(10);
}
}
RADAR_Longitude = um982_get_longitude(&um982);
RADAR_Latitude = um982_get_latitude(&um982);
DIAG("GPS", "Initial position: lat=%.6f lon=%.6f fix=%d sats=%d",
RADAR_Latitude, RADAR_Longitude,
um982_get_fix_quality(&um982), um982_get_num_sats(&um982));
// Re-apply heading after GPS init so the north-alignment stepper move uses
// UM982 dual-antenna heading when available.
if (um982_is_heading_valid(&um982)) {
Yaw_Sensor = um982_get_heading(&um982);
}
//move Stepper to position 1 = 0°
HAL_GPIO_WritePin(STEPPER_CW_P_GPIO_Port, STEPPER_CW_P_Pin, GPIO_PIN_RESET);//Set stepper motor spinning direction to CCW
RADAR_Longitude = um982_get_longitude(&um982);
RADAR_Latitude = um982_get_latitude(&um982);
DIAG("GPS", "Initial position: lat=%.6f lon=%.6f fix=%d sats=%d",
RADAR_Latitude, RADAR_Longitude,
um982_get_fix_quality(&um982), um982_get_num_sats(&um982));
// Re-apply heading after GPS init so the north-alignment stepper move uses
// UM982 dual-antenna heading when available.
if (um982_is_heading_valid(&um982)) {
Yaw_Sensor = um982_get_heading(&um982);
}
//move Stepper to position 1 = 0°
HAL_GPIO_WritePin(STEPPER_CW_P_GPIO_Port, STEPPER_CW_P_Pin, GPIO_PIN_RESET);//Set stepper motor spinning direction to CCW
//Point Stepper to North
for(int i= 0;i<(int)(Yaw_Sensor*Stepper_steps/360);i++){
HAL_GPIO_WritePin(STEPPER_CLK_P_GPIO_Port, STEPPER_CLK_P_Pin, GPIO_PIN_SET);
@@ -1820,14 +1819,14 @@ int main(void)
/**********wait for GUI start flag and Send Lat/Long/alt********/
/***************************************************************/
GPS_Data_t gps_data;
// Binary packet structure:
// [Header 4 bytes][Latitude 8 bytes][Longitude 8 bytes][Altitude 4 bytes][Pitch 4 bytes][CRC 2 bytes]
gps_data = {RADAR_Latitude, RADAR_Longitude, RADAR_Altitude, Pitch_Sensor, HAL_GetTick()};
if (!GPS_SendBinaryToGUI(&gps_data)) {
const uint8_t gps_send_error[] = "GPS binary send failed\r\n";
HAL_UART_Transmit(&huart3, (uint8_t*)gps_send_error, sizeof(gps_send_error) - 1, 1000);
}
GPS_Data_t gps_data;
// Binary packet structure:
// [Header 4 bytes][Latitude 8 bytes][Longitude 8 bytes][Altitude 4 bytes][Pitch 4 bytes][CRC 2 bytes]
gps_data = {RADAR_Latitude, RADAR_Longitude, RADAR_Altitude, Pitch_Sensor, HAL_GetTick()};
if (!GPS_SendBinaryToGUI(&gps_data)) {
const uint8_t gps_send_error[] = "GPS binary send failed\r\n";
HAL_UART_Transmit(&huart3, (uint8_t*)gps_send_error, sizeof(gps_send_error) - 1, 1000);
}
/* [STM32-006 FIXED] Removed blocking do-while loop that waited for
* usbHandler.isStartFlagReceived(). The production V7 PyQt GUI does not
@@ -2180,9 +2179,24 @@ int main(void)
runRadarPulseSequence();
/* [AGC] Outer-loop AGC: read FPGA saturation flag (DIG_5 / PD13),
* adjust ADAR1000 VGA common gain once per radar frame (~258 ms).
* Only run when AGC is enabled — otherwise leave VGA gains untouched. */
/* [AGC] Outer-loop AGC: sync enable from FPGA via DIG_6 (PD14),
* then read saturation flag (DIG_5 / PD13) and adjust ADAR1000 VGA
* common gain once per radar frame (~258 ms).
* FPGA register host_agc_enable is the single source of truth —
* DIG_6 propagates it to MCU every frame.
* 2-frame confirmation debounce: only change outerAgc.enabled when
* two consecutive frames read the same DIG_6 value. Prevents a
* single-sample glitch from causing a spurious AGC state transition.
* Added latency: 1 extra frame (~258 ms), acceptable for control plane. */
{
bool dig6_now = (HAL_GPIO_ReadPin(FPGA_DIG6_GPIO_Port,
FPGA_DIG6_Pin) == GPIO_PIN_SET);
static bool dig6_prev = false; // matches boot default (AGC off)
if (dig6_now == dig6_prev) {
outerAgc.enabled = dig6_now;
}
dig6_prev = dig6_now;
}
if (outerAgc.enabled) {
bool sat = HAL_GPIO_ReadPin(FPGA_DIG5_SAT_GPIO_Port,
FPGA_DIG5_SAT_Pin) == GPIO_PIN_SET;
9_Firmware/9_1_Microcontroller/tests/stm32_hal_mock.c
+8
View File
@@ -406,3 +406,11 @@ static int mock_spi_init_stub(void) { return 0; }
const struct no_os_spi_platform_ops stm32_spi_ops = {
.init = mock_spi_init_stub,
};
/* ========================= CMSIS-Core stub storage ======================= */
/* See stm32_hal_mock.h for rationale. SystemCoreClock = 0 forces delayUs() to
* return immediately under host test builds. DWT->CTRL pre-enabled so the
* one-time-init branch is skipped deterministically. */
struct _DWT_Mock_Type _dwt_mock = { .CTRL = DWT_CTRL_CYCCNTENA_Msk, .CYCCNT = 0 };
struct _CoreDebug_Mock_Type _coredebug_mock = { .DEMCR = 0 };
uint32_t SystemCoreClock = 0U;
9_Firmware/9_1_Microcontroller/tests/stm32_hal_mock.h
+20
View File
@@ -242,6 +242,26 @@ uint8_t ADS7830_Measure_SingleEnded(ADC_HandleTypeDef *hadc, uint8_t channel);
* if desired via a global flag. */
extern int mock_printf_enabled;
/* ========================= CMSIS-Core stubs ======================= */
/* Minimum surface to let F-4.7's DWT-based delayUs() in ADAR1000_Manager.cpp
* compile under the host mock build. SystemCoreClock is intentionally 0 so
* target = microseconds * (SystemCoreClock / 1000000) is also 0, making the
* busy-wait loop exit immediately regardless of argument. Pre-setting
* DWT->CTRL with CYCCNTENA also skips the one-time init branch. */
#define DWT_CTRL_CYCCNTENA_Msk (1UL << 0)
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << 24)
struct _DWT_Mock_Type { uint32_t CTRL; uint32_t CYCCNT; };
struct _CoreDebug_Mock_Type { uint32_t DEMCR; };
extern struct _DWT_Mock_Type _dwt_mock;
extern struct _CoreDebug_Mock_Type _coredebug_mock;
extern uint32_t SystemCoreClock;
#define DWT (&_dwt_mock)
#define CoreDebug (&_coredebug_mock)
#ifdef __cplusplus
}
#endif
9_Firmware/9_1_Microcontroller/tests/test_agc_outer_loop.cpp
+9 -1
View File
@@ -50,7 +50,7 @@ static void test_defaults()
assert(agc.min_gain == 0);
assert(agc.max_gain == 127);
assert(agc.holdoff_frames == 4);
assert(agc.enabled == true);
assert(agc.enabled == false); // disabled by default — FPGA DIG_6 is source of truth
assert(agc.holdoff_counter == 0);
assert(agc.last_saturated == false);
assert(agc.saturation_event_count == 0);
@@ -67,6 +67,7 @@ static void test_defaults()
static void test_saturation_reduces_gain()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
uint8_t initial = agc.agc_base_gain; // 30
agc.update(true); // saturation
@@ -82,6 +83,7 @@ static void test_saturation_reduces_gain()
static void test_holdoff_prevents_early_gain_up()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
agc.update(true); // saturate once -> gain = 26
uint8_t after_sat = agc.agc_base_gain;
@@ -101,6 +103,7 @@ static void test_holdoff_prevents_early_gain_up()
static void test_recovery_after_holdoff()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
agc.update(true); // saturate -> gain = 26
uint8_t after_sat = agc.agc_base_gain;
@@ -119,6 +122,7 @@ static void test_recovery_after_holdoff()
static void test_min_gain_clamp()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
agc.min_gain = 10;
agc.agc_base_gain = 12;
agc.gain_step_down = 4;
@@ -136,6 +140,7 @@ static void test_min_gain_clamp()
static void test_max_gain_clamp()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
agc.max_gain = 32;
agc.agc_base_gain = 31;
agc.gain_step_up = 2;
@@ -226,6 +231,7 @@ static void test_apply_gain_spi()
static void test_reset_preserves_config()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
agc.agc_base_gain = 42;
agc.gain_step_down = 8;
agc.cal_offset[3] = -5;
@@ -255,6 +261,7 @@ static void test_reset_preserves_config()
static void test_saturation_counter()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
for (int i = 0; i < 10; ++i) {
agc.update(true);
@@ -274,6 +281,7 @@ static void test_saturation_counter()
static void test_mixed_sequence()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
agc.agc_base_gain = 30;
agc.gain_step_down = 4;
agc.gain_step_up = 1;
9_Firmware/9_2_FPGA/ad9484_interface_400m.v
+61 -3
View File
@@ -4,15 +4,23 @@ module ad9484_interface_400m (
input wire [7:0] adc_d_n, // ADC Data N
input wire adc_dco_p, // Data Clock Output P (400MHz)
input wire adc_dco_n, // Data Clock Output N (400MHz)
// Audit F-0.1: AD9484 OR (overrange) LVDS pair, DDR like data.
// Routed on the 50T main board to bank 14 pins M6/N6. Asserts for any
// sample whose absolute value exceeds full-scale.
input wire adc_or_p,
input wire adc_or_n,
// System Interface
input wire sys_clk, // 100MHz system clock (for control only)
input wire reset_n,
// Output at 400MHz domain
output wire [7:0] adc_data_400m, // ADC data at 400MHz
output wire adc_data_valid_400m, // Valid at 400MHz
output wire adc_dco_bufg // Buffered 400MHz DCO clock for downstream use
output wire adc_dco_bufg, // Buffered 400MHz DCO clock for downstream use
// Audit F-0.1: OR flag, clk_400m domain. High on any sample in the
// current 400 MHz cycle where the ADC reports overrange.
output wire adc_overrange_400m
);
// LVDS to single-ended conversion
@@ -166,4 +174,54 @@ end
assign adc_data_400m = adc_data_400m_reg;
assign adc_data_valid_400m = adc_data_valid_400m_reg;
// ============================================================================
// Audit F-0.1: AD9484 OR (overrange) capture
// OR is a DDR LVDS pair (same as data). Buffer it, capture both edges with an
// IDDR in the BUFIO domain, then OR the two phases into a single clk_400m
// flag. Register once for stability. No latching — downstream is expected to
// stickify in its own domain.
// ============================================================================
wire adc_or_raw;
IBUFDS #(
.DIFF_TERM("FALSE"),
.IOSTANDARD("DEFAULT")
) ibufds_or (
.O(adc_or_raw),
.I(adc_or_p),
.IB(adc_or_n)
);
wire adc_or_rise;
wire adc_or_fall;
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.SRTYPE("SYNC")
) iddr_or (
.Q1(adc_or_rise),
.Q2(adc_or_fall),
.C(adc_dco_bufio),
.CE(1'b1),
.D(adc_or_raw),
.R(1'b0),
.S(1'b0)
);
reg adc_or_rise_bufg;
reg adc_or_fall_bufg;
always @(posedge adc_dco_buffered) begin
adc_or_rise_bufg <= adc_or_rise;
adc_or_fall_bufg <= adc_or_fall;
end
reg adc_overrange_r;
always @(posedge adc_dco_buffered or negedge reset_n_400m) begin
if (!reset_n_400m)
adc_overrange_r <= 1'b0;
else
adc_overrange_r <= adc_or_rise_bufg | adc_or_fall_bufg;
end
assign adc_overrange_400m = adc_overrange_r;
endmodule
9_Firmware/9_2_FPGA/cdc_modules.v
+36 -140
View File
@@ -17,7 +17,12 @@ module cdc_adc_to_processing #(
input wire [WIDTH-1:0] src_data,
input wire src_valid,
output wire [WIDTH-1:0] dst_data,
output wire dst_valid
output wire dst_valid,
// Audit F-1.2: overrun pulse in src_clk domain. Asserts for 1 src cycle
// whenever src_valid fires while the previous sample has not yet been
// acknowledged by the destination edge-detector (i.e., the transaction
// the CDC is silently dropping). Hold/count externally.
output wire overrun
`ifdef FORMAL
,output wire [WIDTH-1:0] fv_src_data_reg,
output wire [1:0] fv_src_toggle
@@ -130,6 +135,36 @@ module cdc_adc_to_processing #(
assign dst_data = dst_data_reg;
assign dst_valid = dst_valid_reg;
// ------------------------------------------------------------------
// Audit F-1.2: overrun detection
//
// The src-side `src_toggle` counter flips on each latched src_valid.
// We feed back a 1-bit "ack" toggle from the dst domain (flipped each
// time dst_valid fires) through a STAGES-deep synchronizer into the
// src domain. If a new src_valid arrives while src_toggle[0] already
// differs from the acked value, the previous sample is still in flight
// and this new latch drops it. Emit a 1-cycle overrun pulse.
// ------------------------------------------------------------------
reg dst_ack_toggle;
always @(posedge dst_clk) begin
if (!dst_reset_n) dst_ack_toggle <= 1'b0;
else if (dst_valid_reg) dst_ack_toggle <= ~dst_ack_toggle;
end
(* ASYNC_REG = "TRUE" *) reg [STAGES-1:0] ack_sync_chain;
always @(posedge src_clk) begin
if (!src_reset_n) ack_sync_chain <= {STAGES{1'b0}};
else ack_sync_chain <= {ack_sync_chain[STAGES-2:0], dst_ack_toggle};
end
wire ack_in_src = ack_sync_chain[STAGES-1];
reg overrun_r;
always @(posedge src_clk) begin
if (!src_reset_n) overrun_r <= 1'b0;
else overrun_r <= src_valid && (src_toggle[0] != ack_in_src);
end
assign overrun = overrun_r;
`ifdef FORMAL
assign fv_src_data_reg = src_data_reg;
assign fv_src_toggle = src_toggle;
@@ -137,145 +172,6 @@ module cdc_adc_to_processing #(
endmodule
// ============================================================================
// ASYNC FIFO FOR CONTINUOUS SAMPLE STREAMS
// ============================================================================
// Replaces cdc_adc_to_processing for the DDC path where the CIC decimator
// produces samples at ~100 MSPS from a 400 MHz clock and the consumer runs
// at 100 MHz. Gray-coded read/write pointers (the only valid use of Gray
// encoding across clock domains) ensure no data corruption or loss.
//
// Depth must be a power of 2. Default 8 entries gives comfortable margin
// for the 4:1 decimated stream (1 sample per 4 src clocks, 1 consumer
// clock per sample).
// ============================================================================
module cdc_async_fifo #(
parameter WIDTH = 18,
parameter DEPTH = 8, // Must be power of 2
parameter ADDR_BITS = 3 // log2(DEPTH)
)(
// Write (source) domain
input wire wr_clk,
input wire wr_reset_n,
input wire [WIDTH-1:0] wr_data,
input wire wr_en,
output wire wr_full,
// Read (destination) domain
input wire rd_clk,
input wire rd_reset_n,
output wire [WIDTH-1:0] rd_data,
output wire rd_valid,
input wire rd_ack // Consumer asserts to pop
);
// Gray code conversion functions
function [ADDR_BITS:0] bin2gray;
input [ADDR_BITS:0] bin;
bin2gray = bin ^ (bin >> 1);
endfunction
function [ADDR_BITS:0] gray2bin;
input [ADDR_BITS:0] gray;
reg [ADDR_BITS:0] bin;
integer k;
begin
bin[ADDR_BITS] = gray[ADDR_BITS];
for (k = ADDR_BITS-1; k >= 0; k = k - 1)
bin[k] = bin[k+1] ^ gray[k];
gray2bin = bin;
end
endfunction
// ------- Pointer declarations (both domains, before use) -------
// Write domain pointers
reg [ADDR_BITS:0] wr_ptr_bin = 0; // Extra bit for full/empty
reg [ADDR_BITS:0] wr_ptr_gray = 0;
// Read domain pointers (declared here so write domain can synchronize them)
reg [ADDR_BITS:0] rd_ptr_bin = 0;
reg [ADDR_BITS:0] rd_ptr_gray = 0;
// ------- Write domain -------
// Synchronized read pointer in write domain (scalar regs, not memory
// arrays — avoids iverilog sensitivity/NBA bugs on array elements and
// gives synthesis explicit flop names for ASYNC_REG constraints)
(* ASYNC_REG = "TRUE" *) reg [ADDR_BITS:0] rd_ptr_gray_sync0 = 0;
(* ASYNC_REG = "TRUE" *) reg [ADDR_BITS:0] rd_ptr_gray_sync1 = 0;
// FIFO memory (inferred as distributed RAM — small depth)
reg [WIDTH-1:0] mem [0:DEPTH-1];
wire wr_addr_match = (wr_ptr_gray == rd_ptr_gray_sync1);
wire wr_wrap_match = (wr_ptr_gray[ADDR_BITS] != rd_ptr_gray_sync1[ADDR_BITS]) &&
(wr_ptr_gray[ADDR_BITS-1] != rd_ptr_gray_sync1[ADDR_BITS-1]) &&
(wr_ptr_gray[ADDR_BITS-2:0] == rd_ptr_gray_sync1[ADDR_BITS-2:0]);
assign wr_full = wr_wrap_match;
always @(posedge wr_clk) begin
if (!wr_reset_n) begin
wr_ptr_bin <= 0;
wr_ptr_gray <= 0;
rd_ptr_gray_sync0 <= 0;
rd_ptr_gray_sync1 <= 0;
end else begin
// Synchronize read pointer into write domain
rd_ptr_gray_sync0 <= rd_ptr_gray;
rd_ptr_gray_sync1 <= rd_ptr_gray_sync0;
// Write
if (wr_en && !wr_full) begin
mem[wr_ptr_bin[ADDR_BITS-1:0]] <= wr_data;
wr_ptr_bin <= wr_ptr_bin + 1;
wr_ptr_gray <= bin2gray(wr_ptr_bin + 1);
end
end
end
// ------- Read domain -------
// Synchronized write pointer in read domain (scalar regs — see above)
(* ASYNC_REG = "TRUE" *) reg [ADDR_BITS:0] wr_ptr_gray_sync0 = 0;
(* ASYNC_REG = "TRUE" *) reg [ADDR_BITS:0] wr_ptr_gray_sync1 = 0;
wire rd_empty = (rd_ptr_gray == wr_ptr_gray_sync1);
// Output register — holds data until consumed
reg [WIDTH-1:0] rd_data_reg = 0;
reg rd_valid_reg = 0;
always @(posedge rd_clk) begin
if (!rd_reset_n) begin
rd_ptr_bin <= 0;
rd_ptr_gray <= 0;
wr_ptr_gray_sync0 <= 0;
wr_ptr_gray_sync1 <= 0;
rd_data_reg <= 0;
rd_valid_reg <= 0;
end else begin
// Synchronize write pointer into read domain
wr_ptr_gray_sync0 <= wr_ptr_gray;
wr_ptr_gray_sync1 <= wr_ptr_gray_sync0;
// Pop logic: present data when FIFO not empty
if (!rd_empty && (!rd_valid_reg || rd_ack)) begin
rd_data_reg <= mem[rd_ptr_bin[ADDR_BITS-1:0]];
rd_valid_reg <= 1'b1;
rd_ptr_bin <= rd_ptr_bin + 1;
rd_ptr_gray <= bin2gray(rd_ptr_bin + 1);
end else if (rd_valid_reg && rd_ack) begin
// Consumer took data but FIFO is empty now
rd_valid_reg <= 1'b0;
end
end
end
assign rd_data = rd_data_reg;
assign rd_valid = rd_valid_reg;
endmodule
// ============================================================================
// CDC FOR SINGLE BIT SIGNALS
// Uses synchronous reset on sync chain to avoid metastability on reset
9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v
+50 -10
View File
@@ -32,11 +32,50 @@ localparam COMB_WIDTH = 28;
// adjacent DSP48E1 tiles — zero fabric delay, guaranteed to meet 400+ MHz
// on 7-series regardless of speed grade.
//
// Active-high reset derived from reset_n (inverted).
// Active-high reset derived from reset_n (inverted and REGISTERED).
// CEP (clock enable for P register) gated by data_valid.
// ============================================================================
wire reset_h = ~reset_n; // active-high reset for DSP48E1 RSTP
//
// ----------------------------------------------------------------------------
// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
// ----------------------------------------------------------------------------
// Previously this was a combinational wire (`wire reset_h = ~reset_n`). Vivado
// collapsed all per-module inversions across the DDC hierarchy into a SINGLE
// shared LUT1, whose output fanned out to 702 loads (DSP48E1 RSTP/RSTB/RSTC
// plus FDRE R pins of all comb-stage DSP48E1s inferred via use_dsp="yes").
// Route delay alone on that net was 2.019–2.268 ns — nearly one full 2.5 ns
// period. Timing failed by 626 ps on the 400 MHz domain.
//
// Fix: convert reset_h to a REGISTERED signal with (* max_fanout = 50 *).
// Vivado treats max_fanout on a REG (not a wire) as authoritative and
// replicates the register into N copies, each placed near its ≈50 loads.
// Invariants preserved:
// I1 (correctness): reset_h is still active-high, equals ~reset_n
// after one clk edge; CIC reset is a RECEIVER-side
// synchronizer anyway (driven by reset_n_400m which
// is already sync'd in the parent DDC), so adding
// one more clk cycle of latency is safe.
// I2 (glitch-free): Registered output => inherently glitch-free,
// feeding DSP48E1 RST pins (which are synchronous
// to CLK, so they capture on the same edge anyway).
// I3 (power-up safety): reset_h is NOT async-reset itself. On power-up,
// FDRE INIT=0 starts reset_h LOW. First clk edge
// samples ~reset_n which is LOW on power-up (the
// parent DDC holds reset_n_400m low until the 2-
// stage synchronizer releases), so reset_h goes
// HIGH on cycle 1 and all DSPs see reset during
// the following cycles. System is held in reset
// for enough cycles that any initial register
// state garbage is overwritten. ✅
// I4 (reset de-assertion):reset_h goes LOW one cycle AFTER reset_n_400m
// goes HIGH. Downstream DSPs come out of reset on
// the next clk edge after that. Total latency
// from system reset release to first valid sample:
// 2 (sync chain) + 1 (reset_h reg) + 1 (first
// DSP output) = 4 cycles at 400 MHz = 10 ns.
// Negligible vs system reset assertion duration.
// ----------------------------------------------------------------------------
(* max_fanout = 25 *) reg reset_h = 1'b1; // INIT=1'b1: registers start in reset state on power-up
always @(posedge clk) reset_h <= ~reset_n;
// Sign-extended input for integrator_0 C port (48-bit)
wire [ACC_WIDTH-1:0] data_in_c = {{(ACC_WIDTH-18){data_in[17]}}, data_in};
@@ -699,10 +738,11 @@ initial begin
end
// Decimation control + monitoring (integrators are now DSP48E1 instances)
// Sync reset: enables FDRE inference for better timing at 400 MHz.
// Reset is already synchronous to clk via reset synchronizer in parent module.
// Sync reset via reset_h (registered, max_fanout=50) — eliminates the shared
// LUT1 inverter that previously fanned out to all fabric FDRE R pins plus
// DSP48E1 RST pins (702 loads total). See "RESET FAN-OUT INVARIANT" at top.
always @(posedge clk) begin
if (!reset_n) begin
if (reset_h) begin
integrator_sampled <= 0;
decimation_counter <= 0;
data_valid_delayed <= 0;
@@ -755,9 +795,9 @@ always @(posedge clk) begin
end
// Pipeline the valid signal for comb section
// Sync reset: matches decimation control block reset style.
// Sync reset via reset_h — same replicated-register source as DSP48E1 RSTs.
always @(posedge clk) begin
if (!reset_n) begin
if (reset_h) begin
data_valid_comb <= 0;
data_valid_comb_pipe <= 0;
data_valid_comb_0_out <= 0;
@@ -792,7 +832,7 @@ end
// - Each stage: comb[i] = comb[i-1] - comb_delay[i][last]
always @(posedge clk) begin
if (!reset_n) begin
if (reset_h) begin
for (i = 0; i < STAGES; i = i + 1) begin
comb[i] <= 0;
for (j = 0; j < COMB_DELAY; j = j + 1) begin
9_Firmware/9_2_FPGA/constraints/README.md
+8 -7
View File
@@ -32,8 +32,8 @@ the `USB_MODE` parameter in `radar_system_top.v`:
| USB_MODE | Interface | Bus Width | Speed | Board Target |
|----------|-----------|-----------|-------|--------------|
| 0 (default) | FT601 (USB 3.0) | 32-bit | 100 MHz | 200T premium dev board |
| 1 | FT2232H (USB 2.0) | 8-bit | 60 MHz | 50T production board |
| 0 | FT601 (USB 3.0) | 32-bit | 100 MHz | 200T premium dev board |
| 1 (default) | FT2232H (USB 2.0) | 8-bit | 60 MHz | 50T production board |
### How USB_MODE Works
@@ -72,7 +72,8 @@ The parameter is set via a **wrapper module** that overrides the default:
```
- **200T dev board**: `radar_system_top` is used directly as the top module.
`USB_MODE` defaults to `0` (FT601). No wrapper needed.
`USB_MODE` defaults to `1` (FT2232H) since production is the primary target.
Override with `.USB_MODE(0)` for FT601 builds.
### RTL Files by USB Interface
@@ -158,7 +159,7 @@ The build scripts automatically select the correct top module and constraints:
You do NOT need to set `USB_MODE` manually. The top module selection handles it:
- `radar_system_top_50t` forces `USB_MODE=1` internally
- `radar_system_top` defaults to `USB_MODE=0`
- `radar_system_top` defaults to `USB_MODE=1` (FT2232H, production default)
## How to Select Constraints in Vivado
@@ -190,9 +191,9 @@ read_xdc constraints/te0713_te0701_minimal.xdc
| Target | Top module | USB_MODE | USB Interface | Notes |
|--------|------------|----------|---------------|-------|
| 50T Production (FTG256) | `radar_system_top_50t` | 1 | FT2232H (8-bit) | Wrapper sets USB_MODE=1, ties off FT601 |
| 200T Dev (FBG484) | `radar_system_top` | 0 (default) | FT601 (32-bit) | No wrapper needed |
| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | 0 (default) | FT601 (32-bit) | Minimal bring-up wrapper |
| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | 0 (default) | FT601 (32-bit) | Alternate SoM wrapper |
| 200T Dev (FBG484) | `radar_system_top` | 0 (override) | FT601 (32-bit) | Build script overrides default USB_MODE=1 |
| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | 0 (override) | FT601 (32-bit) | Minimal bring-up wrapper |
| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | 0 (override) | FT601 (32-bit) | Alternate SoM wrapper |
## Trenz Split Status
9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
+23 -11
View File
@@ -33,10 +33,10 @@
# (one period) to ensure the tools verify the transfer fits within one cycle
# without over-constraining with full inter-clock setup/hold analysis.
set_max_delay -datapath_only -from [get_clocks adc_dco_p] \
-to [get_clocks clk_mmcm_out0] 2.500
-to [get_clocks clk_mmcm_out0] 2.700
set_max_delay -datapath_only -from [get_clocks clk_mmcm_out0] \
-to [get_clocks adc_dco_p] 2.500
-to [get_clocks adc_dco_p] 2.700
# --------------------------------------------------------------------------
# CDC: MMCM output domain ↔ other clock domains
@@ -47,8 +47,12 @@ set_max_delay -datapath_only -from [get_clocks clk_mmcm_out0] \
set_false_path -from [get_clocks clk_100m] -to [get_clocks clk_mmcm_out0]
set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks clk_100m]
set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft601_clk_in]
set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_mmcm_out0]
# Audit F-0.6: the USB-domain clock name differs per board
# (50T: ft_clkout, 200T: ft601_clk_in). XDC files only support a
# restricted Tcl subset — `foreach`/`unset` trigger CRITICAL WARNING
# [Designutils 20-1307]. The clk_mmcm_out0 ↔ USB-clock false paths
# are declared in the per-board XDC (xc7a50t_ftg256.xdc and
# xc7a200t_fbg484.xdc) where the USB clock name is already known.
set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks clk_120m_dac]
set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_mmcm_out0]
@@ -59,7 +63,10 @@ set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_mmcm_out0]
# LOCKED is not a valid timing startpoint (it's a combinational output of the
# MMCM primitive). Use -through instead of -from to waive all paths that pass
# through the LOCKED net. This avoids the CRITICAL WARNING from Build 19/20.
set_false_path -through [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED]
# Audit F-0.7: the literal hierarchical path was missing the `u_core/`
# prefix and silently matched no pins. Use a hierarchical wildcard to
# catch the MMCM LOCKED pin regardless of wrapper hierarchy.
set_false_path -through [get_pins -hierarchical -filter {REF_PIN_NAME == LOCKED}]
# --------------------------------------------------------------------------
# Hold waiver for source-synchronous ADC capture (BUFIO-clocked IDDR)
@@ -82,14 +89,19 @@ set_false_path -through [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED]
#
# Waiving hold on these 8 paths (adc_d_p[0..7] → IDDR) is standard practice
# for source-synchronous LVDS ADC interfaces using BUFIO capture.
set_false_path -hold -from [get_ports {adc_d_p[*]}] -to [get_clocks adc_dco_p]
# adc_or_p (AD9484 overrange, audit F-0.1) shares the same IBUFDS→BUFIO
# source-synchronous capture topology as adc_d_p[*] — same ~1.9 ns STA hold
# violation for the same reason (BUFIO clock insertion ~4 ns vs data IBUFDS
# ~0.9 ns), resolved by the same external-timing argument.
set_false_path -hold -from [get_ports {adc_d_p[*] adc_or_p}] -to [get_clocks adc_dco_p]
# --------------------------------------------------------------------------
# Timing margin for 400 MHz critical paths
# --------------------------------------------------------------------------
# Extra setup uncertainty forces Vivado to leave margin for temperature/voltage/
# aging variation. Reduced from 200 ps to 100 ps after NCO→mixer pipeline
# register fix eliminated the dominant timing bottleneck (WNS went from +0.002ns
# to comfortable margin). 100 ps still provides ~4% guardband on the 2.5ns period.
# This is additive to the existing jitter-based uncertainty (~53 ps).
set_clock_uncertainty -setup -add 0.100 [get_clocks clk_mmcm_out0]
# aging variation. 150 ps absolute covers the built-in jitter-based value
# (~53 ps) plus ~100 ps temperature/voltage/aging guardband.
# NOTE: Vivado's set_clock_uncertainty does NOT accept -add; prior use of
# -add 0.100 was silently rejected as a CRITICAL WARNING, so no guardband
# was applied. Use an absolute value. (audit finding F-0.8)
set_clock_uncertainty -setup 0.150 [get_clocks clk_mmcm_out0]
9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc
+20
View File
@@ -134,6 +134,22 @@ set_property IOSTANDARD LVDS_25 [get_ports {adc_d_p[*]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_d_n[*]}]
set_property DIFF_TERM TRUE [get_ports {adc_d_p[*]}]
# --------------------------------------------------------------------------
# Audit F-0.1: AD9484 OR (overrange) LVDS pair
# The 50T main board schematic routes ADC_OR_P/N to bank-14 pins M6/N6 on
# xc7a50t-ftg256. The 200T dev-board schematic has NOT been checked yet;
# adc_or_p/n are declared as top-level ports so the 50T build anchors them
# cleanly, but the 200T anchor below is a TODO placeholder — synth/impl will
# error on unplaced IO until the 200T schematic is verified and the PACKAGE_PIN
# values are set. IOSTANDARD/DIFF_TERM properties stay as-is (same class as
# adc_d_p).
# --------------------------------------------------------------------------
set_property IOSTANDARD LVDS_25 [get_ports {adc_or_p}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_or_n}]
set_property DIFF_TERM TRUE [get_ports {adc_or_p}]
# TODO(F-0.1): set_property PACKAGE_PIN <?> [get_ports {adc_or_p}] after 200T schematic audit
# TODO(F-0.1): set_property PACKAGE_PIN <?> [get_ports {adc_or_n}] after 200T schematic audit
# ADC Power Down — single-ended, Bank 14 (LVCMOS25 matches bank VCCO)
# Pin: P20 = IO_0_14
set_property PACKAGE_PIN P20 [get_ports {adc_pwdn}]
@@ -621,6 +637,10 @@ set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_120m_dac]
set_false_path -from [get_clocks adc_dco_p] -to [get_clocks ft601_clk_in]
set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks adc_dco_p]
# MMCM 400 MHz domain ↔ FT601 USB clock (see adc_clk_mmcm.xdc for rationale)
set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft601_clk_in]
set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_mmcm_out0]
# Generated clock cross-domain paths:
# dac_clk_fwd and ft601_clk_fwd are generated from their respective source
# clocks. Vivado automatically inherits the source clock false paths for
9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc
+93 -11
View File
@@ -70,9 +70,10 @@ set_input_jitter [get_clocks clk_100m] 0.1
# NOTE: The physical DAC (U3, AD9708) receives its clock directly from the
# AD9523 via a separate net (DAC_CLOCK), NOT from the FPGA. The FPGA
# uses this clock input for internal DAC data timing only. The RTL port
# `dac_clk` is an output that assigns clk_120m directly — it has no
# separate physical pin on this board and should be removed from the
# RTL or left unconnected.
# `dac_clk` is an RTL output that assigns clk_120m directly. It has no
# physical pin on the 50T board and is left unconnected here. The port
# CANNOT be removed from the RTL because the 200T board uses it with
# ODDR clock forwarding (pin H17, see xc7a200t_fbg484.xdc).
# FIX: Moved from C13 (IO_L12N = N-type) to D13 (IO_L12P = P-type MRCC).
# Clock inputs must use the P-type pin of an MRCC pair (PLIO-9 DRC).
set_property PACKAGE_PIN D13 [get_ports {clk_120m_dac}]
@@ -106,8 +107,15 @@ set_property PACKAGE_PIN C4 [get_ports {ft_clkout}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft_clkout}]
create_clock -name ft_clkout -period 16.667 [get_ports {ft_clkout}]
set_input_jitter [get_clocks ft_clkout] 0.2
# N-type MRCC pin requires dedicated route override (Place 30-876)
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {ft_clkout_IBUF}]
# N-type MRCC pin requires dedicated route override (Place 30-876).
# Audit F-0.4: the literal net name `ft_clkout_IBUF` exists post-synth but
# the XDC scan happens before synthesis, when the IBUF net does not yet
# exist — Vivado reported `No nets matched 'ft_clkout_IBUF'` + CRITICAL
# WARNING. Use -hierarchical -filter + -quiet so the constraint matches
# post-synth without warning during pre-synth XDC scan. The TCL duplicate
# at scripts/50t/build_50t.tcl:119 remains as belt-and-suspenders.
set_property -quiet CLOCK_DEDICATED_ROUTE FALSE \
[get_nets -quiet -hierarchical -filter {NAME =~ *ft_clkout_IBUF}]
# ============================================================================
# RESET (Active-Low)
@@ -224,7 +232,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {stm32_mixers_enable}]
# DIG_5 = H11, DIG_6 = G12, DIG_7 = H12 — FPGA→STM32 status outputs
# DIG_5: AGC saturation flag (PD13 on STM32)
# DIG_6: reserved (PD14)
# DIG_6: AGC enable flag (PD14) — mirrors FPGA host_agc_enable to STM32
# DIG_7: reserved (PD15)
set_property PACKAGE_PIN H11 [get_ports {gpio_dig5}]
set_property PACKAGE_PIN G12 [get_ports {gpio_dig6}]
@@ -282,6 +290,22 @@ set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_d_p[*]}]
set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
# --------------------------------------------------------------------------
# Audit F-0.1: AD9484 OR (overrange) LVDS pair (Bank 14)
# Schematic RADAR_Main_Board.sch: ADC_OR_P → U42 IO_L19P_T3_A10_D26_14 (M6)
# ADC_OR_N → U42 IO_L19N_T3_A09_D25_VREF_14 (N6)
# DDR-sourced by adc_dco_p, same timing class as adc_d_p[*].
# --------------------------------------------------------------------------
set_property PACKAGE_PIN M6 [get_ports {adc_or_p}]
set_property PACKAGE_PIN N6 [get_ports {adc_or_n}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_or_p}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_or_n}]
set_property DIFF_TERM TRUE [get_ports {adc_or_p}]
set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 [get_ports {adc_or_p}]
set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_or_p}]
set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_or_p}] -add_delay
set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_or_p}] -add_delay
# ============================================================================
# FT2232H USB 2.0 INTERFACE (Bank 35, VCCO=3.3V)
# ============================================================================
@@ -332,6 +356,50 @@ set_property DRIVE 8 [get_ports {ft_data[*]}]
# ft_clkout constrained above in CLOCK CONSTRAINTS section (C4, 60 MHz)
# --------------------------------------------------------------------------
# FT2232H Source-Synchronous Timing Constraints
# --------------------------------------------------------------------------
# FT2232H 245 Synchronous FIFO mode timing (60 MHz, period = 16.667 ns).
# Values per FTDI TN_167 "FT2232H Synchronous FIFO Bus Bridge" — verify
# against the exact app-note revision before shipping.
#
# FPGA Read Path (FT2232H drives data/RXF#/TXE#, FPGA samples on CLKOUT↑):
# - t_co (CLKOUT↑ → data valid) max = 10.0 ns
# - t_coh (CLKOUT↑ → data hold) min = 0.5 ns
# - set_input_delay -max = t_co, -min = t_coh
#
# FPGA Write Path (FPGA drives data/WR#/RD#/OE#, FT2232H samples on CLKOUT↑):
# - t_su (data setup before CLKOUT↑) min = 3.5 ns (NOT 5 ns — prior
# constraint used a synthetic period-based back-calculation)
# - t_h (data hold after CLKOUT↑) min = 1.0 ns (NOT 0 — a 0 ns hold
# constraint produced no hold check at all)
# - set_output_delay -max = t_su, -min = -t_h (Vivado convention)
#
# Audit F-2026-04-20 Option B: the previous output_delay = 11.667 ns
# (= period − 5) over-constrained launch by ~8 ns vs the actual datasheet
# figure. Relaxing to 3.5 ns matches the chip's real setup requirement.
# --------------------------------------------------------------------------
# Input delays: FT2232H → FPGA (data bus and status signals)
set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_data[*]}]
set_input_delay -clock [get_clocks ft_clkout] -min 0.5 [get_ports {ft_data[*]}]
set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_rxf_n}]
set_input_delay -clock [get_clocks ft_clkout] -min 0.5 [get_ports {ft_rxf_n}]
set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_txe_n}]
set_input_delay -clock [get_clocks ft_clkout] -min 0.5 [get_ports {ft_txe_n}]
# Output delays: FPGA → FT2232H (control strobes and data bus when writing)
set_output_delay -clock [get_clocks ft_clkout] -max 3.5 [get_ports {ft_data[*]}]
set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_data[*]}]
set_output_delay -clock [get_clocks ft_clkout] -max 3.5 [get_ports {ft_rd_n}]
set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_rd_n}]
set_output_delay -clock [get_clocks ft_clkout] -max 3.5 [get_ports {ft_wr_n}]
set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_wr_n}]
set_output_delay -clock [get_clocks ft_clkout] -max 3.5 [get_ports {ft_oe_n}]
set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_oe_n}]
set_output_delay -clock [get_clocks ft_clkout] -max 3.5 [get_ports {ft_siwu}]
set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_siwu}]
# ============================================================================
# STATUS / DEBUG OUTPUTS — NO PHYSICAL CONNECTIONS
# ============================================================================
@@ -369,7 +437,17 @@ set_false_path -from [get_ports {stm32_mixers_enable}]
# - Reset deassertion order is not functionally critical — all registers
# come out of reset within a few cycles of each other
# --------------------------------------------------------------------------
set_false_path -from [get_cells reset_sync_reg[*]] -to [get_pins -filter {REF_PIN_NAME == CLR} -of_objects [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ REGISTER.*.*}]]
# Audit F-0.5: the literal cell name `reset_sync_reg[*]` does not match any
# cell in the post-synth netlist. The actual sync regs are
# `u_core/reset_sync_reg[0..1]`, `u_core/rx_inst/ddc/reset_sync_400m_reg[*]`,
# `u_core/gen_ft2232h.usb_inst/ft_reset_sync_reg[*]`, and peers under
# `u_core/reset_sync_120m_reg[*]`, `u_core/reset_sync_ft601_reg[*]`,
# `u_core/rx_inst/adc/reset_sync_400m_reg[*]`. The waiver below covers all
# of them by matching any register whose name contains `reset_sync`.
# Without this, STA runs recovery/removal on the fanout of each sync-chain
# output register (up to ~1000 loads pre-PR#113 replication).
set_false_path -from [get_cells -hierarchical -filter {NAME =~ *reset_sync*_reg*}] \
-to [get_pins -hierarchical -filter {REF_PIN_NAME == CLR || REF_PIN_NAME == PRE}]
# --------------------------------------------------------------------------
# Clock Domain Crossing false paths
@@ -391,6 +469,10 @@ set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_100m]
set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks ft_clkout]
set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_120m_dac]
# MMCM 400 MHz domain ↔ FT2232H USB clock (see adc_clk_mmcm.xdc for rationale)
set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft_clkout]
set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_mmcm_out0]
# ============================================================================
# PHYSICAL CONSTRAINTS
# ============================================================================
@@ -418,10 +500,10 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
# 4. JTAG: FPGA_TCK (L7), FPGA_TDI (N7), FPGA_TDO (N8), FPGA_TMS (M7).
# Dedicated pins — no XDC constraints needed.
#
# 5. dac_clk port: The RTL top module declares `dac_clk` as an output, but
# the physical board wires the DAC clock (AD9708 CLOCK pin) directly from
# the AD9523, not from the FPGA. This port should be removed from the RTL
# or left unconnected. It currently just assigns clk_120m_dac passthrough.
# 5. dac_clk port: Not connected on the 50T board (DAC clocked directly from
# AD9523). The RTL port exists for 200T board compatibility, where the FPGA
# forwards the DAC clock via ODDR to pin H17 with generated clock and
# timing constraints (see xc7a200t_fbg484.xdc). Do NOT remove from RTL.
#
# ============================================================================
# END OF CONSTRAINTS
9_Firmware/9_2_FPGA/ddc_400m.v
+380 -357
View File
@@ -1,106 +1,69 @@
`timescale 1ns / 1ps
module ddc_400m_enhanced (
input wire clk_400m, // 400MHz clock from ADC DCO
input wire clk_100m, // 100MHz system clock
input wire reset_n,
input wire mixers_enable,
input wire [7:0] adc_data, // ADC data at 400MHz
`timescale 1ns / 1ps
module ddc_400m_enhanced (
input wire clk_400m, // 400MHz clock from ADC DCO
input wire clk_100m, // 100MHz system clock
input wire reset_n,
input wire mixers_enable,
input wire [7:0] adc_data, // ADC data at 400MHz
input wire adc_data_valid_i, // Valid at 400MHz
input wire adc_data_valid_q,
output wire signed [17:0] baseband_i,
output wire signed [17:0] baseband_q,
input wire adc_data_valid_q,
output wire signed [17:0] baseband_i,
output wire signed [17:0] baseband_q,
output wire baseband_valid_i,
output wire baseband_valid_q,
output wire [1:0] ddc_status,
// Enhanced interfaces
output wire [7:0] ddc_diagnostics,
output wire baseband_valid_q,
output wire [1:0] ddc_status,
// Enhanced interfaces
output wire [7:0] ddc_diagnostics,
output wire mixer_saturation,
output wire filter_overflow,
input wire [1:0] test_mode,
input wire [15:0] test_phase_inc,
input wire force_saturation,
input wire reset_monitors,
output wire [31:0] debug_sample_count,
output wire [17:0] debug_internal_i,
output wire [17:0] debug_internal_q
);
// Parameters for numerical precision
parameter ADC_WIDTH = 8;
parameter NCO_WIDTH = 16;
parameter MIXER_WIDTH = 18;
parameter OUTPUT_WIDTH = 18;
// IF frequency parameters
parameter IF_FREQ = 120000000;
parameter FS = 400000000;
parameter PHASE_WIDTH = 32;
// Internal signals
wire signed [15:0] sin_out, cos_out;
wire nco_ready;
wire cic_valid;
wire fir_valid;
wire [17:0] cic_i_out, cic_q_out;
wire signed [17:0] fir_i_out, fir_q_out;
input wire [1:0] test_mode,
input wire [15:0] test_phase_inc,
input wire force_saturation,
input wire reset_monitors,
output wire [31:0] debug_sample_count,
output wire [17:0] debug_internal_i,
output wire [17:0] debug_internal_q,
// Audit F-1.2: sticky CIC→FIR CDC overrun flag (clk_400m domain). Goes
// high on the first dropped sample and stays high until reset_monitors.
output wire cdc_cic_fir_overrun
);
// Parameters for numerical precision
parameter ADC_WIDTH = 8;
parameter NCO_WIDTH = 16;
parameter MIXER_WIDTH = 18;
parameter OUTPUT_WIDTH = 18;
// IF frequency parameters
parameter IF_FREQ = 120000000;
parameter FS = 400000000;
parameter PHASE_WIDTH = 32;
// Internal signals
wire signed [15:0] sin_out, cos_out;
wire nco_ready;
wire cic_valid;
wire fir_valid;
wire [17:0] cic_i_out, cic_q_out;
wire signed [17:0] fir_i_out, fir_q_out;
// Diagnostic registers
reg [2:0] saturation_count;
reg overflow_detected;
reg [7:0] error_counter;
// ============================================================================
// 400 MHz Reset Synchronizer
//
// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
// Using it directly as an async reset in the 400 MHz domain causes the reset
// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
// domain, requiring 18.243ns of routing (WNS = -18.081ns).
//
// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
// path from reset_n to all 400 MHz registers). Reset deassertion is
// synchronized to clk_400m rising edge, preventing metastability.
//
// All 400 MHz submodules (NCO, CIC, mixers, LFSR) use reset_n_400m.
// All 100 MHz submodules (FIR, output stage) continue using reset_n directly
// (already synchronized to 100 MHz at radar_system_top level).
// ============================================================================
(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
// Active-high reset for DSP48E1 RST ports (avoids LUT1 inverter fan-out)
(* max_fanout = 50 *) reg reset_400m;
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
reset_sync_400m <= 2'b00;
reset_400m <= 1'b1;
end else begin
reset_sync_400m <= {reset_sync_400m[0], 1'b1};
reset_400m <= ~reset_sync_400m[1];
end
end
// CDC synchronization for control signals (2-stage synchronizers)
(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
wire mixers_enable_sync;
wire force_saturation_sync;
// Debug monitoring signals
reg [31:0] sample_counter;
wire signed [17:0] debug_mixed_i_trunc;
wire signed [17:0] debug_mixed_q_trunc;
// Real-time status monitoring
reg [7:0] signal_power_i, signal_power_q;
reg [7:0] signal_power_i, signal_power_q;
// Internal mixing signals
// Pipeline: NCO fabric reg (1) + DSP48E1 AREG/BREG (1) + MREG (1) + PREG (1) + retiming (1) = 5 cycles
// The NCO fabric pipeline register was added to break the long NCO→DSP B-port route
@@ -118,61 +81,110 @@ reg [4:0] dsp_valid_pipe;
// Post-DSP retiming registers — breaks DSP48E1 CLK→P to fabric timing path
// This extra pipeline stage absorbs the 1.866ns DSP output prop delay + routing,
// ensuring WNS > 0 at 400 MHz regardless of placement seed
(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
// Output stage registers
reg signed [17:0] baseband_i_reg, baseband_q_reg;
reg baseband_valid_reg;
// ============================================================================
(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
// Output stage registers
reg signed [17:0] baseband_i_reg, baseband_q_reg;
reg baseband_valid_reg;
// ============================================================================
// Phase Dithering Signals
// ============================================================================
wire [7:0] phase_dither_bits;
reg [31:0] phase_inc_dithered;
// ============================================================================
// Debug Signal Assignments
// ============================================================================
assign debug_internal_i = mixed_i[25:8];
assign debug_internal_q = mixed_q[25:8];
assign debug_sample_count = sample_counter;
assign debug_mixed_i_trunc = mixed_i[25:8];
assign debug_mixed_q_trunc = mixed_q[25:8];
// ============================================================================
// Clock Domain Crossing for Control Signals (2-stage synchronizers)
reg [31:0] phase_inc_dithered;
// ============================================================================
assign mixers_enable_sync = mixers_enable_sync_chain[1];
// Debug Signal Assignments
// ============================================================================
assign debug_internal_i = mixed_i[25:8];
assign debug_internal_q = mixed_q[25:8];
assign debug_sample_count = sample_counter;
assign debug_mixed_i_trunc = mixed_i[25:8];
assign debug_mixed_q_trunc = mixed_q[25:8];
// ============================================================================
// 400 MHz Reset Synchronizer
//
// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
// Using it directly as an async reset in the 400 MHz domain causes the reset
// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
// domain, requiring 18.243ns of routing (WNS = -18.081ns).
//
// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
// path from reset_n to all 400 MHz registers). Reset deassertion is
//
// reset_400m : ACTIVE-HIGH registered reset with (* max_fanout = 50 *).
// This is THE signal fed to every synchronous 400 MHz FDRE
// and every DSP48E1 RST pin in this module and its children
// (NCO, CIC, LFSR). Vivado replicates the register (~14
// copies) so each replica drives ≈50 loads regionally,
// eliminating the single-LUT1 / 702-load net that caused
// WNS=-0.626 ns in Build N.
//
// System-level invariants preserved:
// I1 Reset assertion propagates to all 400 MHz regs within ≤3 clk edges
// (2 sync + 1 replicated-reg fanout). At 400 MHz = 7.5 ns << any
// system-level reset assertion duration.
// I2 Reset de-assertion is always synchronous to clk_400m (via
// reset_sync_400m), never glitches.
// I3 DSP48E1 RST pins are all fed from Q of a register — glitch-free.
// I4 No new CDC introduced: reset_400m is entirely in clk_400m domain.
// I5 Power-up: reset_n is asserted externally and mmcm_locked is low;
// reset_sync_400m stays 2'b00, reset_400m stays 1'b1, downstream
// FDREs stay cleared. Safe.
// ============================================================================
(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m = 2'b00;
(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
// Active-high replicated reset for all synchronous 400 MHz consumers
(* max_fanout = 50 *) reg reset_400m = 1'b1;
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
reset_sync_400m <= 2'b00;
reset_400m <= 1'b1;
end else begin
reset_sync_400m <= {reset_sync_400m[0], 1'b1};
reset_400m <= ~reset_sync_400m[1];
end
end
// CDC synchronization for control signals (2-stage synchronizers).
// Audit F-1.3: the mixers_enable synchronizer was dead — its _sync output
// was never consumed (the NCO phase_valid uses the raw port), and the only
// caller (radar_receiver_final.v) ties the port to 1'b1. Removed.
(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
wire force_saturation_sync;
assign force_saturation_sync = force_saturation_sync_chain[1];
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
mixers_enable_sync_chain <= 2'b00;
// Sync reset via reset_400m (replicated, max_fanout=50). Was async on
// reset_n_400m — see "400 MHz RESET DISTRIBUTION" comment above.
always @(posedge clk_400m) begin
if (reset_400m) begin
force_saturation_sync_chain <= 2'b00;
end else begin
mixers_enable_sync_chain <= {mixers_enable_sync_chain[0], mixers_enable};
force_saturation_sync_chain <= {force_saturation_sync_chain[0], force_saturation};
end
end
// ============================================================================
// Sample Counter and Debug Monitoring
// ============================================================================
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m || reset_monitors) begin
end
// ============================================================================
// Sample Counter and Debug Monitoring
// ============================================================================
always @(posedge clk_400m) begin
if (reset_400m || reset_monitors) begin
sample_counter <= 0;
error_counter <= 0;
end else if (adc_data_valid_i && adc_data_valid_q ) begin
sample_counter <= sample_counter + 1;
end
end
// ============================================================================
// Enhanced Phase Dithering Instance
// ============================================================================
error_counter <= 0;
end else if (adc_data_valid_i && adc_data_valid_q ) begin
sample_counter <= sample_counter + 1;
end
end
// ============================================================================
// Enhanced Phase Dithering Instance
// ============================================================================
lfsr_dither_enhanced #(
.DITHER_WIDTH(8)
) phase_dither_gen (
@@ -180,36 +192,36 @@ lfsr_dither_enhanced #(
.reset_n(reset_n_400m),
.enable(nco_ready),
.dither_out(phase_dither_bits)
);
// ============================================================================
// Phase Increment Calculation with Dithering
// ============================================================================
// Calculate phase increment for 120MHz IF at 400MHz sampling
localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
);
// ============================================================================
// Phase Increment Calculation with Dithering
// ============================================================================
// Calculate phase increment for 120MHz IF at 400MHz sampling
localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
// Apply dithering to reduce spurious tones (registered for 400 MHz timing)
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m)
always @(posedge clk_400m) begin
if (reset_400m)
phase_inc_dithered <= PHASE_INC_120MHZ;
else
phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
end
// ============================================================================
// Enhanced NCO with Diagnostics
// ============================================================================
end
// ============================================================================
// Enhanced NCO with Diagnostics
// ============================================================================
nco_400m_enhanced nco_core (
.clk_400m(clk_400m),
.reset_n(reset_n_400m),
.frequency_tuning_word(phase_inc_dithered),
.phase_valid(mixers_enable),
.phase_offset(16'h0000),
.sin_out(sin_out),
.cos_out(cos_out),
.dds_ready(nco_ready)
);
.reset_n(reset_n_400m),
.frequency_tuning_word(phase_inc_dithered),
.phase_valid(mixers_enable),
.phase_offset(16'h0000),
.sin_out(sin_out),
.cos_out(cos_out),
.dds_ready(nco_ready)
);
// ============================================================================
// Enhanced Mixing Stage — DSP48E1 direct instantiation for 400 MHz timing
//
@@ -229,8 +241,8 @@ assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
{1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
// Valid pipeline: 5-stage shift register (1 NCO pipe + 3 DSP48E1 AREG+MREG+PREG + 1 retiming)
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
always @(posedge clk_400m) begin
if (reset_400m) begin
dsp_valid_pipe <= 5'b00000;
end else begin
dsp_valid_pipe <= {dsp_valid_pipe[3:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
@@ -246,8 +258,8 @@ reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal; // Mod
reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg; // Models PREG
// Stage 0: NCO pipeline — breaks long NCO→DSP route (matches synthesis fabric registers)
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
always @(posedge clk_400m) begin
if (reset_400m) begin
cos_nco_pipe <= 0;
sin_nco_pipe <= 0;
end else begin
@@ -257,8 +269,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
end
// Stage 1: AREG/BREG equivalent (uses pipelined NCO outputs)
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
always @(posedge clk_400m) begin
if (reset_400m) begin
adc_signed_reg <= 0;
cos_pipe_reg <= 0;
sin_pipe_reg <= 0;
@@ -270,8 +282,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
end
// Stage 2: MREG equivalent
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
always @(posedge clk_400m) begin
if (reset_400m) begin
mult_i_internal <= 0;
mult_q_internal <= 0;
end else begin
@@ -281,8 +293,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
end
// Stage 3: PREG equivalent
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
always @(posedge clk_400m) begin
if (reset_400m) begin
mult_i_reg <= 0;
mult_q_reg <= 0;
end else begin
@@ -292,8 +304,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
end
// Stage 4: Post-DSP retiming register (matches synthesis path)
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
always @(posedge clk_400m) begin
if (reset_400m) begin
mult_i_retimed <= 0;
mult_q_retimed <= 0;
end else begin
@@ -311,8 +323,8 @@ wire [47:0] dsp_p_i, dsp_p_q;
// (1.505ns routing observed in Build 26). These fabric registers are placed
// near the DSP by the placer, splitting the route into two shorter segments.
// DONT_TOUCH on the reg declaration (above) prevents absorption/retiming.
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
always @(posedge clk_400m) begin
if (reset_400m) begin
cos_nco_pipe <= 0;
sin_nco_pipe <= 0;
end else begin
@@ -329,11 +341,10 @@ DSP48E1 #(
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
// Pipeline register attributes — all enabled for max timing
.AREG(1),
.BREG(1),
.MREG(1),
.PREG(1), // P register enabled — absorbs CLK→P delay for timing closure
.PREG(1),
.ADREG(0),
.ACASCREG(1),
.BCASCREG(1),
@@ -344,7 +355,6 @@ DSP48E1 #(
.DREG(0),
.INMODEREG(0),
.OPMODEREG(0),
// Pattern detector (unused)
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
@@ -496,8 +506,8 @@ wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WID
// Stage 4: Post-DSP retiming register — breaks DSP48E1 CLK→P to fabric path
// Without this, the DSP output prop delay (1.866ns) + routing (0.515ns) exceeds
// the 2.500ns clock period at slow process corner
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
always @(posedge clk_400m) begin
if (reset_400m) begin
mult_i_retimed <= 0;
mult_q_retimed <= 0;
end else begin
@@ -513,8 +523,8 @@ end
// force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
// polluting the critical input path with extra logic
// ============================================================================
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
always @(posedge clk_400m) begin
if (reset_400m) begin
mixed_i <= 0;
mixed_q <= 0;
mixed_valid <= 0;
@@ -556,151 +566,155 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
mixer_overflow_q <= 0;
overflow_detected <= 1'b0;
end
end
// ============================================================================
// Enhanced CIC Decimators
// ============================================================================
wire cic_valid_i, cic_valid_q;
end
// ============================================================================
// Enhanced CIC Decimators
// ============================================================================
wire cic_valid_i, cic_valid_q;
cic_decimator_4x_enhanced cic_i_inst (
.clk(clk_400m),
.reset_n(reset_n_400m),
.data_in(mixed_i[33:16]),
.data_valid(mixed_valid),
.data_out(cic_i_out),
.data_out_valid(cic_valid_i)
);
.reset_n(reset_n_400m),
.data_in(mixed_i[33:16]),
.data_valid(mixed_valid),
.data_out(cic_i_out),
.data_out_valid(cic_valid_i)
);
cic_decimator_4x_enhanced cic_q_inst (
.clk(clk_400m),
.reset_n(reset_n_400m),
.data_in(mixed_q[33:16]),
.data_valid(mixed_valid),
.data_out(cic_q_out),
.data_out_valid(cic_valid_q)
);
.reset_n(reset_n_400m),
.data_in(mixed_q[33:16]),
.data_valid(mixed_valid),
.data_out(cic_q_out),
.data_out_valid(cic_valid_q)
);
assign cic_valid = cic_valid_i & cic_valid_q;
// ============================================================================
// Clock Domain Crossing: 400 MHz CIC output → 100 MHz FIR input
// ============================================================================
// The CIC decimates 4:1, producing one sample per 4 clk_400m cycles (~100 MSPS).
// The FIR runs at clk_100m (100 MHz). The two clocks have unknown phase
// relationship, so a proper asynchronous FIFO with Gray-coded pointers is
// required. The old cdc_adc_to_processing module Gray-encoded the sample
// DATA which is invalid (Gray encoding only guarantees single-bit transitions
// for monotonically incrementing counters, not arbitrary sample values).
//
// Depth 8 provides margin: worst case, 2 samples can be in flight before
// the read side pops, well within a depth-8 budget.
// Enhanced FIR Filters with FIXED valid signal handling
// NOTE: Wire declarations moved BEFORE CDC instances to fix forward-reference
// error in Icarus Verilog (was originally after CDC instantiation)
// ============================================================================
wire fir_in_valid_i, fir_in_valid_q;
wire fir_valid_i, fir_valid_q;
wire fir_i_ready, fir_q_ready;
wire [17:0] fir_d_in_i, fir_d_in_q;
// Audit F-1.2: per-lane CIC→FIR CDC overrun pulses (clk_400m domain)
wire cdc_fir_i_overrun;
wire cdc_fir_q_overrun;
// I-channel CDC: async FIFO, 400 MHz write → 100 MHz read
cdc_async_fifo #(
cdc_adc_to_processing #(
.WIDTH(18),
.DEPTH(8),
.ADDR_BITS(3)
) CDC_FIR_i (
.wr_clk(clk_400m),
.wr_reset_n(reset_n_400m),
.wr_data(cic_i_out),
.wr_en(cic_valid_i),
.wr_full(), // At 1:1 data rate, overflow should not occur
.rd_clk(clk_100m),
.rd_reset_n(reset_n),
.rd_data(fir_d_in_i),
.rd_valid(fir_in_valid_i),
.rd_ack(fir_in_valid_i) // Auto-pop: consume every valid sample
.STAGES(3)
)CDC_FIR_i(
.src_clk(clk_400m),
.dst_clk(clk_100m),
.src_reset_n(reset_n_400m),
.dst_reset_n(reset_n),
.src_data(cic_i_out),
.src_valid(cic_valid_i),
.dst_data(fir_d_in_i),
.dst_valid(fir_in_valid_i),
.overrun(cdc_fir_i_overrun)
);
// Q-channel CDC: async FIFO, 400 MHz write → 100 MHz read
cdc_async_fifo #(
cdc_adc_to_processing #(
.WIDTH(18),
.DEPTH(8),
.ADDR_BITS(3)
) CDC_FIR_q (
.wr_clk(clk_400m),
.wr_reset_n(reset_n_400m),
.wr_data(cic_q_out),
.wr_en(cic_valid_q),
.wr_full(),
.STAGES(3)
)CDC_FIR_q(
.src_clk(clk_400m),
.dst_clk(clk_100m),
.src_reset_n(reset_n_400m),
.dst_reset_n(reset_n),
.src_data(cic_q_out),
.src_valid(cic_valid_q),
.dst_data(fir_d_in_q),
.dst_valid(fir_in_valid_q),
.overrun(cdc_fir_q_overrun)
);
// Audit F-1.2: sticky-latch the two per-lane overrun pulses in the 400 MHz
// domain and expose a single module-level flag. Cleared only by
// reset_monitors (or reset_n via reset_400m), matching the other DDC
// diagnostic latches (overflow/saturation).
reg cdc_cic_fir_overrun_sticky;
always @(posedge clk_400m) begin
if (reset_400m || reset_monitors) cdc_cic_fir_overrun_sticky <= 1'b0;
else if (cdc_fir_i_overrun || cdc_fir_q_overrun) cdc_cic_fir_overrun_sticky <= 1'b1;
end
assign cdc_cic_fir_overrun = cdc_cic_fir_overrun_sticky;
.rd_clk(clk_100m),
.rd_reset_n(reset_n),
.rd_data(fir_d_in_q),
.rd_valid(fir_in_valid_q),
.rd_ack(fir_in_valid_q)
);
// ============================================================================
// FIR Filter Instances
// ============================================================================
// FIR I channel
fir_lowpass_parallel_enhanced fir_i_inst (
.clk(clk_100m),
.reset_n(reset_n),
.data_in(fir_d_in_i), // Use synchronized data
.data_valid(fir_in_valid_i), // Use synchronized valid
.data_out(fir_i_out),
.data_out_valid(fir_valid_i),
.fir_ready(fir_i_ready),
.filter_overflow()
);
// FIR Q channel
fir_lowpass_parallel_enhanced fir_q_inst (
.clk(clk_100m),
.reset_n(reset_n),
.data_in(fir_d_in_q), // Use synchronized data
.data_valid(fir_in_valid_q), // Use synchronized valid
.data_out(fir_q_out),
.data_out_valid(fir_valid_q),
.fir_ready(fir_q_ready),
.filter_overflow()
);
assign fir_valid = fir_valid_i & fir_valid_q;
// ============================================================================
// Enhanced Output Stage
// ============================================================================
always @(posedge clk_100m or negedge reset_n) begin
if (!reset_n) begin
baseband_i_reg <= 0;
baseband_q_reg <= 0;
baseband_valid_reg <= 0;
end else if (fir_valid) begin
baseband_i_reg <= fir_i_out;
baseband_q_reg <= fir_q_out;
baseband_valid_reg <= 1;
end else begin
baseband_valid_reg <= 0;
end
end
// ============================================================================
// Output Assignments
// ============================================================================
assign baseband_i = baseband_i_reg;
assign baseband_q = baseband_q_reg;
// FIR overflow flags (audit F-6.2 — previously dangling, now OR'd into
// module-level filter_overflow so the receiver can see FIR arithmetic overflow)
wire fir_i_overflow;
wire fir_q_overflow;
// FIR I channel
fir_lowpass_parallel_enhanced fir_i_inst (
.clk(clk_100m),
.reset_n(reset_n),
.data_in(fir_d_in_i), // Use synchronized data
.data_valid(fir_in_valid_i), // Use synchronized valid
.data_out(fir_i_out),
.data_out_valid(fir_valid_i),
.fir_ready(fir_i_ready),
.filter_overflow(fir_i_overflow)
);
// FIR Q channel
fir_lowpass_parallel_enhanced fir_q_inst (
.clk(clk_100m),
.reset_n(reset_n),
.data_in(fir_d_in_q), // Use synchronized data
.data_valid(fir_in_valid_q), // Use synchronized valid
.data_out(fir_q_out),
.data_out_valid(fir_valid_q),
.fir_ready(fir_q_ready),
.filter_overflow(fir_q_overflow)
);
assign fir_valid = fir_valid_i & fir_valid_q;
assign filter_overflow = fir_i_overflow | fir_q_overflow;
// ============================================================================
// Enhanced Output Stage
// ============================================================================
always @(posedge clk_100m or negedge reset_n) begin
if (!reset_n) begin
baseband_i_reg <= 0;
baseband_q_reg <= 0;
baseband_valid_reg <= 0;
end else if (fir_valid) begin
baseband_i_reg <= fir_i_out;
baseband_q_reg <= fir_q_out;
baseband_valid_reg <= 1;
end else begin
baseband_valid_reg <= 0;
end
end
// ============================================================================
// Output Assignments
// ============================================================================
assign baseband_i = baseband_i_reg;
assign baseband_q = baseband_q_reg;
assign baseband_valid_i = baseband_valid_reg;
assign baseband_valid_q = baseband_valid_reg;
assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
assign mixer_saturation = overflow_detected;
assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
// ============================================================================
// Enhanced Debug and Monitoring
// ============================================================================
assign baseband_valid_q = baseband_valid_reg;
assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
assign mixer_saturation = overflow_detected;
assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
// ============================================================================
// Enhanced Debug and Monitoring
// ============================================================================
reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;
`ifdef SIMULATION
@@ -717,10 +731,10 @@ always @(posedge clk_100m) begin
baseband_i, baseband_q, debug_bb_count);
end
end
`endif
// In ddc_400m.v, add these debug signals:
`endif
// In ddc_400m.v, add these debug signals:
// Debug monitoring (simulation only)
`ifdef SIMULATION
reg [31:0] debug_adc_count = 0;
@@ -741,58 +755,67 @@ always @(posedge clk_100m) begin
baseband_i, baseband_q, debug_baseband_count, $time);
end
end
`endif
endmodule
// ============================================================================
// Enhanced Phase Dithering Module
// ============================================================================
`timescale 1ns / 1ps
module lfsr_dither_enhanced #(
parameter DITHER_WIDTH = 8 // Increased for better dithering
)(
input wire clk,
input wire reset_n,
input wire enable,
output wire [DITHER_WIDTH-1:0] dither_out
);
reg [DITHER_WIDTH-1:0] lfsr_reg;
reg [15:0] cycle_counter;
reg lock_detected;
// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
wire feedback;
generate
if (DITHER_WIDTH == 4) begin
assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
end else if (DITHER_WIDTH == 8) begin
assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
end else begin
assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
end
endgenerate
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
lfsr_reg <= {DITHER_WIDTH{1'b1}}; // Non-zero initial state
cycle_counter <= 0;
lock_detected <= 0;
end else if (enable) begin
lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
cycle_counter <= cycle_counter + 1;
// Detect LFSR lock after sufficient cycles
if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
lock_detected <= 1'b1;
end
end
end
assign dither_out = lfsr_reg;
endmodule
`endif
endmodule
// ============================================================================
// Enhanced Phase Dithering Module
// ============================================================================
`timescale 1ns / 1ps
module lfsr_dither_enhanced #(
parameter DITHER_WIDTH = 8 // Increased for better dithering
)(
input wire clk,
input wire reset_n,
input wire enable,
output wire [DITHER_WIDTH-1:0] dither_out
);
reg [DITHER_WIDTH-1:0] lfsr_reg;
reg [15:0] cycle_counter;
reg lock_detected;
// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
wire feedback;
generate
if (DITHER_WIDTH == 4) begin
assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
end else if (DITHER_WIDTH == 8) begin
assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
end else begin
assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
end
endgenerate
// ============================================================================
// RESET FAN-OUT INVARIANT: registered active-high reset with max_fanout=50.
// See cic_decimator_4x_enhanced.v for full reasoning. reset_n here is driven
// by the parent DDC's reset_n_400m (already synchronized to clk_400m), so
// sync reset on the LFSR is safe. INIT=1'b1 holds LFSR in reset on power-up.
// ============================================================================
(* max_fanout = 50 *) reg reset_h = 1'b1;
always @(posedge clk) reset_h <= ~reset_n;
always @(posedge clk) begin
if (reset_h) begin
lfsr_reg <= {DITHER_WIDTH{1'b1}}; // Non-zero initial state
cycle_counter <= 0;
lock_detected <= 0;
end else if (enable) begin
lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
cycle_counter <= cycle_counter + 1;
// Detect LFSR lock after sufficient cycles
if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
lock_detected <= 1'b1;
end
end
end
assign dither_out = lfsr_reg;
endmodule
9_Firmware/9_2_FPGA/doppler_processor.v
+1 -18
View File
@@ -531,23 +531,6 @@ xfft_16 fft_inst (
// Status Outputs
// ==============================================
assign processing_active = (state != S_IDLE);
// frame_complete must be a single-cycle pulse, not a level.
// The AGC (rx_gain_control) uses this as frame_boundary to snapshot
// per-frame metrics and update gain. If held high continuously,
// the AGC would re-evaluate every clock with zeroed accumulators,
// collapsing saturation_count/peak_magnitude to zero.
//
// Detect the falling edge of processing_active: the exact clock
// when the Doppler processor finishes all sub-frame FFTs and
// returns to S_IDLE with the frame buffer drained.
reg processing_active_prev;
always @(posedge clk or negedge reset_n) begin
if (!reset_n)
processing_active_prev <= 1'b0;
else
processing_active_prev <= processing_active;
end
assign frame_complete = (~processing_active & processing_active_prev);
assign frame_complete = (state == S_IDLE && frame_buffer_full == 0);
endmodule
9_Firmware/9_2_FPGA/matched_filter_multi_segment.v
+11 -78
View File
@@ -77,7 +77,6 @@ reg signed [15:0] buf_rdata_i, buf_rdata_q;
// State machine
reg [3:0] state;
localparam ST_IDLE = 0;
localparam ST_WAIT_LISTEN = 9; // Wait for TX chirp to end before collecting
localparam ST_COLLECT_DATA = 1;
localparam ST_ZERO_PAD = 2;
localparam ST_WAIT_REF = 3;
@@ -99,22 +98,11 @@ reg signed [15:0] overlap_cache_i [0:OVERLAP_SAMPLES-1];
reg signed [15:0] overlap_cache_q [0:OVERLAP_SAMPLES-1];
reg [7:0] overlap_copy_count;
// Listen-window delay counter: skip TX chirp duration before collecting echoes.
// The chirp_start_pulse fires at the beginning of TX, but the matched filter
// must collect receive-window samples (echoes), not TX leakage.
// For long chirp: skip LONG_CHIRP_SAMPLES (3000) ddc_valid counts
// For short chirp: skip SHORT_CHIRP_SAMPLES (50) ddc_valid counts
reg [15:0] listen_delay_count;
reg [15:0] listen_delay_target;
// Microcontroller sync detection
// mc_new_chirp/elevation/azimuth are TOGGLE signals from radar_mode_controller:
// they invert on every event. Detect ANY transition (XOR with previous value),
// not just rising edge, otherwise every other chirp/elevation/azimuth is missed.
reg mc_new_chirp_prev, mc_new_elevation_prev, mc_new_azimuth_prev;
wire chirp_start_pulse = mc_new_chirp ^ mc_new_chirp_prev;
wire elevation_change_pulse = mc_new_elevation ^ mc_new_elevation_prev;
wire azimuth_change_pulse = mc_new_azimuth ^ mc_new_azimuth_prev;
wire chirp_start_pulse = mc_new_chirp && !mc_new_chirp_prev;
wire elevation_change_pulse = mc_new_elevation && !mc_new_elevation_prev;
wire azimuth_change_pulse = mc_new_azimuth && !mc_new_azimuth_prev;
// Processing chain signals
wire [15:0] fft_pc_i, fft_pc_q;
@@ -196,8 +184,6 @@ always @(posedge clk or negedge reset_n) begin
buf_wdata_q <= 0;
buf_raddr <= 0;
overlap_copy_count <= 0;
listen_delay_count <= 0;
listen_delay_target <= 0;
end else begin
pc_valid <= 0;
mem_request <= 0;
@@ -219,45 +205,19 @@ always @(posedge clk or negedge reset_n) begin
// Wait for chirp start from microcontroller
if (chirp_start_pulse) begin
state <= ST_COLLECT_DATA;
total_segments <= use_long_chirp ? LONG_SEGMENTS[2:0] : SHORT_SEGMENTS[2:0];
// Delay collection until the listen window opens.
// chirp_start_pulse fires at TX start; echoes only arrive
// after the chirp finishes. Skip the TX duration by
// counting ddc_valid pulses before entering ST_COLLECT_DATA.
listen_delay_count <= 0;
listen_delay_target <= use_long_chirp ? LONG_CHIRP_SAMPLES[15:0]
: SHORT_CHIRP_SAMPLES[15:0];
state <= ST_WAIT_LISTEN;
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Chirp start detected, waiting for listen window (%0d samples)",
use_long_chirp ? LONG_CHIRP_SAMPLES : SHORT_CHIRP_SAMPLES);
$display("[MULTI_SEG_FIXED] Starting %s chirp, segments: %d",
use_long_chirp ? "LONG" : "SHORT",
use_long_chirp ? LONG_SEGMENTS : SHORT_SEGMENTS);
$display("[MULTI_SEG_FIXED] Overlap: %d samples, Advance: %d samples",
OVERLAP_SAMPLES, SEGMENT_ADVANCE);
`endif
end
end
ST_WAIT_LISTEN: begin
// Skip TX chirp duration — count ddc_valid pulses until the
// listen window opens. This ensures we only collect echo data,
// not TX leakage or dead time.
if (ddc_valid) begin
if (listen_delay_count >= listen_delay_target - 1) begin
// Listen window is now open — begin data collection
state <= ST_COLLECT_DATA;
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Listen window open after %0d TX samples, starting %s chirp collection",
listen_delay_count + 1,
use_long_chirp ? "LONG" : "SHORT");
$display("[MULTI_SEG_FIXED] Overlap: %d samples, Advance: %d samples",
OVERLAP_SAMPLES, SEGMENT_ADVANCE);
`endif
end else begin
listen_delay_count <= listen_delay_count + 1;
end
end
end
ST_COLLECT_DATA: begin
// Collect samples for current segment with overlap-save
if (ddc_valid && buffer_write_ptr < BUFFER_SIZE) begin
@@ -574,36 +534,9 @@ always @(posedge clk or negedge reset_n) begin
end
`endif
// ========== OUTPUT CONNECTIONS — OVERLAP-SAVE TRIM ==========
// In overlap-save processing, the first OVERLAP_SAMPLES (128) output bins
// of each segment after segment 0 are corrupted by circular convolution
// wrap-around. These must be discarded. Only the SEGMENT_ADVANCE (896)
// valid bins per segment are forwarded downstream.
//
// For segment 0: all 1024 output bins are valid (no prior overlap).
// For segments 1+: bins [0..127] are artifacts, bins [128..1023] are valid.
//
// We count fft_pc_valid pulses per segment and suppress output during
// the overlap region.
reg [10:0] output_bin_count;
wire output_in_overlap = (current_segment != 0) &&
(output_bin_count < OVERLAP_SAMPLES);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
output_bin_count <= 0;
end else begin
if (state == ST_PROCESSING && buffer_read_ptr == 0) begin
// Reset counter at start of each segment's processing
output_bin_count <= 0;
end else if (fft_pc_valid) begin
output_bin_count <= output_bin_count + 1;
end
end
end
// ========== OUTPUT CONNECTIONS ==========
assign pc_i_w = fft_pc_i;
assign pc_q_w = fft_pc_q;
assign pc_valid_w = fft_pc_valid & ~output_in_overlap;
assign pc_valid_w = fft_pc_valid;
endmodule
9_Firmware/9_2_FPGA/mti_canceller.v
+24 -7
View File
@@ -58,7 +58,12 @@ module mti_canceller #(
input wire mti_enable, // 1=MTI active, 0=pass-through
// ========== STATUS ==========
output reg mti_first_chirp // 1 during first chirp (output muted)
output reg mti_first_chirp, // 1 during first chirp (output muted)
// Audit F-6.3: count of saturated samples since last reset. Saturation
// here produces spurious Doppler harmonics (phantom targets at ±fs/2)
// and was previously invisible to the MCU. Saturates at 0xFF.
output reg [7:0] mti_saturation_count
);
// ============================================================================
@@ -104,18 +109,30 @@ assign diff_q_sat = (diff_q_full > $signed({{2{1'b0}}, {(DATA_WIDTH-1){1'b1}}}))
? $signed({1'b1, {(DATA_WIDTH-1){1'b0}}})
: diff_q_full[DATA_WIDTH-1:0];
// Saturation detection (F-6.3): the top two bits of the DATA_WIDTH+1 signed
// difference disagree iff the value exceeds the DATA_WIDTH signed range.
wire diff_i_overflow = (diff_i_full[DATA_WIDTH] != diff_i_full[DATA_WIDTH-1]);
wire diff_q_overflow = (diff_q_full[DATA_WIDTH] != diff_q_full[DATA_WIDTH-1]);
// ============================================================================
// MAIN LOGIC
// ============================================================================
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
range_i_out <= {DATA_WIDTH{1'b0}};
range_q_out <= {DATA_WIDTH{1'b0}};
range_valid_out <= 1'b0;
range_bin_out <= 6'd0;
has_previous <= 1'b0;
mti_first_chirp <= 1'b1;
range_i_out <= {DATA_WIDTH{1'b0}};
range_q_out <= {DATA_WIDTH{1'b0}};
range_valid_out <= 1'b0;
range_bin_out <= 6'd0;
has_previous <= 1'b0;
mti_first_chirp <= 1'b1;
mti_saturation_count <= 8'd0;
end else begin
// Count saturated MTI-active samples (F-6.3). Clamp at 0xFF.
if (range_valid_in && mti_enable && has_previous
&& (diff_i_overflow || diff_q_overflow)
&& (mti_saturation_count != 8'hFF)) begin
mti_saturation_count <= mti_saturation_count + 8'd1;
end
// Default: no valid output
range_valid_out <= 1'b0;
9_Firmware/9_2_FPGA/nco_400m_enhanced.v
+35 -16
View File
@@ -59,6 +59,25 @@ reg [1:0] quadrant_reg2; // Pass-through for Stage 5 MUX
// Valid pipeline: tracks 6-stage latency
reg [5:0] valid_pipe;
// ============================================================================
// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
// ============================================================================
// reset_h is an ACTIVE-HIGH, REGISTERED copy of ~reset_n with (* max_fanout=50 *).
// Vivado replicates this register (14+ copies) so each copy drives ≈50 loads
// regionally, avoiding the single-LUT1 / 702-load net that caused timing
// failure in Build N. It feeds:
// - DSP48E1 RSTP/RSTC on the phase-accumulator DSP (below)
// - All pipeline-stage fabric FDREs (synchronous reset)
// Invariants (see cic_decimator_4x_enhanced.v for full reasoning):
// I1 correctness: reset_h == ~reset_n one cycle later
// I2 glitch-free: registered output
// I3 power-up safe: INIT=1'b1 holds all downstream in reset until first
// valid clock edge; reset_n is low on power-up anyway
// I4 de-assert lat.: +1 cycle vs. direct async; negligible at 400 MHz
// ============================================================================
(* max_fanout = 50 *) reg reset_h = 1'b1;
always @(posedge clk_400m) reset_h <= ~reset_n;
// Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
wire [7:0] lut_address = phase_with_offset[31:24];
@@ -135,8 +154,8 @@ wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe_cos];
// Stage 2: phase_with_offset adds phase offset
reg [31:0] phase_accumulator;
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m) begin
if (reset_h) begin
phase_accumulator <= 32'h00000000;
phase_accum_reg <= 32'h00000000;
phase_with_offset <= 32'h00000000;
@@ -190,8 +209,8 @@ DSP48E1 #(
.RSTA(1'b0),
.RSTB(1'b0),
.RSTM(1'b0),
.RSTP(!reset_n), // Reset P register (phase accumulator) on !reset_n
.RSTC(!reset_n), // Reset C register (tuning word) on !reset_n
.RSTP(reset_h), // Reset P register (phase accumulator) — registered, max_fanout=50
.RSTC(reset_h), // Reset C register (tuning word) — registered, max_fanout=50
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTCTRL(1'b0),
@@ -245,8 +264,8 @@ DSP48E1 #(
// Stage 1: Capture DSP48E1 P output into fabric register
// Stage 2: Add phase offset to captured value
// Split into two registered stages to break DSP48E1.P→CARRY4 critical path
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m) begin
if (reset_h) begin
phase_accum_reg <= 32'h00000000;
phase_with_offset <= 32'h00000000;
end else if (phase_valid) begin
@@ -264,8 +283,8 @@ end
// Only 2 registers driven (lut_index_pipe + quadrant_pipe)
// Minimal fanout → short routes → easy timing
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m) begin
if (reset_h) begin
lut_index_pipe_sin <= 6'b000000;
lut_index_pipe_cos <= 6'b000000;
quadrant_pipe <= 2'b00;
@@ -281,8 +300,8 @@ end
// Registered address → combinational LUT6 read → register
// Only 1 logic level (LUT6), trivial timing
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m) begin
if (reset_h) begin
sin_abs_reg <= 16'h0000;
cos_abs_reg <= 16'h7FFF;
quadrant_reg <= 2'b00;
@@ -298,8 +317,8 @@ end
// CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
// Also pass through abs values and quadrant for Stage 5
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m) begin
if (reset_h) begin
sin_neg_reg <= 16'h0000;
cos_neg_reg <= -16'h7FFF;
sin_abs_reg2 <= 16'h0000;
@@ -318,8 +337,8 @@ end
// Stage 5: Quadrant sign application → final sin/cos output
// Uses pre-computed negated values from Stage 4 — pure MUX, no arithmetic
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m) begin
if (reset_h) begin
sin_out <= 16'h0000;
cos_out <= 16'h7FFF;
end else if (valid_pipe[4]) begin
@@ -347,8 +366,8 @@ end
// ============================================================================
// Valid pipeline and dds_ready (6-stage latency)
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m) begin
if (reset_h) begin
valid_pipe <= 6'b000000;
dds_ready <= 1'b0;
end else begin
9_Firmware/9_2_FPGA/radar_receiver_final.v
+93 -14
View File
@@ -9,6 +9,9 @@ module radar_receiver_final (
input wire [7:0] adc_d_n, // ADC Data N (LVDS)
input wire adc_dco_p, // Data Clock Output P (400MHz LVDS)
input wire adc_dco_n, // Data Clock Output N (400MHz LVDS)
// Audit F-0.1: AD9484 OR (overrange) LVDS pair
input wire adc_or_p,
input wire adc_or_n,
output wire adc_pwdn,
// Chirp counter from transmitter (for matched filter indexing)
@@ -74,7 +77,28 @@ module radar_receiver_final (
// AGC status outputs (for status readback / STM32 outer loop)
output wire [7:0] agc_saturation_count, // Per-frame clipped sample count
output wire [7:0] agc_peak_magnitude, // Per-frame peak (upper 8 bits)
output wire [3:0] agc_current_gain // Effective gain_shift encoding
output wire [3:0] agc_current_gain, // Effective gain_shift encoding
// DDC overflow diagnostics (audit F-6.1 — previously deleted at boundary).
// Not yet plumbed into the USB status packet (protocol contract is frozen);
// exposed here for gpio aggregation and ILA mark_debug visibility.
output wire ddc_overflow_any,
output wire [2:0] ddc_saturation_count,
// MTI 2-pulse canceller saturation count (audit F-6.3).
output wire [7:0] mti_saturation_count_out,
// Range-bin decimator watchdog (audit F-6.4 — previously tied off
// with an ILA-only note). A high pulse here means the decimator
// FSM has not seen the expected number of input samples within
// its timeout window, i.e. the upstream FIR/CDC has stalled.
output wire range_decim_watchdog,
// Audit F-1.2: sticky CIC→FIR CDC overrun flag. Asserts on the first
// silent sample drop between the 400 MHz CIC output and the 100 MHz
// FIR input; stays high until the next reset. OR'd into the GPIO
// diagnostic bit at the top level.
output wire ddc_cic_fir_overrun
);
// ========== INTERNAL SIGNALS ==========
@@ -185,18 +209,43 @@ wire adc_valid; // Data valid signal
// ADC power-down control (directly tie low = ADC always on)
assign adc_pwdn = 1'b0;
wire adc_overrange_400m;
ad9484_interface_400m adc (
.adc_d_p(adc_d_p),
.adc_d_n(adc_d_n),
.adc_dco_p(adc_dco_p),
.adc_dco_n(adc_dco_n),
.adc_or_p(adc_or_p),
.adc_or_n(adc_or_n),
.sys_clk(clk),
.reset_n(reset_n),
.adc_data_400m(adc_data_cmos),
.adc_data_valid_400m(adc_valid),
.adc_dco_bufg(clk_400m)
.adc_dco_bufg(clk_400m),
.adc_overrange_400m(adc_overrange_400m)
);
// Audit F-0.1: stickify the 400 MHz OR pulse, then CDC to clk_100m via 2FF.
// Same reasoning as ddc_cic_fir_overrun: single-bit, low→high-only once
// latched, so a 2FF sync is sufficient for a GPIO-class diagnostic. Cleared
// only by global reset_n.
reg adc_overrange_sticky_400m;
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n)
adc_overrange_sticky_400m <= 1'b0;
else if (adc_overrange_400m)
adc_overrange_sticky_400m <= 1'b1;
end
(* ASYNC_REG = "TRUE" *) reg [1:0] adc_overrange_sync_100m;
always @(posedge clk or negedge reset_n) begin
if (!reset_n)
adc_overrange_sync_100m <= 2'b00;
else
adc_overrange_sync_100m <= {adc_overrange_sync_100m[0], adc_overrange_sticky_400m};
end
wire adc_overrange_100m = adc_overrange_sync_100m[1];
// NOTE: The cdc_adc_to_processing instance that was here used src_clk=dst_clk=clk_400m
// (same clock domain — no crossing). Gray-code CDC on same-clock with fast-changing
// ADC data corrupts samples because Gray coding only guarantees safe transfer of
@@ -211,6 +260,16 @@ wire signed [17:0] ddc_out_q;
wire ddc_valid_i;
wire ddc_valid_q;
// DDC diagnostic signals (audit F-6.1 — all outputs previously unconnected)
wire [1:0] ddc_status_w;
wire [7:0] ddc_diagnostics_w;
wire ddc_mixer_saturation;
wire ddc_filter_overflow;
(* mark_debug = "true" *) wire ddc_mixer_saturation_dbg = ddc_mixer_saturation;
(* mark_debug = "true" *) wire ddc_filter_overflow_dbg = ddc_filter_overflow;
(* mark_debug = "true" *) wire [7:0] ddc_diagnostics_dbg = ddc_diagnostics_w;
ddc_400m_enhanced ddc(
.clk_400m(clk_400m), // 400MHz clock from ADC DCO
.clk_100m(clk), // 100MHz system clock //used by the 2 FIR
@@ -219,12 +278,31 @@ ddc_400m_enhanced ddc(
.adc_data_valid_i(adc_valid), // Valid at 400MHz
.adc_data_valid_q(adc_valid), // Valid at 400MHz
.baseband_i(ddc_out_i), // I output at 100MHz
.baseband_q(ddc_out_q), // Q output at 100MHz
.baseband_q(ddc_out_q), // Q output at 100MHz
.baseband_valid_i(ddc_valid_i), // Valid at 100MHz
.baseband_valid_q(ddc_valid_q),
.mixers_enable(1'b1)
.baseband_valid_q(ddc_valid_q),
.mixers_enable(1'b1),
// Diagnostics (audit F-6.1) — previously all unconnected
.ddc_status(ddc_status_w),
.ddc_diagnostics(ddc_diagnostics_w),
.mixer_saturation(ddc_mixer_saturation),
.filter_overflow(ddc_filter_overflow),
// Test/debug inputs — explicit tie-low (were floating)
.test_mode(2'b00),
.test_phase_inc(16'h0000),
.force_saturation(1'b0),
.reset_monitors(1'b0),
.debug_sample_count(),
.debug_internal_i(),
.debug_internal_q(),
.cdc_cic_fir_overrun(ddc_cic_fir_overrun)
);
// Audit F-0.1: AD9484 overrange aggregated here so a single gpio_dig bit
// covers DDC-internal saturation, FIR overflow, AND raw ADC clipping.
assign ddc_overflow_any = ddc_mixer_saturation | ddc_filter_overflow | adc_overrange_100m;
assign ddc_saturation_count = ddc_diagnostics_w[7:5];
ddc_input_interface ddc_if (
.clk(clk),
.reset_n(reset_n),
@@ -369,7 +447,7 @@ range_bin_decimator #(
.range_bin_index(decimated_range_bin),
.decimation_mode(2'b01), // Peak detection mode
.start_bin(10'd0),
.watchdog_timeout() // Diagnostic — unconnected (monitored via ILA if needed)
.watchdog_timeout(range_decim_watchdog) // Audit F-6.4 — plumbed out
);
// ========== MTI CANCELLER (Ground Clutter Removal) ==========
@@ -391,7 +469,8 @@ mti_canceller #(
.range_valid_out(mti_range_valid),
.range_bin_out(mti_range_bin),
.mti_enable(host_mti_enable),
.mti_first_chirp(mti_first_chirp)
.mti_first_chirp(mti_first_chirp),
.mti_saturation_count(mti_saturation_count_out)
);
// ========== FRAME SYNC FROM TRANSMITTER ==========
@@ -430,12 +509,12 @@ assign range_data_32bit = {mti_range_q, mti_range_i};
assign range_data_valid = mti_range_valid;
// ========== DOPPLER PROCESSOR ==========
doppler_processor_optimized #(
.DOPPLER_FFT_SIZE(16),
.RANGE_BINS(64),
.CHIRPS_PER_FRAME(32),
.CHIRPS_PER_SUBFRAME(16)
) doppler_proc (
doppler_processor_optimized #(
.DOPPLER_FFT_SIZE(16),
.RANGE_BINS(64),
.CHIRPS_PER_FRAME(32),
.CHIRPS_PER_SUBFRAME(16)
) doppler_proc (
.clk(clk),
.reset_n(reset_n),
.range_data(range_data_32bit),
@@ -498,4 +577,4 @@ assign agc_saturation_count = gc_saturation_count;
assign agc_peak_magnitude = gc_peak_magnitude;
assign agc_current_gain = gc_current_gain;
endmodule
endmodule
9_Firmware/9_2_FPGA/radar_system_top.v
+90 -41
View File
@@ -67,6 +67,9 @@ module radar_system_top (
input wire [7:0] adc_d_n, // ADC Data N (LVDS)
input wire adc_dco_p, // Data Clock Output P (400MHz LVDS)
input wire adc_dco_n, // Data Clock Output N (400MHz LVDS)
// Audit F-0.1: AD9484 OR (overrange) LVDS pair
input wire adc_or_p,
input wire adc_or_n,
output wire adc_pwdn, // ADC Power Down
// ========== STM32 CONTROL INTERFACES ==========
@@ -130,7 +133,7 @@ module radar_system_top (
// FPGA→STM32 GPIO outputs (DIG_5..DIG_7 on 50T board)
// Used by STM32 outer AGC loop to read saturation state without USB polling.
output wire gpio_dig5, // DIG_5 (H11→PD13): AGC saturation flag (1=clipping detected)
output wire gpio_dig6, // DIG_6 (G12→PD14): reserved (tied low)
output wire gpio_dig6, // DIG_6 (G12→PD14): AGC enable flag (mirrors host_agc_enable)
output wire gpio_dig7 // DIG_7 (H12→PD15): reserved (tied low)
);
@@ -142,7 +145,7 @@ module radar_system_top (
parameter USE_LONG_CHIRP = 1'b1; // Default to long chirp
parameter DOPPLER_ENABLE = 1'b1; // Enable Doppler processing
parameter USB_ENABLE = 1'b1; // Enable USB data transfer
parameter USB_MODE = 0; // 0=FT601 (32-bit, 200T), 1=FT2232H (8-bit, 50T)
parameter USB_MODE = 1; // 0=FT601 (32-bit, 200T), 1=FT2232H (8-bit, 50T production default)
// ============================================================================
// INTERNAL SIGNALS
@@ -198,6 +201,19 @@ wire [7:0] rx_agc_saturation_count;
wire [7:0] rx_agc_peak_magnitude;
wire [3:0] rx_agc_current_gain;
// DDC overflow diagnostics (audit F-6.1) — plumbed out of receiver so the
// DDC mixer_saturation / filter_overflow ports are no longer deleted at
// the boundary. Aggregated into gpio_dig5 alongside AGC saturation.
wire rx_ddc_overflow_any;
wire [2:0] rx_ddc_saturation_count;
// MTI saturation count (audit F-6.3). OR'd into gpio_dig5 for MCU visibility.
wire [7:0] rx_mti_saturation_count;
// Range-bin decimator watchdog (audit F-6.4). High = decimator stalled.
wire rx_range_decim_watchdog;
// CIC→FIR CDC overrun sticky (audit F-1.2). High = at least one baseband
// sample has been silently dropped between the 400 MHz CIC and 100 MHz FIR.
wire rx_ddc_cic_fir_overrun;
// Data packing for USB
wire [31:0] usb_range_profile;
wire usb_range_valid;
@@ -243,12 +259,12 @@ reg [5:0] host_chirps_per_elev; // Opcode 0x15 (default 32)
reg host_status_request; // Opcode 0xFF (self-clearing pulse)
// Fix 4: Doppler/chirps mismatch protection
// DOPPLER_FRAME_CHIRPS is the fixed chirp count expected by the staggered-PRI
// Doppler path (16 long + 16 short). If host sets chirps_per_elev to a
// different value, Doppler accumulation is corrupted. Clamp at command decode
// and flag the mismatch so the host knows.
localparam DOPPLER_FRAME_CHIRPS = 32; // Total chirps per Doppler frame
reg chirps_mismatch_error; // Set if host tried to set chirps != FFT size
// DOPPLER_FRAME_CHIRPS is the fixed chirp count expected by the staggered-PRI
// Doppler path (16 long + 16 short). If host sets chirps_per_elev to a
// different value, Doppler accumulation is corrupted. Clamp at command decode
// and flag the mismatch so the host knows.
localparam DOPPLER_FRAME_CHIRPS = 32; // Total chirps per Doppler frame
reg chirps_mismatch_error; // Set if host tried to set chirps != FFT size
// Fix 7: Range-mode register (opcode 0x20)
// Future-proofing for 3km/10km antenna switching.
@@ -513,6 +529,8 @@ radar_receiver_final rx_inst (
.adc_d_n(adc_d_n),
.adc_dco_p(adc_dco_p),
.adc_dco_n(adc_dco_n),
.adc_or_p(adc_or_p),
.adc_or_n(adc_or_n),
.adc_pwdn(adc_pwdn),
// Doppler Outputs
@@ -562,7 +580,15 @@ radar_receiver_final rx_inst (
// AGC status outputs
.agc_saturation_count(rx_agc_saturation_count),
.agc_peak_magnitude(rx_agc_peak_magnitude),
.agc_current_gain(rx_agc_current_gain)
.agc_current_gain(rx_agc_current_gain),
// DDC overflow diagnostics (audit F-6.1)
.ddc_overflow_any(rx_ddc_overflow_any),
.ddc_saturation_count(rx_ddc_saturation_count),
// MTI saturation count (audit F-6.3)
.mti_saturation_count_out(rx_mti_saturation_count),
// Range-bin decimator watchdog (audit F-6.4)
.range_decim_watchdog(rx_range_decim_watchdog),
.ddc_cic_fir_overrun(rx_ddc_cic_fir_overrun)
);
// ============================================================================
@@ -578,21 +604,21 @@ assign rx_doppler_data_valid = rx_doppler_valid;
// ============================================================================
// DC NOTCH FILTER (post-Doppler-FFT, pre-CFAR)
// ============================================================================
// Zeros out Doppler bins within ±host_dc_notch_width of DC for BOTH
// sub-frames in the dual 16-pt FFT architecture.
// doppler_bin[4:0] = {sub_frame, bin[3:0]}:
// Sub-frame 0: bins 0-15, DC = bin 0, wrap = bin 15
// Sub-frame 1: bins 16-31, DC = bin 16, wrap = bin 31
// notch_width=1 → zero bins {0,16}. notch_width=2 → zero bins
// {0,1,15,16,17,31}. etc.
// When host_dc_notch_width=0: pass-through (no zeroing).
wire dc_notch_active;
wire [4:0] dop_bin_unsigned = rx_doppler_bin;
wire [3:0] bin_within_sf = dop_bin_unsigned[3:0];
assign dc_notch_active = (host_dc_notch_width != 3'd0) &&
(bin_within_sf < {1'b0, host_dc_notch_width} ||
bin_within_sf > (4'd15 - {1'b0, host_dc_notch_width} + 4'd1));
// Zeros out Doppler bins within ±host_dc_notch_width of DC for BOTH
// sub-frames in the dual 16-pt FFT architecture.
// doppler_bin[4:0] = {sub_frame, bin[3:0]}:
// Sub-frame 0: bins 0-15, DC = bin 0, wrap = bin 15
// Sub-frame 1: bins 16-31, DC = bin 16, wrap = bin 31
// notch_width=1 → zero bins {0,16}. notch_width=2 → zero bins
// {0,1,15,16,17,31}. etc.
// When host_dc_notch_width=0: pass-through (no zeroing).
wire dc_notch_active;
wire [4:0] dop_bin_unsigned = rx_doppler_bin;
wire [3:0] bin_within_sf = dop_bin_unsigned[3:0];
assign dc_notch_active = (host_dc_notch_width != 3'd0) &&
(bin_within_sf < {1'b0, host_dc_notch_width} ||
bin_within_sf > (4'd15 - {1'b0, host_dc_notch_width} + 4'd1));
// Notched Doppler data: zero I/Q when in notch zone, pass through otherwise
wire [31:0] notched_doppler_data = dc_notch_active ? 32'd0 : rx_doppler_output;
@@ -871,6 +897,19 @@ endgenerate
// we simply sample them in clk_100m when the CDC'd pulse arrives.
// Step 1: Toggle on cmd_valid pulse (ft601_clk domain)
//
// CDC INVARIANT (audit F-1.1): usb_cmd_opcode / usb_cmd_addr / usb_cmd_value
// / usb_cmd_data MUST be driven to their final values BEFORE usb_cmd_valid
// asserts, and held stable for at least (STAGES + 1) clk_100m cycles after
// (i.e., until cmd_valid_100m has pulsed in the destination domain). These
// buses cross from ft601_clk to clk_100m as quasi-static data, NOT through
// a synchronizer — only the toggle bit above is CDC'd. If a future edit
// moves the cmd_* register write to the SAME cycle as the toggle flip, or
// drops the stability hold, the clk_100m sampler at the command decoder
// will latch metastable bits and dispatch on a garbage opcode.
// The source-side FSM in usb_data_interface_ft2232h.v / usb_data_interface.v
// currently satisfies this by assigning the cmd_* buses several cycles
// before pulsing cmd_valid and leaving them stable until the next command.
reg cmd_valid_toggle_ft601;
always @(posedge ft601_clk_buf or negedge sys_reset_ft601_n) begin
if (!sys_reset_ft601_n)
@@ -959,19 +998,19 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
8'h13: host_short_chirp_cycles <= usb_cmd_value;
8'h14: host_short_listen_cycles <= usb_cmd_value;
8'h15: begin
// Fix 4: Clamp chirps_per_elev to the fixed Doppler frame size.
// If host requests a different value, clamp and set error flag.
if (usb_cmd_value[5:0] > DOPPLER_FRAME_CHIRPS[5:0]) begin
host_chirps_per_elev <= DOPPLER_FRAME_CHIRPS[5:0];
chirps_mismatch_error <= 1'b1;
end else if (usb_cmd_value[5:0] == 6'd0) begin
host_chirps_per_elev <= DOPPLER_FRAME_CHIRPS[5:0];
chirps_mismatch_error <= 1'b1;
end else begin
host_chirps_per_elev <= usb_cmd_value[5:0];
// Clear error only if value matches FFT size exactly
chirps_mismatch_error <= (usb_cmd_value[5:0] != DOPPLER_FRAME_CHIRPS[5:0]);
end
// Fix 4: Clamp chirps_per_elev to the fixed Doppler frame size.
// If host requests a different value, clamp and set error flag.
if (usb_cmd_value[5:0] > DOPPLER_FRAME_CHIRPS[5:0]) begin
host_chirps_per_elev <= DOPPLER_FRAME_CHIRPS[5:0];
chirps_mismatch_error <= 1'b1;
end else if (usb_cmd_value[5:0] == 6'd0) begin
host_chirps_per_elev <= DOPPLER_FRAME_CHIRPS[5:0];
chirps_mismatch_error <= 1'b1;
end else begin
host_chirps_per_elev <= usb_cmd_value[5:0];
// Clear error only if value matches FFT size exactly
chirps_mismatch_error <= (usb_cmd_value[5:0] != DOPPLER_FRAME_CHIRPS[5:0]);
end
end
8'h16: host_gain_shift <= usb_cmd_value[3:0]; // Fix 3: digital gain
8'h20: host_range_mode <= usb_cmd_value[1:0]; // Fix 7: range mode
@@ -1037,9 +1076,19 @@ assign system_status = status_reg;
// ============================================================================
// DIG_5: AGC saturation flag — high when per-frame saturation_count > 0.
// STM32 reads PD13 to detect clipping and adjust ADAR1000 VGA gain.
// DIG_6, DIG_7: Reserved (tied low for future use).
assign gpio_dig5 = (rx_agc_saturation_count != 8'd0);
assign gpio_dig6 = 1'b0;
// DIG_6: AGC enable flag — mirrors host_agc_enable so STM32 outer-loop AGC
// tracks the FPGA register as single source of truth.
// DIG_7: Reserved (tied low for future use).
// gpio_dig5: "signal-chain clipped" — asserts on AGC saturation, DDC mixer/FIR
// overflow, or MTI 2-pulse saturation. Audit F-6.1/F-6.3: these were all
// previously invisible to the MCU.
assign gpio_dig5 = (rx_agc_saturation_count != 8'd0)
| rx_ddc_overflow_any
| (rx_ddc_saturation_count != 3'd0)
| (rx_mti_saturation_count != 8'd0)
| rx_range_decim_watchdog // audit F-6.4
| rx_ddc_cic_fir_overrun; // audit F-1.2
assign gpio_dig6 = host_agc_enable;
assign gpio_dig7 = 1'b0;
// ============================================================================
@@ -1073,4 +1122,4 @@ always @(posedge clk_100m_buf) begin
end
`endif
endmodule
endmodule
9_Firmware/9_2_FPGA/radar_system_top_50t.v
+4
View File
@@ -60,6 +60,8 @@ module radar_system_top_50t (
input wire [7:0] adc_d_n,
input wire adc_dco_p,
input wire adc_dco_n,
input wire adc_or_p,
input wire adc_or_n,
output wire adc_pwdn,
// ===== STM32 Control (Bank 15: 3.3V) =====
@@ -171,6 +173,8 @@ module radar_system_top_50t (
.adc_d_n (adc_d_n),
.adc_dco_p (adc_dco_p),
.adc_dco_n (adc_dco_n),
.adc_or_p (adc_or_p),
.adc_or_n (adc_or_n),
.adc_pwdn (adc_pwdn),
// ----- STM32 Control -----
9_Firmware/9_2_FPGA/radar_system_top_te0713_umft601x_dev.v
+6 -1
View File
@@ -138,7 +138,12 @@ usb_data_interface usb_inst (
.status_range_mode(2'b01),
.status_self_test_flags(5'b11111),
.status_self_test_detail(8'hA5),
.status_self_test_busy(1'b0)
.status_self_test_busy(1'b0),
// AGC status: tie off with benign defaults (no AGC on dev board)
.status_agc_current_gain(4'd0),
.status_agc_peak_magnitude(8'd0),
.status_agc_saturation_count(8'd0),
.status_agc_enable(1'b0)
);
endmodule
9_Firmware/9_2_FPGA/run_regression.sh
+47 -76
View File
@@ -70,6 +70,7 @@ PROD_RTL=(
xfft_16.v
fft_engine.v
usb_data_interface.v
usb_data_interface_ft2232h.v
edge_detector.v
radar_mode_controller.v
rx_gain_control.v
@@ -86,6 +87,33 @@ EXTRA_RTL=(
frequency_matched_filter.v
)
# ---------------------------------------------------------------------------
# Shared RTL file lists for integration / system tests
# Centralised here so a new module only needs adding once.
# ---------------------------------------------------------------------------
# Receiver chain (used by golden generate/compare tests)
RECEIVER_RTL=(
radar_receiver_final.v
radar_mode_controller.v
tb/ad9484_interface_400m_stub.v
ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v
cdc_modules.v fir_lowpass.v ddc_input_interface.v
chirp_memory_loader_param.v latency_buffer.v
matched_filter_multi_segment.v matched_filter_processing_chain.v
range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v
rx_gain_control.v mti_canceller.v
)
# Full system top (receiver chain + TX + USB + detection + self-test)
SYSTEM_RTL=(
radar_system_top.v
radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v
"${RECEIVER_RTL[@]}"
usb_data_interface.v usb_data_interface_ft2232h.v edge_detector.v
cfar_ca.v fpga_self_test.v
)
# ---- Layer A: iverilog -Wall compilation ----
run_lint_iverilog() {
local label="$1"
@@ -219,26 +247,9 @@ run_lint_static() {
fi
done
# --- Single-line regex checks across all production RTL ---
for f in "$@"; do
[[ -f "$f" ]] || continue
case "$f" in tb/*) continue ;; esac
local linenum=0
while IFS= read -r line; do
linenum=$((linenum + 1))
# CHECK 5: $readmemh / $readmemb in synthesizable code
# (Only valid in simulation blocks — flag if outside `ifdef SIMULATION)
# This is hard to check line-by-line without tracking ifdefs.
# Skip for v1.
# CHECK 6: Unused `include files (informational only)
# Skip for v1.
: # placeholder — prevents empty loop body
done < "$f"
done
# CHECK 5 ($readmemh in synth code) and CHECK 6 (unused includes)
# require multi-line ifdef tracking / cross-file analysis. Not feasible
# with line-by-line regex. Omitted — use Vivado lint instead.
if [[ "$err_count" -gt 0 ]]; then
echo -e "${RED}FAIL${NC} ($err_count errors, $warn_count warnings)"
@@ -420,57 +431,36 @@ if [[ "$QUICK" -eq 0 ]]; then
run_test "Receiver (golden generate)" \
tb/tb_rx_golden_reg.vvp \
-DGOLDEN_GENERATE \
tb/tb_radar_receiver_final.v radar_receiver_final.v \
radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
cdc_modules.v fir_lowpass.v ddc_input_interface.v \
chirp_memory_loader_param.v latency_buffer.v \
matched_filter_multi_segment.v matched_filter_processing_chain.v \
range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
rx_gain_control.v mti_canceller.v
tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
# Golden compare
run_test "Receiver (golden compare)" \
tb/tb_rx_compare_reg.vvp \
tb/tb_radar_receiver_final.v radar_receiver_final.v \
radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
cdc_modules.v fir_lowpass.v ddc_input_interface.v \
chirp_memory_loader_param.v latency_buffer.v \
matched_filter_multi_segment.v matched_filter_processing_chain.v \
range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
rx_gain_control.v mti_canceller.v
tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
# Full system top (monitoring-only, legacy)
run_test "System Top (radar_system_tb)" \
tb/tb_system_reg.vvp \
tb/radar_system_tb.v radar_system_top.v \
radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v \
radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
cdc_modules.v fir_lowpass.v ddc_input_interface.v \
chirp_memory_loader_param.v latency_buffer.v \
matched_filter_multi_segment.v matched_filter_processing_chain.v \
range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
usb_data_interface.v edge_detector.v radar_mode_controller.v \
rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
# E2E integration (46 strict checks: TX, RX, USB R/W, CDC, safety, reset)
run_test "System E2E (tb_system_e2e)" \
tb/tb_system_e2e_reg.vvp \
tb/tb_system_e2e.v radar_system_top.v \
radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v \
radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
cdc_modules.v fir_lowpass.v ddc_input_interface.v \
chirp_memory_loader_param.v latency_buffer.v \
matched_filter_multi_segment.v matched_filter_processing_chain.v \
range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
usb_data_interface.v edge_detector.v radar_mode_controller.v \
rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
# USB_MODE=1 (FT2232H production) variants of system tests
run_test "System Top USB_MODE=1 (FT2232H)" \
tb/tb_system_ft2232h_reg.vvp \
-DUSB_MODE_1 \
tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
run_test "System E2E USB_MODE=1 (FT2232H)" \
tb/tb_system_e2e_ft2232h_reg.vvp \
-DUSB_MODE_1 \
tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
else
echo " (skipped receiver golden + system top + E2E — use without --quick)"
SKIP=$((SKIP + 4))
SKIP=$((SKIP + 6))
fi
echo ""
@@ -526,25 +516,6 @@ run_test "Radar Mode Controller" \
echo ""
# ===========================================================================
# PHASE 5: P0 ADVERSARIAL TESTS — Invariant Violation Fixes
# ===========================================================================
echo "--- PHASE 5: P0 Adversarial Tests ---"
run_test "P0 Fix #1: Async FIFO CDC (show-ahead, overflow, reset)" \
tb/tb_p0_async_fifo.vvp \
tb/tb_p0_async_fifo.v cdc_modules.v
run_test "P0 Fixes #2/#3/#4: Matched Filter (toggle, listen, overlap)" \
tb/tb_p0_mf_adversarial.vvp \
tb/tb_p0_mf_adversarial.v matched_filter_multi_segment.v
run_test "P0 Fix #7: Frame Complete Pulse (falling-edge)" \
tb/tb_p0_frame_pulse.vvp \
tb/tb_p0_frame_pulse.v
echo ""
# ===========================================================================
# SUMMARY
# ===========================================================================
9_Firmware/9_2_FPGA/scripts/200t/build_200t.tcl
+3
View File
@@ -108,6 +108,9 @@ add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "
set_property top $top_module [current_fileset]
set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
# Override USB_MODE to 0 (FT601) for 200T premium board.
# The RTL default is USB_MODE=1 (FT2232H, production 50T).
set_property generic {USB_MODE=0} [current_fileset]
# ==============================================================================
# 2. Synthesis
9_Firmware/9_2_FPGA/tb/ad9484_interface_400m_stub.v
+17 -1
View File
@@ -19,6 +19,10 @@ module ad9484_interface_400m (
input wire [7:0] adc_d_n,
input wire adc_dco_p,
input wire adc_dco_n,
// Audit F-0.1: AD9484 OR (overrange) LVDS pair — stub treats adc_or_p as
// the single-ended overrange flag, adc_or_n is ignored.
input wire adc_or_p,
input wire adc_or_n,
// System Interface
input wire sys_clk,
@@ -27,7 +31,8 @@ module ad9484_interface_400m (
// Output at 400MHz domain
output wire [7:0] adc_data_400m,
output wire adc_data_valid_400m,
output wire adc_dco_bufg
output wire adc_dco_bufg,
output wire adc_overrange_400m
);
// Pass-through clock (no BUFG needed in simulation)
@@ -50,4 +55,15 @@ end
assign adc_data_400m = adc_data_400m_reg;
assign adc_data_valid_400m = adc_data_valid_400m_reg;
// Audit F-0.1: 1-cycle pipeline of adc_or_p to match the real IDDR+register
// capture path. TB drives adc_or_p directly with the overrange flag.
reg adc_overrange_400m_reg;
always @(posedge adc_dco_p or negedge reset_n) begin
if (!reset_n)
adc_overrange_400m_reg <= 1'b0;
else
adc_overrange_400m_reg <= adc_or_p;
end
assign adc_overrange_400m = adc_overrange_400m_reg;
endmodule
9_Firmware/9_2_FPGA/tb/cosim/rtl_bb_dc.csv
+2455 -2455
View File
File diff suppressed because it is too large Load Diff
9_Firmware/9_2_FPGA/tb/cosim/rx_final_doppler_out.csv
+2048 -2048
View File
File diff suppressed because it is too large Load Diff
9_Firmware/9_2_FPGA/tb/golden/golden_doppler.mem
+2084 -2084
View File
File diff suppressed because it is too large Load Diff
9_Firmware/9_2_FPGA/tb/radar_system_tb.v
+13 -1
View File
@@ -430,7 +430,13 @@ end
// DUT INSTANTIATION
// ============================================================================
radar_system_top dut (
radar_system_top #(
`ifdef USB_MODE_1
.USB_MODE(1) // FT2232H interface (production 50T board)
`else
.USB_MODE(0) // FT601 interface (200T dev board)
`endif
) dut (
// System Clocks
.clk_100m(clk_100m),
.clk_120m_dac(clk_120m_dac),
@@ -481,6 +487,8 @@ radar_system_top dut (
.adc_d_n(adc_d_n),
.adc_dco_p(adc_dco_p),
.adc_dco_n(adc_dco_n),
.adc_or_p(1'b0),
.adc_or_n(1'b1),
.adc_pwdn(adc_pwdn),
// STM32 Control
@@ -619,7 +627,11 @@ initial begin
// Optional: dump specific signals for debugging
$dumpvars(1, dut.tx_inst);
$dumpvars(1, dut.rx_inst);
`ifdef USB_MODE_1
$dumpvars(1, dut.gen_ft2232h.usb_inst);
`else
$dumpvars(1, dut.gen_ft601.usb_inst);
`endif
end
endmodule
9_Firmware/9_2_FPGA/tb/tb_ddc_cosim.v
+15 -4
View File
@@ -64,9 +64,11 @@ module tb_ddc_cosim;
// Scenario selector (set via +define)
reg [255:0] scenario_name;
reg [1023:0] hex_file_path;
reg [1023:0] csv_out_path;
reg [1023:0] csv_cic_path;
// Widened to 4 kbits (512 bytes) so fuzz-runner temp paths
// (e.g. /private/var/folders/.../pytest-of-...) fit without MSB truncation.
reg [4095:0] hex_file_path;
reg [4095:0] csv_out_path;
reg [4095:0] csv_cic_path;
// ── Clock generation ──────────────────────────────────────
// 400 MHz clock
@@ -152,7 +154,16 @@ module tb_ddc_cosim;
// ── Select scenario ───────────────────────────────────
// Default to DC scenario for fastest validation
// Override with: +define+SCENARIO_SINGLE, +define+SCENARIO_MULTI, etc.
`ifdef SCENARIO_SINGLE
`ifdef SCENARIO_FUZZ
// Audit F-3.2: fuzz runner provides +hex and +csv paths plus a
// scenario tag. Any missing plusarg falls back to the DC vector.
if (!$value$plusargs("hex=%s", hex_file_path))
hex_file_path = "tb/cosim/adc_dc.hex";
if (!$value$plusargs("csv=%s", csv_out_path))
csv_out_path = "tb/cosim/rtl_bb_fuzz.csv";
if (!$value$plusargs("tag=%s", scenario_name))
scenario_name = "fuzz";
`elsif SCENARIO_SINGLE
hex_file_path = "tb/cosim/adc_single_target.hex";
csv_out_path = "tb/cosim/rtl_bb_single_target.csv";
scenario_name = "single_target";
9_Firmware/9_2_FPGA/tb/tb_p0_async_fifo.v
-558
View File
@@ -1,558 +0,0 @@
`timescale 1ns / 1ps
// ============================================================================
// ADVERSARIAL TESTBENCH: cdc_async_fifo (P0 Fix #1)
// ============================================================================
// Actively tries to BREAK the async FIFO that replaced the flawed
// Gray-encoded CDC for the DDC 400→100 MHz sample path.
//
// Attack vectors:
// 1. Read on empty FIFO — no spurious rd_valid
// 2. Single write/read — basic data integrity
// 3. Fill to capacity — wr_full asserts correctly
// 4. Overflow — write-when-full must be rejected, no corruption
// 5. Ordered streaming — FIFO order preserved under sustained load
// 6. Reset mid-transfer — clean recovery, no stale data
// 7. Burst writes at max wr_clk rate — stress back-pressure
// 8. wr_full deasserts promptly after read
// 9. Alternating single-entry traffic — throughput = 1
// 10. Pathological data patterns — all-ones, alternating bits
// ============================================================================
module tb_p0_async_fifo;
localparam WR_PERIOD = 2.5; // 400 MHz source clock
localparam RD_PERIOD = 10.0; // 100 MHz destination clock
localparam WIDTH = 18;
localparam DEPTH = 8;
// ── Test bookkeeping ─────────────────────────────────────
integer pass_count = 0;
integer fail_count = 0;
integer test_num = 0;
integer i, j;
task check;
input cond;
input [511:0] label;
begin
test_num = test_num + 1;
if (cond) begin
$display("[PASS] Test %0d: %0s", test_num, label);
pass_count = pass_count + 1;
end else begin
$display("[FAIL] Test %0d: %0s", test_num, label);
fail_count = fail_count + 1;
end
end
endtask
// ── DUT signals ──────────────────────────────────────────
reg wr_clk = 0;
reg rd_clk = 0;
reg wr_reset_n = 0;
reg rd_reset_n = 0;
reg [WIDTH-1:0] wr_data = 0;
reg wr_en = 0;
wire wr_full;
wire [WIDTH-1:0] rd_data;
wire rd_valid;
reg rd_ack = 0;
always #(WR_PERIOD/2) wr_clk = ~wr_clk;
always #(RD_PERIOD/2) rd_clk = ~rd_clk;
cdc_async_fifo #(
.WIDTH(WIDTH), .DEPTH(DEPTH), .ADDR_BITS(3)
) dut (
.wr_clk(wr_clk), .wr_reset_n(wr_reset_n),
.wr_data(wr_data), .wr_en(wr_en), .wr_full(wr_full),
.rd_clk(rd_clk), .rd_reset_n(rd_reset_n),
.rd_data(rd_data), .rd_valid(rd_valid), .rd_ack(rd_ack)
);
// ── Helper tasks ─────────────────────────────────────────
task do_reset;
begin
wr_en = 0; rd_ack = 0; wr_data = 0;
wr_reset_n = 0; rd_reset_n = 0;
#100;
wr_reset_n = 1; rd_reset_n = 1;
#50;
end
endtask
task wait_wr_n;
input integer n;
integer k;
begin
for (k = 0; k < n; k = k + 1) @(posedge wr_clk);
end
endtask
task wait_rd_n;
input integer n;
integer k;
begin
for (k = 0; k < n; k = k + 1) @(posedge rd_clk);
end
endtask
// ── Read one entry with timeout ──────────────────────────
reg [WIDTH-1:0] read_result;
reg read_ok;
task read_one;
output [WIDTH-1:0] data_out;
output valid_out;
integer timeout;
begin
rd_ack = 1;
valid_out = 0;
data_out = {WIDTH{1'bx}};
for (timeout = 0; timeout < 20; timeout = timeout + 1) begin
@(posedge rd_clk);
if (rd_valid) begin
data_out = rd_data;
valid_out = 1;
timeout = 999; // break
end
end
@(posedge rd_clk);
rd_ack = 0;
end
endtask
// ── Drain FIFO, return count of entries read ─────────────
integer drain_count;
reg [WIDTH-1:0] drain_buf [0:15];
task drain_fifo;
output integer count;
integer t;
begin
count = 0;
rd_ack = 1;
for (t = 0; t < 60; t = t + 1) begin
@(posedge rd_clk);
if (rd_valid && count < 16) begin
drain_buf[count] = rd_data;
count = count + 1;
end
end
rd_ack = 0;
wait_rd_n(3);
end
endtask
// ══════════════════════════════════════════════════════════
// MAIN TEST SEQUENCE
// ══════════════════════════════════════════════════════════
initial begin
$dumpfile("tb_p0_async_fifo.vcd");
$dumpvars(0, tb_p0_async_fifo);
do_reset;
// ──────────────────────────────────────────────────────
// GROUP 1: Empty FIFO — no spurious rd_valid
// ──────────────────────────────────────────────────────
$display("\n=== GROUP 1: Empty FIFO behavior ===");
// 1a: rd_valid must be 0 when nothing written
wait_rd_n(10);
check(rd_valid == 0, "Empty FIFO: rd_valid is 0 (no writes)");
// 1b: rd_ack on empty must not produce spurious valid
rd_ack = 1;
wait_rd_n(10);
check(rd_valid == 0, "Empty FIFO: rd_ack on empty produces no valid");
rd_ack = 0;
wait_rd_n(3);
// ──────────────────────────────────────────────────────
// GROUP 2: Single write/read
// ──────────────────────────────────────────────────────
$display("\n=== GROUP 2: Single write/read ===");
@(posedge wr_clk); #1;
wr_data = 18'h2ABCD;
wr_en = 1;
@(posedge wr_clk); #1;
wr_en = 0;
// Wait for CDC propagation
wait_rd_n(6);
check(rd_valid == 1, "Single write: rd_valid asserted");
check(rd_data == 18'h2ABCD, "Single write: data integrity");
// ACK and verify deassert
#1; rd_ack = 1;
@(posedge rd_clk); #1;
rd_ack = 0;
wait_rd_n(6);
check(rd_valid == 0, "Single write: rd_valid deasserts after ack+empty");
// ──────────────────────────────────────────────────────
// GROUP 3: Fill to capacity
// ──────────────────────────────────────────────────────
// NOTE: This FIFO uses a pre-fetch show-ahead architecture.
// When the FIFO goes from empty to non-empty, the read domain
// auto-presents the first entry into rd_data_reg, advancing
// rd_ptr by 1. This frees one slot in the underlying memory,
// so wr_full requires DEPTH+1 writes (DEPTH in mem + 1 in the
// output register). This is necessary because a combinational
// read from mem across clock domains would be CDC-unsafe.
$display("\n=== GROUP 3: Fill to capacity ===");
do_reset;
// Write DEPTH entries
for (i = 0; i < DEPTH; i = i + 1) begin
@(posedge wr_clk); #1;
wr_data = i[17:0] + 18'h100;
wr_en = 1;
end
@(posedge wr_clk); #1;
wr_en = 0;
// Wait for auto-present round-trip through both synchronizers
wait_wr_n(12);
// After auto-present, rd_ptr advanced by 1 → 1 slot freed → not full yet
check(wr_full == 0, "Pre-fetch show-ahead: DEPTH writes, 1 auto-present frees slot");
// Write one more entry into the freed slot → now truly full
@(posedge wr_clk); #1;
wr_data = 18'hFACE;
wr_en = 1;
@(posedge wr_clk); #1;
wr_en = 0;
wait_wr_n(6);
check(wr_full == 1, "Fill-to-full: wr_full asserted after DEPTH+1 writes");
// ──────────────────────────────────────────────────────
// GROUP 4: Overflow — write when full
// ──────────────────────────────────────────────────────
$display("\n=== GROUP 4: Overflow protection ===");
// Attempt to write 3 more entries while full
for (i = 0; i < 3; i = i + 1) begin
@(posedge wr_clk); #1;
wr_data = 18'h3DEAD + i[17:0];
wr_en = 1;
end
@(posedge wr_clk); #1;
wr_en = 0;
// Drain and verify DEPTH+1 entries (DEPTH mem + 1 output register)
drain_fifo(drain_count);
check(drain_count == DEPTH + 1, "Overflow: exactly DEPTH+1 entries (overflow rejected)");
// Verify data integrity — check first DEPTH entries + the extra FACE entry
begin : overflow_data_check
reg data_ok;
data_ok = 1;
// First entry is the auto-presented one (index 0 from Group 3)
if (drain_buf[0] !== 18'h100) begin
$display(" overflow corruption at [0]: expected %h, got %h",
18'h100, drain_buf[0]);
data_ok = 0;
end
// Next DEPTH-1 entries are indices 1..DEPTH-1
for (i = 1; i < DEPTH; i = i + 1) begin
if (drain_buf[i] !== i[17:0] + 18'h100) begin
$display(" overflow corruption at [%0d]: expected %h, got %h",
i, i[17:0] + 18'h100, drain_buf[i]);
data_ok = 0;
end
end
// Last entry is the FACE entry from the +1 write
if (drain_buf[DEPTH] !== 18'hFACE) begin
$display(" overflow corruption at [%0d]: expected %h, got %h",
DEPTH, 18'hFACE, drain_buf[DEPTH]);
data_ok = 0;
end
check(data_ok, "Overflow: all DEPTH+1 entries data intact (no corruption)");
end
// ──────────────────────────────────────────────────────
// GROUP 5: Data ordering under sustained streaming
// ──────────────────────────────────────────────────────
$display("\n=== GROUP 5: Sustained streaming order ===");
do_reset;
// Simulate CIC-decimated DDC output: 1 sample per 4 wr_clks
// Reader continuously ACKs (rate-matched at 100 MHz)
begin : stream_test
reg [WIDTH-1:0] expected_val;
integer read_idx;
reg ordering_ok;
ordering_ok = 1;
read_idx = 0;
fork
// Writer: 32 samples, 1 per 4 wr_clks (rate-matched to rd_clk)
begin : stream_writer
integer w;
for (w = 0; w < 32; w = w + 1) begin
@(posedge wr_clk); #1;
wr_data = w[17:0] + 18'h1000;
wr_en = 1;
@(posedge wr_clk); #1;
wr_en = 0;
wait_wr_n(2); // 4 wr_clks total per sample
end
end
// Reader: continuously consume at rd_clk rate
begin : stream_reader
integer rd_t;
rd_ack = 1;
for (rd_t = 0; rd_t < 500 && read_idx < 32; rd_t = rd_t + 1) begin
@(posedge rd_clk);
if (rd_valid) begin
expected_val = read_idx[17:0] + 18'h1000;
if (rd_data !== expected_val) begin
$display(" stream order error at [%0d]: expected %h, got %h",
read_idx, expected_val, rd_data);
ordering_ok = 0;
end
read_idx = read_idx + 1;
end
end
#1; rd_ack = 0;
end
join
check(read_idx == 32, "Streaming: all 32 samples received");
check(ordering_ok, "Streaming: FIFO order preserved");
end
// ──────────────────────────────────────────────────────
// GROUP 6: Reset mid-transfer
// ──────────────────────────────────────────────────────
$display("\n=== GROUP 6: Reset mid-transfer ===");
do_reset;
// Write 4 entries
for (i = 0; i < 4; i = i + 1) begin
@(posedge wr_clk); #1;
wr_data = i[17:0] + 18'hAA00;
wr_en = 1;
end
@(posedge wr_clk); #1;
wr_en = 0;
wait_wr_n(3);
// Assert reset while data is in FIFO
wr_reset_n = 0; rd_reset_n = 0;
#50;
wr_reset_n = 1; rd_reset_n = 1;
#50;
// 6a: FIFO must be empty after reset
wait_rd_n(10);
check(rd_valid == 0, "Reset mid-xfer: FIFO empty (no stale data)");
check(wr_full == 0, "Reset mid-xfer: wr_full deasserted");
// 6b: New write after reset must work
@(posedge wr_clk); #1;
wr_data = 18'h3CAFE;
wr_en = 1;
@(posedge wr_clk); #1;
wr_en = 0;
wait_rd_n(6);
check(rd_valid == 1, "Reset recovery: rd_valid for new write");
check(rd_data == 18'h3CAFE, "Reset recovery: correct data");
#1; rd_ack = 1; @(posedge rd_clk); #1; rd_ack = 0;
wait_rd_n(5);
// ──────────────────────────────────────────────────────
// GROUP 7: Burst writes at max wr_clk rate
// ──────────────────────────────────────────────────────
$display("\n=== GROUP 7: Max-rate burst ===");
do_reset;
// Write 7 entries back-to-back (1 per wr_clk, no decimation)
for (i = 0; i < 7; i = i + 1) begin
@(posedge wr_clk); #1;
wr_data = i[17:0] + 18'hB000;
wr_en = 1;
end
@(posedge wr_clk); #1;
wr_en = 0;
// Drain and count
drain_fifo(drain_count);
check(drain_count == 7, "Burst: all 7 entries received (no drops)");
// ──────────────────────────────────────────────────────
// GROUP 8: wr_full deasserts after read
// ──────────────────────────────────────────────────────
$display("\n=== GROUP 8: wr_full release ===");
do_reset;
// Fill FIFO: DEPTH entries first
for (i = 0; i < DEPTH; i = i + 1) begin
@(posedge wr_clk); #1;
wr_data = i[17:0];
wr_en = 1;
end
@(posedge wr_clk); #1;
wr_en = 0;
// Wait for auto-present round-trip
wait_wr_n(12);
// Write the +1 entry (into the slot freed by auto-present)
@(posedge wr_clk); #1;
wr_data = 18'h3BEEF;
wr_en = 1;
@(posedge wr_clk); #1;
wr_en = 0;
wait_wr_n(6);
check(wr_full == 1, "wr_full release: initially full (DEPTH+1 writes)");
// Read one entry (ACK the auto-presented data)
#1; rd_ack = 1;
wait_rd_n(2);
#1; rd_ack = 0;
// Wait for rd_ptr sync back to wr domain (2 wr_clk cycles + margin)
wait_wr_n(10);
check(wr_full == 0, "wr_full release: deasserts after 1 read");
// Drain rest
drain_fifo(drain_count);
wait_rd_n(5);
// ──────────────────────────────────────────────────────
// GROUP 9: Alternating single-entry throughput
// ──────────────────────────────────────────────────────
$display("\n=== GROUP 9: Alternating single-entry ===");
do_reset;
begin : alt_test
reg alt_ok;
reg alt_got_valid;
integer rd_w;
alt_ok = 1;
for (i = 0; i < 12; i = i + 1) begin
// Write 1
@(posedge wr_clk); #1;
wr_data = i[17:0] + 18'hC000;
wr_en = 1;
@(posedge wr_clk); #1;
wr_en = 0;
// Read 1 — wait for auto-present with rd_ack=0, then pulse ack
rd_ack = 0;
alt_got_valid = 0;
for (rd_w = 0; rd_w < 20; rd_w = rd_w + 1) begin
@(posedge rd_clk);
if (rd_valid && !alt_got_valid) begin
alt_got_valid = 1;
if (rd_data !== i[17:0] + 18'hC000) begin
$display(" alt[%0d]: data mismatch", i);
alt_ok = 0;
end
rd_w = 999; // break
end
end
if (!alt_got_valid) begin
$display(" alt[%0d]: no rd_valid after write", i);
alt_ok = 0;
end
// Consume the entry
#1; rd_ack = 1;
@(posedge rd_clk); #1;
rd_ack = 0;
wait_rd_n(2);
end
check(alt_ok, "Alternating: 12 single-entry cycles all correct");
end
// ──────────────────────────────────────────────────────
// GROUP 10: Pathological data patterns
// ──────────────────────────────────────────────────────
$display("\n=== GROUP 10: Pathological data patterns ===");
do_reset;
begin : patho_test
reg patho_ok;
reg patho_seen;
reg [WIDTH-1:0] patterns [0:4];
integer rd_w;
patterns[0] = 18'h3FFFF; // all ones
patterns[1] = 18'h00000; // all zeros
patterns[2] = 18'h2AAAA; // alternating 10...
patterns[3] = 18'h15555; // alternating 01...
patterns[4] = 18'h20001; // MSB + LSB set
patho_ok = 1;
// Write all 5 patterns
for (i = 0; i < 5; i = i + 1) begin
@(posedge wr_clk); #1;
wr_data = patterns[i];
wr_en = 1;
end
@(posedge wr_clk); #1;
wr_en = 0;
// Read one at a time: wait for auto-present, check, ack
rd_ack = 0;
for (i = 0; i < 5; i = i + 1) begin
patho_seen = 0;
for (rd_w = 0; rd_w < 30; rd_w = rd_w + 1) begin
@(posedge rd_clk);
if (rd_valid && !patho_seen) begin
patho_seen = 1;
if (rd_data !== patterns[i]) begin
$display(" pattern[%0d]: expected %h got %h",
i, patterns[i], rd_data);
patho_ok = 0;
end
rd_w = 999; // break
end
end
if (!patho_seen) begin
$display(" pattern[%0d]: no valid", i);
patho_ok = 0;
end
// Consume the entry
#1; rd_ack = 1;
@(posedge rd_clk); #1;
rd_ack = 0;
end
check(patho_ok, "Pathological: all 5 bit-patterns survive CDC");
end
// ══════════════════════════════════════════════════════
// SUMMARY
// ══════════════════════════════════════════════════════
$display("\n============================================");
$display(" P0 Fix #1: Async FIFO Adversarial Tests");
$display("============================================");
$display(" PASSED: %0d", pass_count);
$display(" FAILED: %0d", fail_count);
$display("============================================");
if (fail_count > 0)
$display("RESULT: FAIL");
else
$display("RESULT: PASS");
$finish;
end
// Timeout watchdog
initial begin
#1000000;
$display("[FAIL] TIMEOUT: simulation exceeded 1ms");
$finish;
end
endmodule
9_Firmware/9_2_FPGA/tb/tb_p0_frame_pulse.v
-361
View File
@@ -1,361 +0,0 @@
`timescale 1ns / 1ps
// ============================================================================
// ADVERSARIAL TESTBENCH: frame_complete Pulse Width (P0 Fix #7)
// ============================================================================
// Tests the falling-edge pulse detection pattern used in doppler_processor.v
// (lines 533-551) for the frame_complete signal.
//
// The OLD code held frame_complete as a continuous level whenever the
// Doppler processor was idle. This caused the AGC (rx_gain_control) to
// re-evaluate every clock with zeroed accumulators, collapsing gain control.
//
// The FIX detects the falling edge of processing_active:
// assign processing_active = (state != S_IDLE);
// reg processing_active_prev;
// always @(posedge clk or negedge reset_n)
// processing_active_prev <= processing_active;
// assign frame_complete = (~processing_active & processing_active_prev);
//
// This DUT wrapper replicates the EXACT pattern from doppler_processor.v.
// The adversarial tests drive the state input and verify:
// - Pulse width is EXACTLY 1 clock cycle
// - No pulse during extended idle
// - No pulse on reset deassertion
// - Back-to-back frame completions produce distinct pulses
// - State transitions not touching S_IDLE produce no pulse
// - OLD behavior (continuous level) is regressed
// ============================================================================
// ── DUT: Exact replica of doppler_processor.v frame_complete logic ──
module frame_complete_dut (
input wire clk,
input wire reset_n,
input wire [3:0] state, // Mimic doppler FSM state input
output wire processing_active,
output wire frame_complete
);
// S_IDLE encoding from doppler_processor_optimized
localparam [3:0] S_IDLE = 4'd0;
assign processing_active = (state != S_IDLE);
reg processing_active_prev;
always @(posedge clk or negedge reset_n) begin
if (!reset_n)
processing_active_prev <= 1'b0;
else
processing_active_prev <= processing_active;
end
assign frame_complete = (~processing_active & processing_active_prev);
endmodule
// ── TESTBENCH ────────────────────────────────────────────────
module tb_p0_frame_pulse;
localparam CLK_PERIOD = 10.0; // 100 MHz
// Doppler FSM state encodings (from doppler_processor_optimized)
localparam [3:0] S_IDLE = 4'd0;
localparam [3:0] S_ACCUMULATE = 4'd1;
localparam [3:0] S_WINDOW = 4'd2;
localparam [3:0] S_FFT = 4'd3;
localparam [3:0] S_OUTPUT = 4'd4;
localparam [3:0] S_NEXT_BIN = 4'd5;
// ── Test bookkeeping ─────────────────────────────────────
integer pass_count = 0;
integer fail_count = 0;
integer test_num = 0;
integer i;
task check;
input cond;
input [511:0] label;
begin
test_num = test_num + 1;
if (cond) begin
$display("[PASS] Test %0d: %0s", test_num, label);
pass_count = pass_count + 1;
end else begin
$display("[FAIL] Test %0d: %0s", test_num, label);
fail_count = fail_count + 1;
end
end
endtask
// ── DUT signals ──────────────────────────────────────────
reg clk = 0;
reg reset_n = 0;
reg [3:0] state = S_IDLE;
wire processing_active;
wire frame_complete;
always #(CLK_PERIOD/2) clk = ~clk;
frame_complete_dut dut (
.clk(clk),
.reset_n(reset_n),
.state(state),
.processing_active(processing_active),
.frame_complete(frame_complete)
);
// ── Helper ───────────────────────────────────────────────
task wait_n;
input integer n;
integer k;
begin
for (k = 0; k < n; k = k + 1) @(posedge clk);
end
endtask
// ── Count frame_complete pulses over N clocks ────────────
integer pulse_count;
task count_pulses;
input integer n_clocks;
output integer count;
integer c;
begin
count = 0;
for (c = 0; c < n_clocks; c = c + 1) begin
@(posedge clk);
if (frame_complete) count = count + 1;
end
end
endtask
// ══════════════════════════════════════════════════════════
// MAIN TEST SEQUENCE
// ══════════════════════════════════════════════════════════
initial begin
$dumpfile("tb_p0_frame_pulse.vcd");
$dumpvars(0, tb_p0_frame_pulse);
// ── RESET ────────────────────────────────────────────
state = S_IDLE;
reset_n = 0;
#100;
reset_n = 1;
@(posedge clk);
@(posedge clk);
// ──────────────────────────────────────────────────────
// TEST 1: No pulse on reset deassertion
// ──────────────────────────────────────────────────────
$display("\n=== TEST 1: Reset deassertion ===");
// processing_active = 0 (state = S_IDLE)
// processing_active_prev was reset to 0
// frame_complete = ~0 & 0 = 0
check(frame_complete == 0, "No pulse on reset deassertion (both 0)");
// ──────────────────────────────────────────────────────
// TEST 2: No pulse during extended idle
// ──────────────────────────────────────────────────────
$display("\n=== TEST 2: Extended idle ===");
count_pulses(200, pulse_count);
check(pulse_count == 0, "No pulse during 200 clocks of continuous idle");
// ──────────────────────────────────────────────────────
// TEST 3: Single frame completion — pulse width = 1
// ──────────────────────────────────────────────────────
$display("\n=== TEST 3: Single frame completion ===");
// Enter active state
@(posedge clk); #1;
state = S_ACCUMULATE;
wait_n(5);
check(processing_active == 1, "Active: processing_active = 1");
check(frame_complete == 0, "Active: no frame_complete while active");
// Stay active for 50 clocks (various states)
#1; state = S_WINDOW; wait_n(10);
#1; state = S_FFT; wait_n(10);
#1; state = S_OUTPUT; wait_n(10);
#1; state = S_NEXT_BIN; wait_n(10);
check(frame_complete == 0, "Active (multi-state): no frame_complete");
// Return to idle — should produce exactly 1 pulse
#1; state = S_IDLE;
@(posedge clk);
// On this edge: processing_active = 0, processing_active_prev = 1
// frame_complete = ~0 & 1 = 1
check(frame_complete == 1, "Completion: frame_complete fires");
@(posedge clk);
// Now: processing_active_prev catches up to 0
// frame_complete = ~0 & 0 = 0
check(frame_complete == 0, "Completion: pulse is EXACTLY 1 cycle wide");
// Verify no more pulses
count_pulses(100, pulse_count);
check(pulse_count == 0, "Post-completion: no re-fire during idle");
// ──────────────────────────────────────────────────────
// TEST 4: Back-to-back frame completions
// ──────────────────────────────────────────────────────
$display("\n=== TEST 4: Back-to-back completions ===");
begin : backtoback_test
integer total_pulses;
total_pulses = 0;
// Do 5 rapid frame cycles
for (i = 0; i < 5; i = i + 1) begin
// Go active
@(posedge clk); #1;
state = S_ACCUMULATE;
wait_n(3);
// Return to idle
#1; state = S_IDLE;
@(posedge clk);
if (frame_complete) total_pulses = total_pulses + 1;
@(posedge clk); // pulse should be gone
if (frame_complete) begin
$display(" [WARN] frame %0d: pulse persisted > 1 cycle", i);
end
end
check(total_pulses == 5, "Back-to-back: exactly 5 pulses for 5 completions");
end
// ──────────────────────────────────────────────────────
// TEST 5: State transitions not touching S_IDLE
// ──────────────────────────────────────────────────────
$display("\n=== TEST 5: Non-idle transitions ===");
@(posedge clk); #1;
state = S_ACCUMULATE;
wait_n(3);
// Cycle through active states without returning to idle
begin : nonidle_test
integer nonidle_pulses;
nonidle_pulses = 0;
#1; state = S_WINDOW;
@(posedge clk);
if (frame_complete) nonidle_pulses = nonidle_pulses + 1;
#1; state = S_FFT;
@(posedge clk);
if (frame_complete) nonidle_pulses = nonidle_pulses + 1;
#1; state = S_OUTPUT;
@(posedge clk);
if (frame_complete) nonidle_pulses = nonidle_pulses + 1;
#1; state = S_NEXT_BIN;
@(posedge clk);
if (frame_complete) nonidle_pulses = nonidle_pulses + 1;
#1; state = S_ACCUMULATE;
wait_n(10);
count_pulses(10, pulse_count);
nonidle_pulses = nonidle_pulses + pulse_count;
check(nonidle_pulses == 0,
"Non-idle transitions: zero pulses (all states active)");
end
// Return to idle (one pulse expected)
#1; state = S_IDLE;
@(posedge clk);
check(frame_complete == 1, "Cleanup: pulse on final idle transition");
@(posedge clk);
// ──────────────────────────────────────────────────────
// TEST 6: Long active period — no premature pulse
// ──────────────────────────────────────────────────────
$display("\n=== TEST 6: Long active period ===");
@(posedge clk); #1;
state = S_FFT;
count_pulses(500, pulse_count);
check(pulse_count == 0, "Long active (500 clocks): no premature pulse");
#1; state = S_IDLE;
@(posedge clk);
check(frame_complete == 1, "Long active → idle: pulse fires");
@(posedge clk);
check(frame_complete == 0, "Long active → idle: single cycle only");
// ──────────────────────────────────────────────────────
// TEST 7: Reset during active state
// ──────────────────────────────────────────────────────
$display("\n=== TEST 7: Reset during active ===");
@(posedge clk); #1;
state = S_ACCUMULATE;
wait_n(5);
// Assert reset while active
reset_n = 0;
#50;
// During reset: processing_active_prev forced to 0
// state still = S_ACCUMULATE, processing_active = 1
reset_n = 1;
@(posedge clk);
@(posedge clk);
// After reset release: prev = 0, active = 1
// frame_complete = ~1 & 0 = 0 (no spurious pulse)
check(frame_complete == 0, "Reset during active: no spurious pulse");
// Now go idle — should pulse
#1; state = S_IDLE;
@(posedge clk);
check(frame_complete == 1, "Reset recovery: pulse on idle after active");
@(posedge clk);
// ──────────────────────────────────────────────────────
// TEST 8: REGRESSION — old continuous-level behavior
// ──────────────────────────────────────────────────────
$display("\n=== TEST 8: REGRESSION ===");
// OLD code: frame_complete = (state == S_IDLE && frame_buffer_full == 0)
// This held frame_complete HIGH for the entire idle period.
// With AGC sampling frame_complete, this caused re-evaluation every clock.
//
// The FIX produces a 1-cycle pulse. We've proven:
// - Pulse width = 1 cycle (Test 3)
// - No re-fire during idle (Test 2, 3)
// - Old behavior would have frame_complete = 1 for 200+ clocks (Test 2)
//
// Quantify: old code would produce 200 "events" over 200 idle clocks.
// New code produces 0. This is the fix.
state = S_IDLE;
count_pulses(200, pulse_count);
check(pulse_count == 0,
"REGRESSION: 0 pulses in 200 idle clocks (old code: 200)");
// ══════════════════════════════════════════════════════
// SUMMARY
// ══════════════════════════════════════════════════════
$display("\n============================================");
$display(" P0 Fix #7: frame_complete Pulse Tests");
$display("============================================");
$display(" PASSED: %0d", pass_count);
$display(" FAILED: %0d", fail_count);
$display("============================================");
if (fail_count > 0)
$display("RESULT: FAIL");
else
$display("RESULT: PASS");
$finish;
end
// Timeout watchdog
initial begin
#500000;
$display("[FAIL] TIMEOUT: simulation exceeded 500us");
$finish;
end
endmodule
9_Firmware/9_2_FPGA/tb/tb_p0_mf_adversarial.v
-602
View File
@@ -1,602 +0,0 @@
`timescale 1ns / 1ps
// ============================================================================
// ADVERSARIAL TESTBENCH: Matched Filter Fixes (P0 Fixes #2, #3, #4)
// ============================================================================
// Tests three critical signal-processing invariant fixes in
// matched_filter_multi_segment.v:
//
// Fix #2 — Toggle detection: XOR replaces AND+NOT so both edges of
// mc_new_chirp generate chirp_start_pulse (not just 0→1).
//
// Fix #3 — Listen delay: ST_WAIT_LISTEN state skips TX chirp duration
// (counting ddc_valid pulses) before collecting echo samples.
//
// Fix #4 — Overlap-save trim: First 128 output bins of segments 1+
// are suppressed (circular convolution artifacts).
//
// A STUB processing chain replaces the real FFT pipeline, providing
// controlled timing for state machine verification.
// ============================================================================
// ============================================================================
// STUB: matched_filter_processing_chain
// ============================================================================
// Same port signature as the real module. Accepts 1024 adc_valid samples,
// simulates a short processing delay, then outputs 1024 range_profile_valid
// pulses with incrementing data. chain_state reports 0 when idle.
// ============================================================================
module matched_filter_processing_chain (
input wire clk,
input wire reset_n,
input wire [15:0] adc_data_i,
input wire [15:0] adc_data_q,
input wire adc_valid,
input wire [5:0] chirp_counter,
input wire [15:0] long_chirp_real,
input wire [15:0] long_chirp_imag,
input wire [15:0] short_chirp_real,
input wire [15:0] short_chirp_imag,
output reg signed [15:0] range_profile_i,
output reg signed [15:0] range_profile_q,
output reg range_profile_valid,
output wire [3:0] chain_state
);
localparam [3:0] ST_IDLE = 4'd0;
localparam [3:0] ST_COLLECTING = 4'd1;
localparam [3:0] ST_DELAY = 4'd2;
localparam [3:0] ST_OUTPUTTING = 4'd3;
localparam [3:0] ST_DONE = 4'd9;
reg [3:0] state = ST_IDLE;
reg [10:0] count = 0;
assign chain_state = state;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
state <= ST_IDLE;
count <= 0;
range_profile_valid <= 0;
range_profile_i <= 0;
range_profile_q <= 0;
end else begin
range_profile_valid <= 0;
case (state)
ST_IDLE: begin
count <= 0;
if (adc_valid) begin
state <= ST_COLLECTING;
count <= 1;
end
end
ST_COLLECTING: begin
if (adc_valid) begin
count <= count + 1;
if (count >= 11'd1023) begin
state <= ST_DELAY;
count <= 0;
end
end
end
ST_DELAY: begin
// Simulate processing latency (8 clocks)
count <= count + 1;
if (count >= 11'd7) begin
state <= ST_OUTPUTTING;
count <= 0;
end
end
ST_OUTPUTTING: begin
range_profile_valid <= 1;
range_profile_i <= count[15:0];
range_profile_q <= ~count[15:0];
count <= count + 1;
if (count >= 11'd1023) begin
state <= ST_DONE;
end
end
ST_DONE: begin
state <= ST_IDLE;
end
default: state <= ST_IDLE;
endcase
end
end
endmodule
// ============================================================================
// TESTBENCH
// ============================================================================
module tb_p0_mf_adversarial;
localparam CLK_PERIOD = 10.0; // 100 MHz
// Override matched_filter parameters for fast simulation
localparam TB_LONG_CHIRP = 2000; // echo samples + listen delay target
localparam TB_SHORT_CHIRP = 10;
localparam TB_LONG_SEGS = 3;
localparam TB_SHORT_SEGS = 1;
localparam TB_OVERLAP = 128;
localparam TB_BUF_SIZE = 1024;
localparam TB_SEG_ADVANCE = TB_BUF_SIZE - TB_OVERLAP; // 896
// ── Test bookkeeping ─────────────────────────────────────
integer pass_count = 0;
integer fail_count = 0;
integer test_num = 0;
integer i;
task check;
input cond;
input [511:0] label;
begin
test_num = test_num + 1;
if (cond) begin
$display("[PASS] Test %0d: %0s", test_num, label);
pass_count = pass_count + 1;
end else begin
$display("[FAIL] Test %0d: %0s", test_num, label);
fail_count = fail_count + 1;
end
end
endtask
// ── DUT signals ──────────────────────────────────────────
reg clk = 0;
reg reset_n = 0;
reg signed [17:0] ddc_i = 0;
reg signed [17:0] ddc_q = 0;
reg ddc_valid = 0;
reg use_long_chirp = 0;
reg [5:0] chirp_counter = 0;
reg mc_new_chirp = 0;
reg mc_new_elevation = 0;
reg mc_new_azimuth = 0;
reg [15:0] long_chirp_real = 0;
reg [15:0] long_chirp_imag = 0;
reg [15:0] short_chirp_real = 0;
reg [15:0] short_chirp_imag = 0;
reg mem_ready = 1; // Always ready (stub memory)
wire [1:0] segment_request;
wire [9:0] sample_addr_out;
wire mem_request_w;
wire signed [15:0] pc_i_w;
wire signed [15:0] pc_q_w;
wire pc_valid_w;
wire [3:0] status;
always #(CLK_PERIOD/2) clk = ~clk;
matched_filter_multi_segment #(
.BUFFER_SIZE(TB_BUF_SIZE),
.LONG_CHIRP_SAMPLES(TB_LONG_CHIRP),
.SHORT_CHIRP_SAMPLES(TB_SHORT_CHIRP),
.OVERLAP_SAMPLES(TB_OVERLAP),
.SEGMENT_ADVANCE(TB_SEG_ADVANCE),
.LONG_SEGMENTS(TB_LONG_SEGS),
.SHORT_SEGMENTS(TB_SHORT_SEGS),
.DEBUG(0)
) dut (
.clk(clk),
.reset_n(reset_n),
.ddc_i(ddc_i),
.ddc_q(ddc_q),
.ddc_valid(ddc_valid),
.use_long_chirp(use_long_chirp),
.chirp_counter(chirp_counter),
.mc_new_chirp(mc_new_chirp),
.mc_new_elevation(mc_new_elevation),
.mc_new_azimuth(mc_new_azimuth),
.long_chirp_real(long_chirp_real),
.long_chirp_imag(long_chirp_imag),
.short_chirp_real(short_chirp_real),
.short_chirp_imag(short_chirp_imag),
.segment_request(segment_request),
.sample_addr_out(sample_addr_out),
.mem_request(mem_request_w),
.mem_ready(mem_ready),
.pc_i_w(pc_i_w),
.pc_q_w(pc_q_w),
.pc_valid_w(pc_valid_w),
.status(status)
);
// ── Hierarchical refs for observability ──────────────────
wire [3:0] dut_state = dut.state;
wire dut_chirp_pulse = dut.chirp_start_pulse;
wire dut_elev_pulse = dut.elevation_change_pulse;
wire dut_azim_pulse = dut.azimuth_change_pulse;
wire [15:0] dut_listen_count = dut.listen_delay_count;
wire [15:0] dut_listen_target = dut.listen_delay_target;
wire [2:0] dut_segment = dut.current_segment;
wire [10:0] dut_out_bin_count = dut.output_bin_count;
wire dut_overlap_gate = dut.output_in_overlap;
// State constants (mirror matched_filter_multi_segment localparams)
localparam [3:0] ST_IDLE = 4'd0;
localparam [3:0] ST_COLLECT_DATA = 4'd1;
localparam [3:0] ST_ZERO_PAD = 4'd2;
localparam [3:0] ST_WAIT_REF = 4'd3;
localparam [3:0] ST_PROCESSING = 4'd4;
localparam [3:0] ST_WAIT_FFT = 4'd5;
localparam [3:0] ST_OUTPUT = 4'd6;
localparam [3:0] ST_NEXT_SEG = 4'd7;
localparam [3:0] ST_OVERLAP_COPY = 4'd8;
localparam [3:0] ST_WAIT_LISTEN = 4'd9;
// ── Helper tasks ─────────────────────────────────────────
task do_reset;
begin
reset_n = 0;
mc_new_chirp = 0;
mc_new_elevation = 0;
mc_new_azimuth = 0;
ddc_valid = 0;
ddc_i = 0;
ddc_q = 0;
use_long_chirp = 0;
#100;
reset_n = 1;
@(posedge clk);
@(posedge clk); // Let mc_new_chirp_prev settle to 0
end
endtask
task wait_n;
input integer n;
integer k;
begin
for (k = 0; k < n; k = k + 1) @(posedge clk);
end
endtask
// Provide N ddc_valid pulses (continuous, every clock)
task provide_samples;
input integer n;
integer k;
begin
for (k = 0; k < n; k = k + 1) begin
@(posedge clk);
ddc_i <= k[17:0];
ddc_q <= ~k[17:0];
ddc_valid <= 1;
end
@(posedge clk);
ddc_valid <= 0;
end
endtask
// Wait for DUT to reach a specific state (with timeout)
task wait_for_state;
input [3:0] target;
input integer timeout_clks;
integer t;
begin
for (t = 0; t < timeout_clks; t = t + 1) begin
@(posedge clk);
if (dut_state == target) t = timeout_clks + 1; // break
end
end
endtask
// ══════════════════════════════════════════════════════════
// MAIN TEST SEQUENCE
// ══════════════════════════════════════════════════════════
// Counters for overlap trim verification
integer seg0_valid_count;
integer seg1_valid_count;
reg seg0_counting, seg1_counting;
reg bin127_suppressed, bin128_passed;
initial begin
$dumpfile("tb_p0_mf_adversarial.vcd");
$dumpvars(0, tb_p0_mf_adversarial);
seg0_valid_count = 0;
seg1_valid_count = 0;
seg0_counting = 0;
seg1_counting = 0;
bin127_suppressed = 0;
bin128_passed = 0;
do_reset;
// ──────────────────────────────────────────────────────
// GROUP A: TOGGLE DETECTION (Fix #2)
// ──────────────────────────────────────────────────────
$display("\n=== GROUP A: Toggle Detection (Fix #2) ===");
// A1: Rising edge (0→1) generates chirp_start_pulse
@(posedge clk);
check(dut_chirp_pulse == 0, "A1 pre: no pulse before toggle");
#1; mc_new_chirp = 1; // 0→1
@(posedge clk); // pulse should fire (combinational on new vs prev)
check(dut_chirp_pulse == 1, "A1: rising edge (0->1) generates pulse");
// Pulse must be 1 cycle wide
@(posedge clk); // mc_new_chirp_prev updates to 1
check(dut_chirp_pulse == 0, "A1: pulse is single-cycle (gone on next clock)");
// Let state machine settle (it entered ST_WAIT_LISTEN)
do_reset;
// A2: Falling edge (1→0) generates pulse — THIS IS THE FIX
#1; mc_new_chirp = 1;
@(posedge clk); // prev catches up to 1
@(posedge clk); // prev = 1, mc_new_chirp = 1, XOR = 0
check(dut_chirp_pulse == 0, "A2 pre: no pulse when stable high");
#1; mc_new_chirp = 0; // 1→0
@(posedge clk); // XOR: 0 ^ 1 = 1
check(dut_chirp_pulse == 1, "A2: falling edge (1->0) generates pulse (FIX!)");
@(posedge clk);
check(dut_chirp_pulse == 0, "A2: pulse ends after 1 cycle");
do_reset;
// A3: Stable low — no spurious pulses over 50 clocks
begin : stable_low_test
reg any_pulse;
any_pulse = 0;
for (i = 0; i < 50; i = i + 1) begin
@(posedge clk);
if (dut_chirp_pulse) any_pulse = 1;
end
check(!any_pulse, "A3: stable low for 50 clocks — no spurious pulse");
end
// A4: Elevation and azimuth toggles also detected
#1; mc_new_elevation = 1; // 0→1
@(posedge clk);
check(dut_elev_pulse == 1, "A4a: elevation toggle 0->1 detected");
@(posedge clk);
#1; mc_new_elevation = 0; // 1→0
@(posedge clk);
check(dut_elev_pulse == 1, "A4b: elevation toggle 1->0 detected");
#1; mc_new_azimuth = 1;
@(posedge clk);
check(dut_azim_pulse == 1, "A4c: azimuth toggle 0->1 detected");
@(posedge clk);
#1; mc_new_azimuth = 0;
@(posedge clk);
check(dut_azim_pulse == 1, "A4d: azimuth toggle 1->0 detected");
// A5: REGRESSION — verify OLD behavior would have failed
// Old code: chirp_start_pulse = mc_new_chirp && !mc_new_chirp_prev
// This is a rising-edge detector. On 1→0: 0 && !1 = 0 (missed!)
// The NEW XOR code: 0 ^ 1 = 1 (detected!)
// We already proved this works in A2. Document the regression:
$display(" [INFO] A5 REGRESSION: old AND+NOT code produced 0 for 1->0 transition");
$display(" [INFO] old: mc_new_chirp(0) && !mc_new_chirp_prev(1) = 0 && 0 = 0 MISSED");
$display(" [INFO] new: mc_new_chirp(0) ^ mc_new_chirp_prev(1) = 0 ^ 1 = 1 DETECTED");
check(1, "A5: REGRESSION documented — falling edge was missed by old code");
do_reset;
// ──────────────────────────────────────────────────────
// GROUP B: LISTEN DELAY (Fix #3)
// ──────────────────────────────────────────────────────
$display("\n=== GROUP B: Listen Delay (Fix #3) ===");
// Use SHORT chirp: listen_delay_target = TB_SHORT_CHIRP = 10
#1; use_long_chirp = 0;
// B1: Chirp start → enters ST_WAIT_LISTEN (not ST_COLLECT_DATA)
mc_new_chirp = 1; // toggle 0→1
@(posedge clk); // pulse fires, state machine acts
@(posedge clk); // non-blocking assignment settles
check(dut_state == ST_WAIT_LISTEN, "B1: enters ST_WAIT_LISTEN (not COLLECT_DATA)");
check(dut_listen_target == TB_SHORT_CHIRP,
"B1: listen_delay_target = SHORT_CHIRP_SAMPLES");
// B2: Counter increments only on ddc_valid
// Provide 5 valid pulses, then 5 clocks without valid, then 5 more valid
for (i = 0; i < 5; i = i + 1) begin
@(posedge clk);
ddc_valid <= 1;
ddc_i <= i[17:0];
ddc_q <= 0;
end
@(posedge clk);
ddc_valid <= 0;
// Counter should be 5 after 5 valid pulses
@(posedge clk);
check(dut_listen_count == 5, "B2a: counter = 5 after 5 valid pulses");
check(dut_state == ST_WAIT_LISTEN, "B2a: still in ST_WAIT_LISTEN");
// B3: 5 clocks with no valid — counter must NOT advance
wait_n(5);
check(dut_listen_count == 5, "B3: counter stays 5 during ddc_valid gaps");
check(dut_state == ST_WAIT_LISTEN, "B3: still in ST_WAIT_LISTEN");
// B4: Provide remaining pulses to hit boundary
// Need 5 more valid pulses (total 10 = TB_SHORT_CHIRP)
// Counter transitions at >= target-1 = 9, so pulse 10 triggers
for (i = 0; i < 4; i = i + 1) begin
@(posedge clk);
ddc_valid <= 1;
ddc_i <= (i + 5);
ddc_q <= 0;
end
// After 4 more: count = 9 = target-1 → transition happens on THIS valid
@(posedge clk);
ddc_valid <= 1; // 10th pulse
@(posedge clk);
ddc_valid <= 0;
@(posedge clk); // Let non-blocking assignments settle
check(dut_state == ST_COLLECT_DATA,
"B4: transitions to ST_COLLECT_DATA after exact delay count");
// B5: First sample collected is the one AFTER the delay
// The module is now in ST_COLLECT_DATA. Provide a sample and verify
// it gets written to the buffer (buffer_write_ptr should advance)
begin : first_sample_check
reg [10:0] ptr_before;
ptr_before = dut.buffer_write_ptr;
@(posedge clk);
ddc_valid <= 1;
ddc_i <= 18'h1FACE;
ddc_q <= 18'h1BEEF;
@(posedge clk);
ddc_valid <= 0;
@(posedge clk);
check(dut.buffer_write_ptr == ptr_before + 1,
"B5: first echo sample collected (write_ptr advanced)");
end
do_reset;
// ──────────────────────────────────────────────────────
// GROUP C: OVERLAP-SAVE OUTPUT TRIM (Fix #4)
// ──────────────────────────────────────────────────────
$display("\n=== GROUP C: Overlap-Save Output Trim (Fix #4) ===");
// Use LONG chirp with 2+ segments for overlap trim testing
#1; use_long_chirp = 1;
seg0_valid_count = 0;
seg1_valid_count = 0;
// C-SETUP: Trigger chirp, pass through listen delay, process 2 segments
mc_new_chirp = 1; // toggle 0→1
@(posedge clk);
@(posedge clk);
check(dut_state == ST_WAIT_LISTEN, "C-setup: entered ST_WAIT_LISTEN");
check(dut_listen_target == TB_LONG_CHIRP,
"C-setup: listen target = LONG_CHIRP_SAMPLES");
// Pass through listen delay: provide TB_LONG_CHIRP (2000) ddc_valid pulses
$display(" [INFO] Providing %0d listen-delay samples...", TB_LONG_CHIRP);
provide_samples(TB_LONG_CHIRP);
// Should now be in ST_COLLECT_DATA
@(posedge clk);
check(dut_state == ST_COLLECT_DATA,
"C-setup: in ST_COLLECT_DATA after listen delay");
// ── SEGMENT 0: Collect 1024 samples ──
$display(" [INFO] Providing 1024 echo samples for segment 0...");
provide_samples(TB_BUF_SIZE);
// Should transition through WAIT_REF → PROCESSING → WAIT_FFT
// mem_ready is always 1, so WAIT_REF passes immediately
wait_for_state(ST_WAIT_FFT, 2000);
check(dut_state == ST_WAIT_FFT, "C-setup: seg0 reached ST_WAIT_FFT");
check(dut_segment == 0, "C-setup: processing segment 0");
// During ST_WAIT_FFT, the stub chain outputs 1024 fft_pc_valid pulses.
// Count pc_valid_w (the gated output) for segment 0.
seg0_counting = 1;
wait_for_state(ST_OUTPUT, 2000);
seg0_counting = 0;
// C1: Segment 0 — ALL output bins should pass (no trim)
check(seg0_valid_count == TB_BUF_SIZE,
"C1: segment 0 — all 1024 output bins pass (no trim)");
// Let state machine proceed to next segment
wait_for_state(ST_COLLECT_DATA, 500);
check(dut_segment == 1, "C-setup: advanced to segment 1");
// ── SEGMENT 1: Collect 896 samples (buffer starts at 128 from overlap) ──
$display(" [INFO] Providing %0d echo samples for segment 1...", TB_SEG_ADVANCE);
provide_samples(TB_SEG_ADVANCE);
// Wait for seg 1 processing
wait_for_state(ST_WAIT_FFT, 2000);
check(dut_state == ST_WAIT_FFT, "C-setup: seg1 reached ST_WAIT_FFT");
// Count pc_valid_w during segment 1 output
seg1_counting = 1;
bin127_suppressed = 0;
bin128_passed = 0;
// Monitor specific boundary bins during chain output
begin : seg1_output_monitor
integer wait_count;
for (wait_count = 0; wait_count < 2000; wait_count = wait_count + 1) begin
@(posedge clk);
// Check boundary: bin 127 should be suppressed
if (dut_out_bin_count == 127 && dut.fft_pc_valid) begin
if (pc_valid_w == 0) bin127_suppressed = 1;
end
// Check boundary: bin 128 should pass
if (dut_out_bin_count == 128 && dut.fft_pc_valid) begin
if (pc_valid_w == 1) bin128_passed = 1;
end
if (dut_state == ST_OUTPUT) begin
wait_count = 9999; // break
end
end
end
seg1_counting = 0;
// C2: Segment 1 — first 128 bins suppressed, 896 pass
check(seg1_valid_count == TB_SEG_ADVANCE,
"C2: segment 1 — exactly 896 output bins pass (128 trimmed)");
// C3: Boundary bin accuracy
check(bin127_suppressed, "C3a: bin 127 suppressed (overlap artifact)");
check(bin128_passed, "C3b: bin 128 passes (first valid bin)");
// C4: Overlap gate signal logic
// For segment != 0, output_in_overlap should be true when bin_count < 128
check(dut_segment == 1, "C4 pre: still on segment 1");
// (Gate was already verified implicitly by C2/C3 counts)
check(1, "C4: overlap gate correctly suppresses bins [0..127] on seg 1+");
// ══════════════════════════════════════════════════════
// SUMMARY
// ══════════════════════════════════════════════════════
$display("\n============================================");
$display(" P0 Fixes #2/#3/#4: MF Adversarial Tests");
$display("============================================");
$display(" PASSED: %0d", pass_count);
$display(" FAILED: %0d", fail_count);
$display("============================================");
if (fail_count > 0)
$display("RESULT: FAIL");
else
$display("RESULT: PASS");
$finish;
end
// ── Continuous counters for overlap trim verification ────
always @(posedge clk) begin
if (seg0_counting && pc_valid_w)
seg0_valid_count <= seg0_valid_count + 1;
if (seg1_counting && pc_valid_w)
seg1_valid_count <= seg1_valid_count + 1;
end
// Timeout watchdog (generous for 2000-sample listen delay + 2 segments)
initial begin
#5000000;
$display("[FAIL] TIMEOUT: simulation exceeded 5ms");
$finish;
end
endmodule
9_Firmware/9_2_FPGA/tb/tb_radar_receiver_final.v
+2
View File
@@ -139,6 +139,8 @@ radar_receiver_final dut (
// ADC "LVDS" -- stub treats adc_d_p as single-ended data
.adc_d_p(adc_data),
.adc_d_n(~adc_data), // Complement (ignored by stub)
.adc_or_p(1'b0), // F-0.1: no overrange stimulus in this TB
.adc_or_n(1'b1),
.adc_dco_p(clk_400m), // 400 MHz clock
.adc_dco_n(~clk_400m), // Complement (ignored by stub)
.adc_pwdn(),
9_Firmware/9_2_FPGA/tb/tb_system_e2e.v
+116 -8
View File
@@ -382,7 +382,13 @@ end
// ============================================================================
// DUT INSTANTIATION
// ============================================================================
radar_system_top dut (
radar_system_top #(
`ifdef USB_MODE_1
.USB_MODE(1) // FT2232H interface (production 50T board)
`else
.USB_MODE(0) // FT601 interface (200T dev board)
`endif
) dut (
.clk_100m(clk_100m),
.clk_120m_dac(clk_120m_dac),
.ft601_clk_in(ft601_clk_in),
@@ -421,6 +427,8 @@ radar_system_top dut (
.adc_d_n(adc_d_n),
.adc_dco_p(adc_dco_p),
.adc_dco_n(adc_dco_n),
.adc_or_p(1'b0),
.adc_or_n(1'b1),
.adc_pwdn(adc_pwdn),
.stm32_new_chirp(stm32_new_chirp),
@@ -554,10 +562,10 @@ initial begin
do_reset;
// CRITICAL: Configure stream control to range-only BEFORE any chirps
// fire. The USB write FSM blocks on doppler_valid_ft if doppler stream
// is enabled but no Doppler data arrives (needs 32 chirps/frame).
// Without this, the write FSM deadlocks and the read FSM can never
// activate (it requires write FSM == IDLE).
// fire. The USB write FSM gates on pending flags: if doppler stream is
// enabled but no Doppler data arrives (needs 32 chirps/frame), the FSM
// stays in IDLE waiting for doppler_data_pending. With the write FSM
// not in IDLE, the read FSM cannot activate (bus arbitration rule).
bfm_send_cmd(8'h04, 8'h00, 16'h0001); // stream_control = range only
// Wait for stream_control CDC to propagate (2-stage sync in ft601_clk)
// Must be long enough that stream_ctrl_sync_1 is updated before any
@@ -778,7 +786,7 @@ initial begin
// Restore defaults for subsequent tests
bfm_send_cmd(8'h01, 8'h00, 16'h0001); // mode = auto-scan
bfm_send_cmd(8'h04, 8'h00, 16'h0001); // keep range-only (prevents write FSM deadlock)
bfm_send_cmd(8'h04, 8'h00, 16'h0001); // keep range-only (TB lacks 32-chirp doppler data)
bfm_send_cmd(8'h10, 8'h00, 16'd3000); // restore long chirp cycles
$display("");
@@ -913,7 +921,7 @@ initial begin
// Need to re-send configuration since reset clears all registers
stm32_mixers_enable = 1;
ft601_txe = 0;
bfm_send_cmd(8'h04, 8'h00, 16'h0001); // stream_control = range only (prevent deadlock)
bfm_send_cmd(8'h04, 8'h00, 16'h0001); // stream_control = range only (TB lacks doppler data)
#500; // Wait for stream_control CDC
bfm_send_cmd(8'h01, 8'h00, 16'h0001); // auto-scan
bfm_send_cmd(8'h10, 8'h00, 16'd100); // short timing
@@ -932,6 +940,106 @@ initial begin
$display("");
// ================================================================
// GROUP 9B: Adversarial reset sweep (audit F-2.2)
// ================================================================
// Drive the same auto-scan pipeline, then inject reset at four distinct
// offsets relative to a known-good start of operation. For each offset
// the system must:
// (a) present system_status == 0 while held in reset
// (b) produce at least one additional new_chirp_frame within the
// observation window after reset release
// (c) advance obs_range_valid_count (confirms full DDC+MF chain resumes)
// The four offsets are chosen to hit mid-chirp, mid-listen, and around
// the short/long chirp boundary, which covers the interesting FSM and
// CDC transitions in the pipeline.
$display("--- Group 9B: Adversarial reset sweep (F-2.2) ---");
begin : reset_sweep
integer sweep_i;
integer sweep_baseline_range;
integer sweep_baseline_chirp;
integer sweep_offsets [0:3];
integer sweep_holds [0:3];
reg sweep_ok;
// Reset injection offsets (ns) after the last auto-scan reconfigure.
// 3 us / 7 us / 12 us / 18 us — sprayed across a short-chirp burst.
sweep_offsets[0] = 3000;
sweep_offsets[1] = 7000;
sweep_offsets[2] = 12000;
sweep_offsets[3] = 18000;
// Reset-assert durations mix short (~20 clk_100m) and long (~120)
sweep_holds[0] = 200;
sweep_holds[1] = 1200;
sweep_holds[2] = 400;
sweep_holds[3] = 800;
for (sweep_i = 0; sweep_i < 4; sweep_i = sweep_i + 1) begin
// Re-seed auto-scan from a clean base each iteration
reset_n = 0;
bfm_rx_wr_ptr = 0;
bfm_rx_rd_ptr = 0;
#200;
reset_n = 1;
#500;
stm32_mixers_enable = 1;
ft601_txe = 0;
bfm_send_cmd(8'h04, 8'h00, 16'h0001);
#500;
bfm_send_cmd(8'h01, 8'h00, 16'h0001);
bfm_send_cmd(8'h10, 8'h00, 16'd100);
bfm_send_cmd(8'h11, 8'h00, 16'd200);
bfm_send_cmd(8'h12, 8'h00, 16'd100);
bfm_send_cmd(8'h13, 8'h00, 16'd20);
bfm_send_cmd(8'h14, 8'h00, 16'd100);
bfm_send_cmd(8'h15, 8'h00, 16'd4);
// Let the pipeline reach steady-state and capture a baseline
#30000;
sweep_baseline_range = obs_range_valid_count;
sweep_baseline_chirp = obs_chirp_frame_count;
// Wait out the configured offset, then assert reset asynchronously
#(sweep_offsets[sweep_i]);
reset_n = 0;
#(sweep_holds[sweep_i]);
sweep_ok = (system_status == 4'b0000);
check(sweep_ok,
"G9B.a: system_status drops to 0 during injected reset");
// Release reset, re-configure (regs are cleared), allow recovery
reset_n = 1;
#500;
stm32_mixers_enable = 1;
ft601_txe = 0;
bfm_send_cmd(8'h04, 8'h00, 16'h0001);
#500;
bfm_send_cmd(8'h01, 8'h00, 16'h0001);
bfm_send_cmd(8'h10, 8'h00, 16'd100);
bfm_send_cmd(8'h11, 8'h00, 16'd200);
bfm_send_cmd(8'h12, 8'h00, 16'd100);
bfm_send_cmd(8'h13, 8'h00, 16'd20);
bfm_send_cmd(8'h14, 8'h00, 16'd100);
bfm_send_cmd(8'h15, 8'h00, 16'd4);
sweep_baseline_range = obs_range_valid_count;
sweep_baseline_chirp = obs_chirp_frame_count;
#60000; // 60 us — two+ short-chirp frames
check(obs_chirp_frame_count > sweep_baseline_chirp,
"G9B.b: new_chirp_frame resumes after injected reset");
check(obs_range_valid_count > sweep_baseline_range,
"G9B.c: range pipeline resumes after injected reset");
$display(" [F-2.2] iter=%0d offset=%0dns hold=%0dns chirps=+%0d ranges=+%0d",
sweep_i, sweep_offsets[sweep_i], sweep_holds[sweep_i],
obs_chirp_frame_count - sweep_baseline_chirp,
obs_range_valid_count - sweep_baseline_range);
end
end
$display("");
// ================================================================
// GROUP 10: STREAM CONTROL (Gap 2)
// ================================================================
@@ -947,7 +1055,7 @@ initial begin
check(dut.host_stream_control == 3'b000,
"G10.2: All streams disabled (stream_control = 3'b000)");
// G10.3: Re-enable range only (keep range-only to prevent write FSM deadlock)
// G10.3: Re-enable range only (TB uses range-only — no doppler processing)
bfm_send_cmd(8'h04, 8'h00, 16'h0001); // stream_control = 3'b001
check(dut.host_stream_control == 3'b001,
"G10.3: Range stream re-enabled (stream_control = 3'b001)");
9_Firmware/9_2_FPGA/tb/tb_usb_data_interface.v
+180 -210
View File
@@ -6,15 +6,11 @@ module tb_usb_data_interface;
localparam CLK_PERIOD = 10.0; // 100 MHz main clock
localparam FT_CLK_PERIOD = 10.0; // 100 MHz FT601 clock (asynchronous)
// State definitions (mirror the DUT)
localparam [2:0] S_IDLE = 3'd0,
S_SEND_HEADER = 3'd1,
S_SEND_RANGE = 3'd2,
S_SEND_DOPPLER = 3'd3,
S_SEND_DETECT = 3'd4,
S_SEND_FOOTER = 3'd5,
S_WAIT_ACK = 3'd6,
S_SEND_STATUS = 3'd7; // Gap 2: status readback
// State definitions (mirror the DUT — 4-state packed-word FSM)
localparam [3:0] S_IDLE = 4'd0,
S_SEND_DATA_WORD = 4'd1,
S_SEND_STATUS = 4'd2,
S_WAIT_ACK = 4'd3;
// ── Signals ────────────────────────────────────────────────
reg clk;
@@ -219,9 +215,9 @@ module tb_usb_data_interface;
end
endtask
// ── Helper: wait for DUT to reach a specific state ─────────
// ── Helper: wait for DUT to reach a specific write FSM state ──
task wait_for_state;
input [2:0] target;
input [3:0] target;
input integer max_cyc;
integer cnt;
begin
@@ -280,7 +276,7 @@ module tb_usb_data_interface;
// Set data_pending flags directly via hierarchical access.
// This is the standard TB technique for internal state setup —
// bypasses the CDC path for immediate, reliable flag setting.
// Call BEFORE assert_range_valid in tests that need SEND_DOPPLER/DETECT.
// Call BEFORE assert_range_valid in tests that need doppler/cfar data.
task preload_pending_data;
begin
@(posedge ft601_clk_in);
@@ -354,24 +350,26 @@ module tb_usb_data_interface;
end
endtask
// Drive a complete packet through the FSM by sequentially providing
// range, doppler (4x), and cfar valid pulses.
// Drive a complete data packet through the new 3-word packed FSM.
// Pre-loads pending flags, triggers range_valid, and waits for IDLE.
// With the new FSM, all data is pre-packed in IDLE then sent as 3 words.
task drive_full_packet;
input [31:0] rng;
input [15:0] dr;
input [15:0] di;
input det;
begin
// Pre-load pending flags so FSM enters doppler/cfar states
// Set doppler/cfar captured values via CDC inputs
@(posedge clk);
doppler_real = dr;
doppler_imag = di;
cfar_detection = det;
@(posedge clk);
// Pre-load pending flags so FSM includes doppler/cfar in packet
preload_pending_data;
// Trigger the packet
assert_range_valid(rng);
wait_for_state(S_SEND_DOPPLER, 100);
pulse_doppler_once(dr, di);
pulse_doppler_once(dr, di);
pulse_doppler_once(dr, di);
pulse_doppler_once(dr, di);
wait_for_state(S_SEND_DETECT, 100);
pulse_cfar_once(det);
// Wait for complete packet cycle: IDLE → SEND_DATA_WORD(×3) → WAIT_ACK → IDLE
wait_for_state(S_IDLE, 100);
end
endtask
@@ -414,101 +412,138 @@ module tb_usb_data_interface;
"ft601_siwu_n=1 after reset");
// ════════════════════════════════════════════════════════
// TEST GROUP 2: Range data packet
// TEST GROUP 2: Data packet word packing
//
// Use backpressure to freeze the FSM at specific states
// so we can reliably sample outputs.
// New FSM packs 11-byte data into 3 × 32-bit words:
// Word 0: {HEADER, range[31:24], range[23:16], range[15:8]}
// Word 1: {range[7:0], dop_re_hi, dop_re_lo, dop_im_hi}
// Word 2: {dop_im_lo, detection, FOOTER, 0x00} BE=1110
//
// The DUT uses range_data_ready (1-cycle delayed range_valid_ft)
// to trigger packing. Doppler/CFAR _cap registers must be
// pre-loaded via hierarchical access because no valid pulse is
// given in this test (we only want to verify packing, not CDC).
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 2: Range Data Packet ---");
$display("\n--- Test Group 2: Data Packet Word Packing ---");
apply_reset;
ft601_txe = 1; // Stall so we can inspect packed words
// Stall at SEND_HEADER so we can verify first range word later
ft601_txe = 1;
// Set known doppler/cfar values on clk-domain inputs
@(posedge clk);
doppler_real = 16'hABCD;
doppler_imag = 16'hEF01;
cfar_detection = 1'b1;
@(posedge clk);
// Pre-load pending flags AND captured-data registers directly.
// No doppler/cfar valid pulses are given, so the CDC capture path
// never fires — we must set the _cap registers via hierarchical
// access for the word-packing checks to be meaningful.
preload_pending_data;
@(posedge ft601_clk_in);
uut.doppler_real_cap = 16'hABCD;
uut.doppler_imag_cap = 16'hEF01;
uut.cfar_detection_cap = 1'b1;
@(posedge ft601_clk_in);
assert_range_valid(32'hDEAD_BEEF);
wait_for_state(S_SEND_HEADER, 50);
repeat (2) @(posedge ft601_clk_in); #1;
check(uut.current_state === S_SEND_HEADER,
"Stalled in SEND_HEADER (backpressure)");
// Release: FSM drives header then moves to SEND_RANGE_DATA
// FSM should be in SEND_DATA_WORD, stalled on ft601_txe=1
wait_for_state(S_SEND_DATA_WORD, 50);
repeat (2) @(posedge ft601_clk_in); #1;
check(uut.current_state === S_SEND_DATA_WORD,
"Stalled in SEND_DATA_WORD (backpressure)");
// Verify pre-packed words
// range_profile = 0xDEAD_BEEF → range[31:24]=0xDE, [23:16]=0xAD, [15:8]=0xBE, [7:0]=0xEF
// Word 0: {0xAA, 0xDE, 0xAD, 0xBE}
check(uut.data_pkt_word0 === {8'hAA, 8'hDE, 8'hAD, 8'hBE},
"Word 0: {HEADER=AA, range[31:8]}");
// Word 1: {0xEF, 0xAB, 0xCD, 0xEF}
check(uut.data_pkt_word1 === {8'hEF, 8'hAB, 8'hCD, 8'hEF},
"Word 1: {range[7:0], dop_re, dop_im_hi}");
// Word 2: {0x01, detection_byte, 0x55, 0x00}
// detection_byte bit 7 = frame_start (sample_counter==0 → 1), bit 0 = cfar=1
// so detection_byte = 8'b1000_0001 = 8'h81
check(uut.data_pkt_word2 === {8'h01, 8'h81, 8'h55, 8'h00},
"Word 2: {dop_im_lo, det=81, FOOTER=55, pad=00}");
check(uut.data_pkt_be2 === 4'b1110,
"Word 2 BE=1110 (3 valid bytes + 1 pad)");
// Release backpressure and verify word 0 appears on bus.
// On the first posedge with !ft601_txe the FSM drives word 0 and
// advances data_word_idx 0→1 via NBA. After #1 the NBA has
// resolved, so we see idx=1 and ft601_data_out=word0.
ft601_txe = 0;
@(posedge ft601_clk_in); #1;
// Now the FSM registered the header output and will transition
// At the NEXT posedge the state becomes SEND_RANGE_DATA
@(posedge ft601_clk_in); #1;
check(uut.current_state === S_SEND_RANGE,
"Entered SEND_RANGE_DATA after header");
// The first range word should be on the data bus (byte_counter=0 just
// drove range_profile_cap, byte_counter incremented to 1)
check(uut.ft601_data_out === 32'hDEAD_BEEF || uut.byte_counter <= 8'd1,
"Range data word 0 driven (range_profile_cap)");
check(uut.ft601_data_out === {8'hAA, 8'hDE, 8'hAD, 8'hBE},
"Word 0 driven on data bus after backpressure release");
check(ft601_wr_n === 1'b0,
"Write strobe active during range data");
"Write strobe active during SEND_DATA_WORD");
check(ft601_be === 4'b1111,
"Byte enable=1111 for range data");
"Byte enable=1111 for word 0");
check(uut.ft601_data_oe === 1'b1,
"Data bus output enabled during SEND_DATA_WORD");
// Wait for all 4 range words to complete
wait_for_state(S_SEND_DOPPLER, 50);
#1;
check(uut.current_state === S_SEND_DOPPLER,
"Advanced to SEND_DOPPLER_DATA after 4 range words");
// Next posedge: FSM drives word 1, advances idx 1→2.
// After NBA: idx=2, ft601_data_out=word1.
@(posedge ft601_clk_in); #1;
check(uut.data_word_idx === 2'd2,
"data_word_idx advanced past word 1 (now 2)");
check(uut.ft601_data_out === {8'hEF, 8'hAB, 8'hCD, 8'hEF},
"Word 1 driven on data bus");
check(ft601_be === 4'b1111,
"Byte enable=1111 for word 1");
// Next posedge: FSM drives word 2, idx resets 2→0,
// and current_state transitions to WAIT_ACK.
@(posedge ft601_clk_in); #1;
check(uut.current_state === S_WAIT_ACK,
"Transitioned to WAIT_ACK after 3 data words");
check(uut.ft601_data_out === {8'h01, 8'h81, 8'h55, 8'h00},
"Word 2 driven on data bus");
check(ft601_be === 4'b1110,
"Byte enable=1110 for word 2 (last byte is pad)");
// Then back to IDLE
@(posedge ft601_clk_in); #1;
check(uut.current_state === S_IDLE,
"Returned to IDLE after WAIT_ACK");
// ════════════════════════════════════════════════════════
// TEST GROUP 3: Header verification (stall to observe)
// TEST GROUP 3: Header and footer verification
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 3: Header Verification ---");
$display("\n--- Test Group 3: Header and Footer Verification ---");
apply_reset;
ft601_txe = 1; // Stall at SEND_HEADER
ft601_txe = 1; // Stall to inspect
@(posedge clk);
range_profile = 32'hCAFE_BABE;
range_valid = 1;
repeat (4) @(posedge ft601_clk_in);
doppler_real = 16'h0000;
doppler_imag = 16'h0000;
cfar_detection = 1'b0;
@(posedge clk);
range_valid = 0;
repeat (3) @(posedge ft601_clk_in);
preload_pending_data;
assert_range_valid(32'hCAFE_BABE);
wait_for_state(S_SEND_HEADER, 50);
wait_for_state(S_SEND_DATA_WORD, 50);
repeat (2) @(posedge ft601_clk_in); #1;
check(uut.current_state === S_SEND_HEADER,
"Stalled in SEND_HEADER with backpressure");
// Release backpressure - header will be latched at next posedge
ft601_txe = 0;
@(posedge ft601_clk_in); #1;
check(uut.ft601_data_out[7:0] === 8'hAA,
"Header byte 0xAA on data bus");
check(ft601_be === 4'b0001,
"Byte enable=0001 for header (lower byte only)");
check(ft601_wr_n === 1'b0,
"Write strobe active during header");
check(uut.ft601_data_oe === 1'b1,
"Data bus output enabled during header");
// Header is in byte 3 (MSB) of word 0
check(uut.data_pkt_word0[31:24] === 8'hAA,
"Header byte 0xAA in word 0 MSB");
// Footer is in byte 1 (bits [15:8]) of word 2
check(uut.data_pkt_word2[15:8] === 8'h55,
"Footer byte 0x55 in word 2");
// ════════════════════════════════════════════════════════
// TEST GROUP 4: Doppler data verification
// TEST GROUP 4: Doppler data capture verification
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 4: Doppler Data Verification ---");
$display("\n--- Test Group 4: Doppler Data Capture ---");
apply_reset;
ft601_txe = 0;
// Preload only doppler pending (not cfar) so the FSM sends
// doppler data. After doppler, SEND_DETECT sees cfar_data_pending=0
// and skips to SEND_FOOTER, then WAIT_ACK, then IDLE.
preload_doppler_pending;
assert_range_valid(32'h0000_0001);
wait_for_state(S_SEND_DOPPLER, 100);
#1;
check(uut.current_state === S_SEND_DOPPLER,
"Reached SEND_DOPPLER_DATA");
// Provide doppler data via valid pulse (updates captured values)
@(posedge clk);
doppler_real = 16'hAAAA;
@@ -524,110 +559,70 @@ module tb_usb_data_interface;
check(uut.doppler_imag_cap === 16'h5555,
"doppler_imag captured correctly");
// The FSM has doppler_data_pending set and sends 4 bytes, then
// transitions past SEND_DETECT (cfar_data_pending=0) to IDLE.
// Drive a packet with pending doppler + cfar (both needed for gating
// since all streams are enabled after reset/apply_reset).
preload_pending_data;
assert_range_valid(32'h0000_0001);
wait_for_state(S_IDLE, 100);
#1;
check(uut.current_state === S_IDLE,
"Doppler done, packet completed");
"Packet completed with doppler data");
check(uut.doppler_data_pending === 1'b0,
"doppler_data_pending cleared after packet");
// ════════════════════════════════════════════════════════
// TEST GROUP 5: CFAR detection data
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 5: CFAR Detection Data ---");
// Start a new packet with both doppler and cfar pending to verify
// cfar data is properly sent in SEND_DETECTION_DATA.
apply_reset;
ft601_txe = 0;
preload_pending_data;
assert_range_valid(32'h0000_0002);
// FSM races through: HEADER -> RANGE -> DOPPLER -> DETECT -> FOOTER -> IDLE
// All pending flags consumed proves SEND_DETECT was entered.
wait_for_state(S_IDLE, 200);
#1;
check(uut.cfar_data_pending === 1'b0,
"Starting in SEND_DETECTION_DATA");
// Verify the full packet completed with cfar data consumed
"cfar_data_pending cleared after packet");
check(uut.current_state === S_IDLE &&
uut.doppler_data_pending === 1'b0 &&
uut.cfar_data_pending === 1'b0,
"CFAR detection sent, FSM advanced past SEND_DETECTION_DATA");
"CFAR detection sent, all pending flags cleared");
// ════════════════════════════════════════════════════════
// TEST GROUP 6: Footer check
//
// Strategy: drive packet with ft601_txe=0 all the way through.
// The SEND_FOOTER state is only active for 1 cycle, but we can
// poll the state machine at each ft601_clk_in edge to observe
// it. We use a monitor-style approach: run the packet and
// capture what ft601_data_out contains when we see SEND_FOOTER.
// TEST GROUP 6: Footer retained after packet
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 6: Footer Check ---");
$display("\n--- Test Group 6: Footer Retention ---");
apply_reset;
ft601_txe = 0;
// Drive packet through range data
@(posedge clk);
cfar_detection = 1'b1;
@(posedge clk);
preload_pending_data;
assert_range_valid(32'hFACE_FEED);
wait_for_state(S_SEND_DOPPLER, 100);
// Feed doppler data (need 4 pulses)
pulse_doppler_once(16'h1111, 16'h2222);
pulse_doppler_once(16'h1111, 16'h2222);
pulse_doppler_once(16'h1111, 16'h2222);
pulse_doppler_once(16'h1111, 16'h2222);
wait_for_state(S_SEND_DETECT, 100);
// Feed cfar data, but keep ft601_txe=0 so it flows through
pulse_cfar_once(1'b1);
// Now the FSM should pass through SEND_FOOTER quickly.
// Use wait_for_state to reach SEND_FOOTER, or it may already
// be at WAIT_ACK/IDLE. Let's catch WAIT_ACK or IDLE.
// The footer values are latched into registers, so we can
// verify them even after the state transitions.
// Key verification: the FOOTER constant (0x55) must have been
// driven. We check this by looking at the constant definition.
// Since we can't easily freeze the FSM at SEND_FOOTER without
// also stalling SEND_DETECTION_DATA (both check ft601_txe),
// we verify the footer indirectly:
// 1. The packet completed (reached IDLE/WAIT_ACK)
// 2. ft601_data_out last held 0x55 during SEND_FOOTER
wait_for_state(S_IDLE, 100);
#1;
// If we reached IDLE, the full sequence ran including footer
check(uut.current_state === S_IDLE,
"Full packet incl. footer completed, back in IDLE");
// The registered ft601_data_out should still hold 0x55 from
// SEND_FOOTER (WAIT_ACK and IDLE don't overwrite ft601_data_out).
// Actually, looking at the DUT: WAIT_ACK only sets wr_n=1 and
// data_oe=0, it doesn't change ft601_data_out. So it retains 0x55.
check(uut.ft601_data_out[7:0] === 8'h55,
"ft601_data_out retains footer 0x55 after packet");
// The last word driven was word 2 which contains footer 0x55.
// WAIT_ACK and IDLE don't overwrite ft601_data_out, so it retains
// the last driven value.
check(uut.ft601_data_out[15:8] === 8'h55,
"ft601_data_out retains footer 0x55 in word 2 position");
// Verify WAIT_ACK behavior by doing another packet and catching it
// Verify WAIT_ACK → IDLE transition
apply_reset;
ft601_txe = 0;
preload_pending_data;
assert_range_valid(32'h1234_5678);
wait_for_state(S_SEND_DOPPLER, 100);
pulse_doppler_once(16'hABCD, 16'hEF01);
pulse_doppler_once(16'hABCD, 16'hEF01);
pulse_doppler_once(16'hABCD, 16'hEF01);
pulse_doppler_once(16'hABCD, 16'hEF01);
wait_for_state(S_SEND_DETECT, 100);
pulse_cfar_once(1'b0);
// WAIT_ACK lasts exactly 1 ft601_clk_in cycle then goes IDLE.
// Poll for IDLE (which means WAIT_ACK already happened).
wait_for_state(S_IDLE, 100);
#1;
check(uut.current_state === S_IDLE,
"Returned to IDLE after WAIT_ACK");
check(ft601_wr_n === 1'b1,
"ft601_wr_n deasserted in IDLE (was deasserted in WAIT_ACK)");
"ft601_wr_n deasserted in IDLE");
check(uut.ft601_data_oe === 1'b0,
"Data bus released in IDLE (was released in WAIT_ACK)");
"Data bus released in IDLE");
// ════════════════════════════════════════════════════════
// TEST GROUP 7: Full packet sequence (end-to-end)
@@ -646,23 +641,24 @@ module tb_usb_data_interface;
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 8: FIFO Backpressure ---");
apply_reset;
ft601_txe = 1;
ft601_txe = 1; // FIFO full — stall
preload_pending_data;
assert_range_valid(32'hBBBB_CCCC);
wait_for_state(S_SEND_HEADER, 50);
wait_for_state(S_SEND_DATA_WORD, 50);
repeat (10) @(posedge ft601_clk_in); #1;
check(uut.current_state === S_SEND_HEADER,
"Stalled in SEND_HEADER when ft601_txe=1 (FIFO full)");
check(uut.current_state === S_SEND_DATA_WORD,
"Stalled in SEND_DATA_WORD when ft601_txe=1 (FIFO full)");
check(ft601_wr_n === 1'b1,
"ft601_wr_n not asserted during backpressure stall");
ft601_txe = 0;
repeat (2) @(posedge ft601_clk_in); #1;
repeat (6) @(posedge ft601_clk_in); #1;
check(uut.current_state !== S_SEND_HEADER,
"Resumed from SEND_HEADER after backpressure released");
check(uut.current_state === S_IDLE || uut.current_state === S_WAIT_ACK,
"Resumed and completed after backpressure released");
// ════════════════════════════════════════════════════════
// TEST GROUP 9: Clock divider
@@ -705,13 +701,6 @@ module tb_usb_data_interface;
ft601_txe = 0;
preload_pending_data;
assert_range_valid(32'h1111_2222);
wait_for_state(S_SEND_DOPPLER, 100);
pulse_doppler_once(16'h3333, 16'h4444);
pulse_doppler_once(16'h3333, 16'h4444);
pulse_doppler_once(16'h3333, 16'h4444);
pulse_doppler_once(16'h3333, 16'h4444);
wait_for_state(S_SEND_DETECT, 100);
pulse_cfar_once(1'b0);
wait_for_state(S_WAIT_ACK, 50);
#1;
@@ -805,7 +794,7 @@ module tb_usb_data_interface;
// Start a write packet
preload_pending_data;
assert_range_valid(32'hFACE_FEED);
wait_for_state(S_SEND_HEADER, 50);
wait_for_state(S_SEND_DATA_WORD, 50);
@(posedge ft601_clk_in); #1;
// While write FSM is active, assert RXF=0 (host has data)
@@ -818,13 +807,6 @@ module tb_usb_data_interface;
// Deassert RXF, complete the write packet
ft601_rxf = 1;
wait_for_state(S_SEND_DOPPLER, 100);
pulse_doppler_once(16'hAAAA, 16'hBBBB);
pulse_doppler_once(16'hAAAA, 16'hBBBB);
pulse_doppler_once(16'hAAAA, 16'hBBBB);
pulse_doppler_once(16'hAAAA, 16'hBBBB);
wait_for_state(S_SEND_DETECT, 100);
pulse_cfar_once(1'b1);
wait_for_state(S_IDLE, 100);
@(posedge ft601_clk_in); #1;
@@ -841,32 +823,42 @@ module tb_usb_data_interface;
// ════════════════════════════════════════════════════════
// TEST GROUP 15: Stream Control Gating (Gap 2)
// Verify that disabling individual streams causes the write
// FSM to skip those data phases.
// FSM to zero those fields in the packed words.
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 15: Stream Control Gating (Gap 2) ---");
// 15a: Disable doppler stream (stream_control = 3'b101 = range + cfar only)
apply_reset;
ft601_txe = 0;
ft601_txe = 1; // Stall to inspect packed words
stream_control = 3'b101; // range + cfar, no doppler
// Wait for CDC propagation (2-stage sync)
repeat (6) @(posedge ft601_clk_in);
// Preload cfar pending so the FSM enters the SEND_DETECT data path
// (without it, SEND_DETECT skips immediately on !cfar_data_pending).
preload_cfar_pending;
// Drive range valid — triggers write FSM
assert_range_valid(32'hAA11_BB22);
// FSM: IDLE -> SEND_HEADER -> SEND_RANGE (doppler disabled) -> SEND_DETECT -> FOOTER
// The FSM races through SEND_DETECT in 1 cycle (cfar_data_pending is consumed).
// Verify the packet completed correctly (doppler was skipped).
wait_for_state(S_IDLE, 200);
#1;
// Reaching IDLE proves: HEADER -> RANGE -> (skip DOPPLER) -> DETECT -> FOOTER -> ACK -> IDLE.
// cfar_data_pending consumed confirms SEND_DETECT was entered.
check(uut.current_state === S_IDLE && uut.cfar_data_pending === 1'b0,
"Stream gate: reached SEND_DETECT (range sent, doppler skipped)");
@(posedge clk);
doppler_real = 16'hAAAA;
doppler_imag = 16'hBBBB;
cfar_detection = 1'b1;
@(posedge clk);
preload_cfar_pending;
assert_range_valid(32'hAA11_BB22);
wait_for_state(S_SEND_DATA_WORD, 200);
repeat (2) @(posedge ft601_clk_in); #1;
// With doppler disabled, doppler fields in words 1 and 2 should be zero
// Word 1: {range[7:0], 0x00, 0x00, 0x00} (doppler zeroed)
check(uut.data_pkt_word1[23:0] === 24'h000000,
"Stream gate: doppler bytes zeroed in word 1 when disabled");
// Word 2 byte 3 (dop_im_lo) should also be zero
check(uut.data_pkt_word2[31:24] === 8'h00,
"Stream gate: dop_im_lo zeroed in word 2 when disabled");
// Let it complete
ft601_txe = 0;
wait_for_state(S_IDLE, 100);
#1;
check(uut.current_state === S_IDLE,
"Stream gate: packet completed without doppler");
@@ -951,28 +943,6 @@ module tb_usb_data_interface;
"Status readback: returned to IDLE after 8-word response");
// Verify the status snapshot was captured correctly.
// status_words[0] = {0xFF, 3'b000, mode[1:0], 5'b0, stream_ctrl[2:0], cfar_threshold[15:0]}
// = {8'hFF, 3'b000, 2'b01, 5'b00000, 3'b101, 16'hABCD}
// = 0xFF_09_05_ABCD... let's compute:
// Byte 3: 0xFF = 8'hFF
// Byte 2: {3'b000, 2'b01} = 5'b00001 + 3 high bits of next field...
// Actually the packing is: {8'hFF, 3'b000, status_radar_mode[1:0], 5'b00000, status_stream_ctrl[2:0], status_cfar_threshold[15:0]}
// = {8'hFF, 3'b000, 2'b01, 5'b00000, 3'b101, 16'hABCD}
// = 8'hFF, 5'b00001, 8'b00000101, 16'hABCD
// = FF_09_05_ABCD? Let me compute carefully:
// Bits [31:24] = 8'hFF = 0xFF
// Bits [23:21] = 3'b000
// Bits [20:19] = 2'b01 (mode)
// Bits [18:14] = 5'b00000
// Bits [13:11] = 3'b101 (stream_ctrl)
// Bits [10:0] = ... wait, cfar_threshold is 16 bits → [15:0]
// Total bits = 8+3+2+5+3+16 = 37 bits — won't fit in 32!
// Re-reading the RTL: the packing at line 241 is:
// {8'hFF, 3'b000, status_radar_mode, 5'b00000, status_stream_ctrl, status_cfar_threshold}
// = 8 + 3 + 2 + 5 + 3 + 16 = 37 bits
// This would be truncated to 32 bits. Let me re-read the actual RTL to check.
// For now, just verify status_words[1] (word index 1 in the packet = idx 2 in FSM)
// status_words[1] = {status_long_chirp, status_long_listen} = {16'd3000, 16'd13700}
check(uut.status_words[1] === {16'd3000, 16'd13700},
"Status readback: word 1 = {long_chirp, long_listen}");
check(uut.status_words[2] === {16'd17540, 16'd50},
9_Firmware/9_2_FPGA/usb_data_interface.v
+187 -130
View File
@@ -1,3 +1,17 @@
/**
* usb_data_interface.v
*
* FT601 USB 3.0 SuperSpeed FIFO Interface (32-bit bus, 100 MHz ft601_clk).
* Used on the 200T premium dev board. Production 50T board uses
* usb_data_interface_ft2232h.v (FT2232H, 8-bit, 60 MHz) instead.
*
* USB disconnect recovery:
* A clock-activity watchdog in the clk domain detects when ft601_clk_in
* stops (USB cable unplugged). After ~0.65 ms of silence (65536 system
* clocks) it asserts ft601_clk_lost, which is OR'd into the FT-domain
* reset so FSMs and FIFOs return to a clean state. When ft601_clk_in
* resumes, a 2-stage reset synchronizer deasserts the reset cleanly.
*/
module usb_data_interface (
input wire clk, // Main clock (100MHz recommended)
input wire reset_n,
@@ -15,13 +29,18 @@ module usb_data_interface (
// FT601 Interface (Slave FIFO mode)
// Data bus
inout wire [31:0] ft601_data, // 32-bit bidirectional data bus
output reg [3:0] ft601_be, // Byte enable (4 lanes for 32-bit mode)
output reg [3:0] ft601_be, // Byte enable (active-HIGH per DS_FT600Q-FT601Q Table 3.2)
// Control signals
output reg ft601_txe_n, // Transmit enable (active low)
output reg ft601_rxf_n, // Receive enable (active low)
input wire ft601_txe, // TXE: Transmit FIFO Not Full (high = space available to write)
input wire ft601_rxf, // RXF: Receive FIFO Not Empty (high = data available to read)
// VESTIGIAL OUTPUTS — kept for 200T board port compatibility.
// On the 200T, these are constrained to physical pins G21 (TXE) and
// G22 (RXF) in xc7a200t_fbg484.xdc. Removing them from the RTL would
// break the 200T build. They are reset to 1 and never driven; the
// actual FT601 flow-control inputs are ft601_txe and ft601_rxf below.
output reg ft601_txe_n, // VESTIGIAL: unused output, always 1
output reg ft601_rxf_n, // VESTIGIAL: unused output, always 1
input wire ft601_txe, // TXE: Transmit FIFO Not Full (active-low: 0 = space available)
input wire ft601_rxf, // RXF: Receive FIFO Not Empty (active-low: 0 = data available)
output reg ft601_wr_n, // Write strobe (active low)
output reg ft601_rd_n, // Read strobe (active low)
output reg ft601_oe_n, // Output enable (active low)
@@ -97,21 +116,26 @@ localparam FT601_BURST_SIZE = 512; // Max burst size in bytes
// ============================================================================
// WRITE FSM State definitions (Verilog-2001 compatible)
// ============================================================================
localparam [2:0] IDLE = 3'd0,
SEND_HEADER = 3'd1,
SEND_RANGE_DATA = 3'd2,
SEND_DOPPLER_DATA = 3'd3,
SEND_DETECTION_DATA = 3'd4,
SEND_FOOTER = 3'd5,
WAIT_ACK = 3'd6,
SEND_STATUS = 3'd7; // Gap 2: status readback
// Rewritten: data packet is now 3 x 32-bit writes (11 payload bytes + 1 pad).
// Word 0: {HEADER, range[31:24], range[23:16], range[15:8]} BE=1111
// Word 1: {range[7:0], doppler_real[15:8], doppler_real[7:0], doppler_imag[15:8]} BE=1111
// Word 2: {doppler_imag[7:0], detection, FOOTER, 8'h00} BE=1110
localparam [3:0] IDLE = 4'd0,
SEND_DATA_WORD = 4'd1,
SEND_STATUS = 4'd2,
WAIT_ACK = 4'd3;
reg [2:0] current_state;
reg [7:0] byte_counter;
reg [31:0] data_buffer;
reg [3:0] current_state;
reg [1:0] data_word_idx; // 0..2 for 3-word data packet
reg [31:0] ft601_data_out;
reg ft601_data_oe; // Output enable for bidirectional data bus
// Pre-packed data words (registered snapshot of CDC'd data)
reg [31:0] data_pkt_word0;
reg [31:0] data_pkt_word1;
reg [31:0] data_pkt_word2;
reg [3:0] data_pkt_be2; // BE for last word (BE=1110 since byte 3 is pad)
// ============================================================================
// READ FSM State definitions (Gap 4: USB Read Path)
// ============================================================================
@@ -184,6 +208,67 @@ always @(posedge clk or negedge reset_n) begin
end
end
// ============================================================================
// CLOCK-ACTIVITY WATCHDOG (clk domain)
// ============================================================================
// Detects when ft601_clk_in stops (USB cable unplugged). A toggle register
// in the ft601_clk domain flips every edge. The clk domain synchronizes it
// and checks for transitions. If no transition is seen for 2^16 = 65536
// clk cycles (~0.65 ms at 100 MHz), ft601_clk_lost asserts.
// Toggle register: flips every ft601_clk edge (ft601_clk domain)
reg ft601_heartbeat;
always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
if (!ft601_reset_n)
ft601_heartbeat <= 1'b0;
else
ft601_heartbeat <= ~ft601_heartbeat;
end
// Synchronize heartbeat into clk domain (2-stage)
(* ASYNC_REG = "TRUE" *) reg [1:0] ft601_hb_sync;
reg ft601_hb_prev;
reg [15:0] ft601_clk_timeout;
reg ft601_clk_lost;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
ft601_hb_sync <= 2'b00;
ft601_hb_prev <= 1'b0;
ft601_clk_timeout <= 16'd0;
ft601_clk_lost <= 1'b0;
end else begin
ft601_hb_sync <= {ft601_hb_sync[0], ft601_heartbeat};
ft601_hb_prev <= ft601_hb_sync[1];
if (ft601_hb_sync[1] != ft601_hb_prev) begin
// ft601_clk is alive — reset counter, clear lost flag
ft601_clk_timeout <= 16'd0;
ft601_clk_lost <= 1'b0;
end else if (!ft601_clk_lost) begin
if (ft601_clk_timeout == 16'hFFFF)
ft601_clk_lost <= 1'b1;
else
ft601_clk_timeout <= ft601_clk_timeout + 16'd1;
end
end
end
// Effective FT601-domain reset: asserted by global reset OR clock loss.
// Deassertion synchronized to ft601_clk via 2-stage sync to avoid
// metastability on the recovery edge.
(* ASYNC_REG = "TRUE" *) reg [1:0] ft601_reset_sync;
wire ft601_reset_raw_n = ft601_reset_n & ~ft601_clk_lost;
always @(posedge ft601_clk_in or negedge ft601_reset_raw_n) begin
if (!ft601_reset_raw_n)
ft601_reset_sync <= 2'b00;
else
ft601_reset_sync <= {ft601_reset_sync[0], 1'b1};
end
wire ft601_effective_reset_n = ft601_reset_sync[1];
// FT601-domain captured data (sampled from holding regs on sync'd edge)
reg [31:0] range_profile_cap;
reg [15:0] doppler_real_cap;
@@ -197,6 +282,18 @@ reg cfar_detection_cap;
reg doppler_data_pending;
reg cfar_data_pending;
// 1-cycle delayed range trigger. range_valid_ft fires on the same clock
// edge that range_profile_cap is captured (non-blocking). If the FSM
// reads range_profile_cap on that same edge it sees the STALE value.
// Delaying the trigger by one cycle guarantees the capture register has
// settled before the FSM packs the data words.
reg range_data_ready;
// Frame sync: sample counter (ft601_clk domain, wraps at NUM_CELLS)
// Bit 7 of detection byte is set when sample_counter == 0 (frame start).
localparam [11:0] NUM_CELLS = 12'd2048; // 64 range x 32 doppler
reg [11:0] sample_counter;
// Gap 2: CDC for stream_control (clk_100m -> ft601_clk_in)
// stream_control changes infrequently (only on host USB command), so
// per-bit 2-stage synchronizers are sufficient. No Gray coding needed
@@ -228,8 +325,8 @@ wire range_valid_ft;
wire doppler_valid_ft;
wire cfar_valid_ft;
always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
if (!ft601_reset_n) begin
always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
if (!ft601_effective_reset_n) begin
range_valid_sync <= 2'b00;
doppler_valid_sync <= 2'b00;
cfar_valid_sync <= 2'b00;
@@ -240,6 +337,7 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
doppler_real_cap <= 16'd0;
doppler_imag_cap <= 16'd0;
cfar_detection_cap <= 1'b0;
range_data_ready <= 1'b0;
// Fix #5: Default to range-only on reset (prevents write FSM deadlock)
stream_ctrl_sync_0 <= 3'b001;
stream_ctrl_sync_1 <= 3'b001;
@@ -276,7 +374,7 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
// Word 4: AGC metrics + range_mode
status_words[4] <= {status_agc_current_gain, // [31:28]
status_agc_peak_magnitude, // [27:20]
status_agc_saturation_count, // [19:12]
status_agc_saturation_count, // [19:12] 8-bit saturation count
status_agc_enable, // [11]
9'd0, // [10:2] reserved
status_range_mode}; // [1:0]
@@ -302,6 +400,10 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
if (cfar_valid_sync[1] && !cfar_valid_sync_d) begin
cfar_detection_cap <= cfar_detection_hold;
end
// 1-cycle delayed trigger: ensures range_profile_cap has settled
// before the FSM reads it for word packing.
range_data_ready <= range_valid_ft;
end
end
@@ -314,11 +416,11 @@ assign cfar_valid_ft = cfar_valid_sync[1] && !cfar_valid_sync_d;
// FT601 data bus direction control
assign ft601_data = ft601_data_oe ? ft601_data_out : 32'hzzzz_zzzz;
always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
if (!ft601_reset_n) begin
always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
if (!ft601_effective_reset_n) begin
current_state <= IDLE;
read_state <= RD_IDLE;
byte_counter <= 0;
data_word_idx <= 2'd0;
ft601_data_out <= 0;
ft601_data_oe <= 0;
ft601_be <= 4'b1111; // All bytes enabled for 32-bit mode
@@ -336,6 +438,11 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
cmd_value <= 16'd0;
doppler_data_pending <= 1'b0;
cfar_data_pending <= 1'b0;
data_pkt_word0 <= 32'd0;
data_pkt_word1 <= 32'd0;
data_pkt_word2 <= 32'd0;
data_pkt_be2 <= 4'b1110;
sample_counter <= 12'd0;
// NOTE: ft601_clk_out is driven by the clk-domain always block below.
// Do NOT assign it here (ft601_clk_in domain) — causes multi-driven net.
end else begin
@@ -424,124 +531,66 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
current_state <= SEND_STATUS;
status_word_idx <= 3'd0;
end
// Trigger write FSM on range_valid edge (primary data source).
// Doppler/cfar data_pending flags are checked inside
// SEND_DOPPLER_DATA and SEND_DETECTION_DATA to skip or send.
// Do NOT trigger on pending flags alone — they're sticky and
// would cause repeated packet starts without new range data.
else if (range_valid_ft && stream_range_en) begin
// Trigger on range_data_ready (1 cycle after range_valid_ft)
// so that range_profile_cap has settled from the CDC block.
// Gate on pending flags: only send when all enabled
// streams have fresh data (avoids stale doppler/CFAR)
else if (range_data_ready && stream_range_en
&& (!stream_doppler_en || doppler_data_pending)
&& (!stream_cfar_en || cfar_data_pending)) begin
// Don't start write if a read is about to begin
if (ft601_rxf) begin // rxf=1 means no host data pending
current_state <= SEND_HEADER;
byte_counter <= 0;
// Pack 11-byte data packet into 3 x 32-bit words
// Doppler fields zeroed when stream disabled
// CFAR field zeroed when stream disabled
data_pkt_word0 <= {HEADER,
range_profile_cap[31:24],
range_profile_cap[23:16],
range_profile_cap[15:8]};
data_pkt_word1 <= {range_profile_cap[7:0],
stream_doppler_en ? doppler_real_cap[15:8] : 8'd0,
stream_doppler_en ? doppler_real_cap[7:0] : 8'd0,
stream_doppler_en ? doppler_imag_cap[15:8] : 8'd0};
data_pkt_word2 <= {stream_doppler_en ? doppler_imag_cap[7:0] : 8'd0,
stream_cfar_en
? {(sample_counter == 12'd0), 6'b0, cfar_detection_cap}
: {(sample_counter == 12'd0), 7'd0},
FOOTER,
8'h00}; // pad byte
data_pkt_be2 <= 4'b1110; // 3 valid bytes + 1 pad
data_word_idx <= 2'd0;
current_state <= SEND_DATA_WORD;
end
end
end
SEND_HEADER: begin
if (!ft601_txe) begin // FT601 TX FIFO not empty
ft601_data_oe <= 1;
ft601_data_out <= {24'b0, HEADER};
ft601_be <= 4'b0001; // Only lower byte valid
ft601_wr_n <= 0; // Assert write strobe
// Gap 2: skip to first enabled stream
if (stream_range_en)
current_state <= SEND_RANGE_DATA;
else if (stream_doppler_en)
current_state <= SEND_DOPPLER_DATA;
else if (stream_cfar_en)
current_state <= SEND_DETECTION_DATA;
else
current_state <= SEND_FOOTER; // No streams — send footer only
end
end
SEND_RANGE_DATA: begin
SEND_DATA_WORD: begin
if (!ft601_txe) begin
ft601_data_oe <= 1;
ft601_be <= 4'b1111; // All bytes valid for 32-bit word
case (byte_counter)
0: ft601_data_out <= range_profile_cap;
1: ft601_data_out <= {range_profile_cap[23:0], 8'h00};
2: ft601_data_out <= {range_profile_cap[15:0], 16'h0000};
3: ft601_data_out <= {range_profile_cap[7:0], 24'h000000};
ft601_wr_n <= 0;
case (data_word_idx)
2'd0: begin
ft601_data_out <= data_pkt_word0;
ft601_be <= 4'b1111;
end
2'd1: begin
ft601_data_out <= data_pkt_word1;
ft601_be <= 4'b1111;
end
2'd2: begin
ft601_data_out <= data_pkt_word2;
ft601_be <= data_pkt_be2;
end
default: ;
endcase
ft601_wr_n <= 0;
if (byte_counter == 3) begin
byte_counter <= 0;
// Gap 2: skip disabled streams
if (stream_doppler_en)
current_state <= SEND_DOPPLER_DATA;
else if (stream_cfar_en)
current_state <= SEND_DETECTION_DATA;
else
current_state <= SEND_FOOTER;
if (data_word_idx == 2'd2) begin
data_word_idx <= 2'd0;
current_state <= WAIT_ACK;
end else begin
byte_counter <= byte_counter + 1;
data_word_idx <= data_word_idx + 2'd1;
end
end
end
SEND_DOPPLER_DATA: begin
if (!ft601_txe && doppler_data_pending) begin
ft601_data_oe <= 1;
ft601_be <= 4'b1111;
case (byte_counter)
0: ft601_data_out <= {doppler_real_cap, doppler_imag_cap};
1: ft601_data_out <= {doppler_imag_cap, doppler_real_cap[15:8], 8'h00};
2: ft601_data_out <= {doppler_real_cap[7:0], doppler_imag_cap[15:8], 16'h0000};
3: ft601_data_out <= {doppler_imag_cap[7:0], 24'h000000};
endcase
ft601_wr_n <= 0;
if (byte_counter == 3) begin
byte_counter <= 0;
doppler_data_pending <= 1'b0;
if (stream_cfar_en)
current_state <= SEND_DETECTION_DATA;
else
current_state <= SEND_FOOTER;
end else begin
byte_counter <= byte_counter + 1;
end
end else if (!doppler_data_pending) begin
// No doppler data available yet — skip to next stream
byte_counter <= 0;
if (stream_cfar_en)
current_state <= SEND_DETECTION_DATA;
else
current_state <= SEND_FOOTER;
end
end
SEND_DETECTION_DATA: begin
if (!ft601_txe && cfar_data_pending) begin
ft601_data_oe <= 1;
ft601_be <= 4'b0001;
ft601_data_out <= {24'b0, 7'b0, cfar_detection_cap};
ft601_wr_n <= 0;
cfar_data_pending <= 1'b0;
current_state <= SEND_FOOTER;
end else if (!cfar_data_pending) begin
// No CFAR data available yet — skip to footer
current_state <= SEND_FOOTER;
end
end
SEND_FOOTER: begin
if (!ft601_txe) begin
ft601_data_oe <= 1;
ft601_be <= 4'b0001;
ft601_data_out <= {24'b0, FOOTER};
ft601_wr_n <= 0;
current_state <= WAIT_ACK;
end
end
// Gap 2: Status readback — send 6 x 32-bit status words
// Format: HEADER, status_words[0..5], FOOTER
@@ -581,6 +630,14 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
WAIT_ACK: begin
ft601_wr_n <= 1;
ft601_data_oe <= 0; // Release data bus
// Clear pending flags — data consumed
doppler_data_pending <= 1'b0;
cfar_data_pending <= 1'b0;
// Advance frame sync counter
if (sample_counter == NUM_CELLS - 12'd1)
sample_counter <= 12'd0;
else
sample_counter <= sample_counter + 12'd1;
current_state <= IDLE;
end
endcase
@@ -613,8 +670,8 @@ ODDR #(
`else
// Simulation: behavioral clock forwarding
reg ft601_clk_out_sim;
always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
if (!ft601_reset_n)
always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
if (!ft601_effective_reset_n)
ft601_clk_out_sim <= 1'b0;
else
ft601_clk_out_sim <= 1'b1;
9_Firmware/9_2_FPGA/usb_data_interface_ft2232h.v
+131 -19
View File
@@ -36,6 +36,13 @@
* Clock domains:
* clk = 100 MHz system clock (radar data domain)
* ft_clk = 60 MHz from FT2232H CLKOUT (USB FIFO domain)
*
* USB disconnect recovery:
* A clock-activity watchdog in the clk domain detects when ft_clk stops
* (USB cable unplugged). After ~0.65 ms of silence (65536 system clocks)
* it asserts ft_clk_lost, which is OR'd into the FT-domain reset so
* FSMs and FIFOs return to a clean state. When ft_clk resumes, a 2-stage
* reset synchronizer deasserts the reset cleanly in the ft_clk domain.
*/
module usb_data_interface_ft2232h (
@@ -59,7 +66,9 @@ module usb_data_interface_ft2232h (
output reg ft_rd_n, // Read strobe (active low)
output reg ft_wr_n, // Write strobe (active low)
output reg ft_oe_n, // Output enable (active low) — bus direction
output reg ft_siwu, // Send Immediate / WakeUp
output reg ft_siwu, // Send Immediate / WakeUp — UNUSED: held low.
// SIWU could flush the TX FIFO for lower latency
// but is not needed at current data rates. Deferred.
// Clock from FT2232H (directly used — no ODDR forwarding needed)
input wire ft_clk, // 60 MHz from FT2232H CLKOUT
@@ -134,6 +143,7 @@ localparam [2:0] RD_IDLE = 3'd0,
reg [2:0] rd_state;
reg [1:0] rd_byte_cnt; // 0..3 for 4-byte command word
reg [31:0] rd_shift_reg; // Shift register to assemble 4-byte command
reg rd_cmd_complete; // Set when all 4 bytes received (distinguishes from abort)
// ============================================================================
// DATA BUS DIRECTION CONTROL
@@ -192,6 +202,70 @@ always @(posedge clk or negedge reset_n) begin
end
end
// ============================================================================
// CLOCK-ACTIVITY WATCHDOG (clk domain)
// ============================================================================
// Detects when ft_clk stops (USB cable unplugged). A toggle register in the
// ft_clk domain flips every ft_clk edge. The clk domain synchronizes it and
// checks for transitions. If no transition is seen for 2^16 = 65536 clk
// cycles (~0.65 ms at 100 MHz), ft_clk_lost asserts.
//
// ft_clk_lost feeds into the effective reset for the ft_clk domain so that
// FSMs and capture registers return to a clean state automatically.
// Toggle register: flips every ft_clk edge (ft_clk domain)
reg ft_heartbeat;
always @(posedge ft_clk or negedge ft_reset_n) begin
if (!ft_reset_n)
ft_heartbeat <= 1'b0;
else
ft_heartbeat <= ~ft_heartbeat;
end
// Synchronize heartbeat into clk domain (2-stage)
(* ASYNC_REG = "TRUE" *) reg [1:0] ft_hb_sync;
reg ft_hb_prev;
reg [15:0] ft_clk_timeout;
reg ft_clk_lost;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
ft_hb_sync <= 2'b00;
ft_hb_prev <= 1'b0;
ft_clk_timeout <= 16'd0;
ft_clk_lost <= 1'b0;
end else begin
ft_hb_sync <= {ft_hb_sync[0], ft_heartbeat};
ft_hb_prev <= ft_hb_sync[1];
if (ft_hb_sync[1] != ft_hb_prev) begin
// ft_clk is alive — reset counter, clear lost flag
ft_clk_timeout <= 16'd0;
ft_clk_lost <= 1'b0;
end else if (!ft_clk_lost) begin
if (ft_clk_timeout == 16'hFFFF)
ft_clk_lost <= 1'b1;
else
ft_clk_timeout <= ft_clk_timeout + 16'd1;
end
end
end
// Effective FT-domain reset: asserted by global reset OR clock loss.
// Deassertion synchronized to ft_clk via 2-stage sync to avoid
// metastability on the recovery edge.
(* ASYNC_REG = "TRUE" *) reg [1:0] ft_reset_sync;
wire ft_reset_raw_n = ft_reset_n & ~ft_clk_lost;
always @(posedge ft_clk or negedge ft_reset_raw_n) begin
if (!ft_reset_raw_n)
ft_reset_sync <= 2'b00;
else
ft_reset_sync <= {ft_reset_sync[0], 1'b1};
end
wire ft_effective_reset_n = ft_reset_sync[1];
// --- 3-stage synchronizers (ft_clk domain) ---
// 3 stages for better MTBF at 60 MHz
@@ -228,12 +302,25 @@ reg cfar_detection_cap;
reg doppler_data_pending;
reg cfar_data_pending;
// 1-cycle delayed range trigger. range_valid_ft fires on the same clock
// edge that range_profile_cap is captured (non-blocking). If the FSM
// reads range_profile_cap on that same edge it sees the STALE value.
// Delaying the trigger by one cycle guarantees the capture register has
// settled before the byte mux reads it.
reg range_data_ready;
// Frame sync: sample counter (ft_clk domain, wraps at NUM_CELLS)
// Bit 7 of detection byte is set when sample_counter == 0 (frame start).
// This allows the Python host to resynchronize without a protocol change.
localparam [11:0] NUM_CELLS = 12'd2048; // 64 range x 32 doppler
reg [11:0] sample_counter;
// Status snapshot (ft_clk domain)
reg [31:0] status_words [0:5];
integer si; // status_words loop index
always @(posedge ft_clk or negedge ft_reset_n) begin
if (!ft_reset_n) begin
always @(posedge ft_clk or negedge ft_effective_reset_n) begin
if (!ft_effective_reset_n) begin
range_toggle_sync <= 3'b000;
doppler_toggle_sync <= 3'b000;
cfar_toggle_sync <= 3'b000;
@@ -246,6 +333,7 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
doppler_real_cap <= 16'd0;
doppler_imag_cap <= 16'd0;
cfar_detection_cap <= 1'b0;
range_data_ready <= 1'b0;
// Default to range-only on reset (prevents write FSM deadlock)
stream_ctrl_sync_0 <= 3'b001;
stream_ctrl_sync_1 <= 3'b001;
@@ -279,6 +367,10 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
if (cfar_valid_ft)
cfar_detection_cap <= cfar_detection_hold;
// 1-cycle delayed trigger: ensures range_profile_cap has settled
// before the FSM reads it via the byte mux.
range_data_ready <= range_valid_ft;
// Status snapshot on request
if (status_req_ft) begin
// Word 0: {0xFF[31:24], mode[23:22], stream[21:19], 3'b000[18:16], threshold[15:0]}
@@ -315,11 +407,16 @@ always @(*) begin
5'd2: data_pkt_byte = range_profile_cap[23:16];
5'd3: data_pkt_byte = range_profile_cap[15:8];
5'd4: data_pkt_byte = range_profile_cap[7:0]; // range LSB
5'd5: data_pkt_byte = doppler_real_cap[15:8]; // doppler_real MSB
5'd6: data_pkt_byte = doppler_real_cap[7:0]; // doppler_real LSB
5'd7: data_pkt_byte = doppler_imag_cap[15:8]; // doppler_imag MSB
5'd8: data_pkt_byte = doppler_imag_cap[7:0]; // doppler_imag LSB
5'd9: data_pkt_byte = {7'b0, cfar_detection_cap}; // detection
// Doppler fields: zero when stream_doppler_en is off
5'd5: data_pkt_byte = stream_doppler_en ? doppler_real_cap[15:8] : 8'd0;
5'd6: data_pkt_byte = stream_doppler_en ? doppler_real_cap[7:0] : 8'd0;
5'd7: data_pkt_byte = stream_doppler_en ? doppler_imag_cap[15:8] : 8'd0;
5'd8: data_pkt_byte = stream_doppler_en ? doppler_imag_cap[7:0] : 8'd0;
// Detection field: zero when stream_cfar_en is off
// Bit 7 = frame_start flag (sample_counter == 0), bit 0 = cfar_detection
5'd9: data_pkt_byte = stream_cfar_en
? {(sample_counter == 12'd0), 6'b0, cfar_detection_cap}
: {(sample_counter == 12'd0), 7'd0};
5'd10: data_pkt_byte = FOOTER;
default: data_pkt_byte = 8'h00;
endcase
@@ -376,12 +473,13 @@ end
// Write FSM and Read FSM share the bus. Write FSM operates when Read FSM
// is idle. Read FSM takes priority when host has data available.
always @(posedge ft_clk or negedge ft_reset_n) begin
if (!ft_reset_n) begin
always @(posedge ft_clk or negedge ft_effective_reset_n) begin
if (!ft_effective_reset_n) begin
wr_state <= WR_IDLE;
wr_byte_idx <= 5'd0;
rd_state <= RD_IDLE;
rd_byte_cnt <= 2'd0;
rd_cmd_complete <= 1'b0;
rd_shift_reg <= 32'd0;
ft_data_out <= 8'd0;
ft_data_oe <= 1'b0;
@@ -396,6 +494,7 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
cmd_value <= 16'd0;
doppler_data_pending <= 1'b0;
cfar_data_pending <= 1'b0;
sample_counter <= 12'd0;
end else begin
// Default: clear one-shot signals
cmd_valid <= 1'b0;
@@ -437,17 +536,19 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
rd_shift_reg <= {rd_shift_reg[23:0], ft_data};
if (rd_byte_cnt == 2'd3) begin
// All 4 bytes received
ft_rd_n <= 1'b1;
rd_byte_cnt <= 2'd0;
rd_state <= RD_DEASSERT;
ft_rd_n <= 1'b1;
rd_byte_cnt <= 2'd0;
rd_cmd_complete <= 1'b1;
rd_state <= RD_DEASSERT;
end else begin
rd_byte_cnt <= rd_byte_cnt + 2'd1;
// Keep reading if more data available
if (ft_rxf_n) begin
// Host ran out of data mid-command — abort
ft_rd_n <= 1'b1;
rd_byte_cnt <= 2'd0;
rd_state <= RD_DEASSERT;
ft_rd_n <= 1'b1;
rd_byte_cnt <= 2'd0;
rd_cmd_complete <= 1'b0;
rd_state <= RD_DEASSERT;
end
end
end
@@ -456,7 +557,8 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
// Deassert OE (1 cycle after RD deasserted)
ft_oe_n <= 1'b1;
// Only process if we received a full 4-byte command
if (rd_byte_cnt == 2'd0) begin
if (rd_cmd_complete) begin
rd_cmd_complete <= 1'b0;
rd_state <= RD_PROCESS;
end else begin
// Incomplete command — discard
@@ -491,8 +593,13 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
wr_state <= WR_STATUS_SEND;
wr_byte_idx <= 5'd0;
end
// Trigger on range_valid edge (primary data trigger)
else if (range_valid_ft && stream_range_en) begin
// Trigger on range_data_ready (1 cycle after range_valid_ft)
// so that range_profile_cap has settled from the CDC block.
// Gate on pending flags: only send when all enabled
// streams have fresh data (avoids stale doppler/CFAR)
else if (range_data_ready && stream_range_en
&& (!stream_doppler_en || doppler_data_pending)
&& (!stream_cfar_en || cfar_data_pending)) begin
if (ft_rxf_n) begin // No host read pending
wr_state <= WR_DATA_SEND;
wr_byte_idx <= 5'd0;
@@ -538,6 +645,11 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
// Clear pending flags — data consumed
doppler_data_pending <= 1'b0;
cfar_data_pending <= 1'b0;
// Advance frame sync counter
if (sample_counter == NUM_CELLS - 12'd1)
sample_counter <= 12'd0;
else
sample_counter <= sample_counter + 12'd1;
wr_state <= WR_IDLE;
end
9_Firmware/9_3_GUI/GUI_V6.py
+6
View File
@@ -1,3 +1,9 @@
# =============================================================================
# DEPRECATED: GUI V6 is superseded by GUI_V65_Tk (tkinter) and V7 (PyQt6).
# This file is retained for reference only. Do not use for new development.
# Removal planned for next major release.
# =============================================================================
import tkinter as tk
from tkinter import ttk, messagebox
import threading
9_Firmware/9_3_GUI/GUI_V65_Tk.py
+48 -20
View File
@@ -59,7 +59,7 @@ except (ModuleNotFoundError, ImportError):
# Import protocol layer (no GUI deps)
from radar_protocol import (
RadarProtocol, FT2232HConnection,
RadarProtocol, FT2232HConnection, FT601Connection,
DataRecorder, RadarAcquisition,
RadarFrame, StatusResponse,
NUM_RANGE_BINS, NUM_DOPPLER_BINS, WATERFALL_DEPTH,
@@ -98,9 +98,10 @@ class DemoTarget:
__slots__ = ("azimuth", "classification", "id", "range_m", "snr", "velocity")
# Physical range grid: 64 bins x ~4.8 m/bin = ~307 m max
_RANGE_PER_BIN: float = (3e8 / (2 * 500e6)) * 16 # ~4.8 m
_MAX_RANGE: float = _RANGE_PER_BIN * NUM_RANGE_BINS # ~307 m
# Physical range grid: 64 bins x ~24 m/bin = ~1536 m max
# Bin spacing = c / (2 * Fs) * decimation, where Fs = 100 MHz DDC output.
_RANGE_PER_BIN: float = (3e8 / (2 * 100e6)) * 16 # ~24 m
_MAX_RANGE: float = _RANGE_PER_BIN * NUM_RANGE_BINS # ~1536 m
def __init__(self, tid: int):
self.id = tid
@@ -187,10 +188,10 @@ class DemoSimulator:
mag = np.zeros((NUM_RANGE_BINS, NUM_DOPPLER_BINS), dtype=np.float64)
det = np.zeros((NUM_RANGE_BINS, NUM_DOPPLER_BINS), dtype=np.uint8)
# Range/Doppler scaling (approximate)
range_per_bin = (3e8 / (2 * 500e6)) * 16 # ~4.8 m/bin
# Range/Doppler scaling: bin spacing = c/(2*Fs)*decimation
range_per_bin = (3e8 / (2 * 100e6)) * 16 # ~24 m/bin
max_range = range_per_bin * NUM_RANGE_BINS
vel_per_bin = 1.484 # m/s per Doppler bin (from WaveformConfig)
vel_per_bin = 5.34 # m/s per Doppler bin (radar_scene.py: lam/(2*16*PRI))
for t in targets:
if t.range_m > max_range or t.range_m < 0:
@@ -385,13 +386,14 @@ class RadarDashboard:
UPDATE_INTERVAL_MS = 100 # 10 Hz display refresh
# Radar parameters used for range-axis scaling.
BANDWIDTH = 500e6 # Hz — chirp bandwidth
SAMPLE_RATE = 100e6 # Hz — DDC output I/Q rate (matched filter input)
C = 3e8 # m/s — speed of light
def __init__(self, root: tk.Tk, connection: FT2232HConnection,
def __init__(self, root: tk.Tk, mock: bool,
recorder: DataRecorder, device_index: int = 0):
self.root = root
self.conn = connection
self._mock = mock
self.conn: FT2232HConnection | FT601Connection | None = None
self.recorder = recorder
self.device_index = device_index
@@ -485,6 +487,16 @@ class RadarDashboard:
style="Accent.TButton")
self.btn_connect.pack(side="right", padx=4)
# USB Interface selector (production FT2232H / premium FT601)
self._usb_iface_var = tk.StringVar(value="FT2232H (Production)")
self.cmb_usb_iface = ttk.Combobox(
top, textvariable=self._usb_iface_var,
values=["FT2232H (Production)", "FT601 (Premium)"],
state="readonly", width=20,
)
self.cmb_usb_iface.pack(side="right", padx=4)
ttk.Label(top, text="USB:", font=("Menlo", 10)).pack(side="right")
self.btn_record = ttk.Button(top, text="Record", command=self._on_record)
self.btn_record.pack(side="right", padx=4)
@@ -515,9 +527,8 @@ class RadarDashboard:
def _build_display_tab(self, parent):
# Compute physical axis limits
range_res = self.C / (2.0 * self.BANDWIDTH) # ~0.3 m per FFT bin
# After decimation 1024→64, each range bin = 16 FFT bins
range_per_bin = range_res * 16
# Bin spacing = c / (2 * Fs_ddc) for matched-filter processing.
range_per_bin = self.C / (2.0 * self.SAMPLE_RATE) * 16 # ~24 m
max_range = range_per_bin * NUM_RANGE_BINS
doppler_bin_lo = 0
@@ -1018,15 +1029,17 @@ class RadarDashboard:
# ------------------------------------------------------------ Actions
def _on_connect(self):
if self.conn.is_open:
if self.conn is not None and self.conn.is_open:
# Disconnect
if self._acq_thread is not None:
self._acq_thread.stop()
self._acq_thread.join(timeout=2)
self._acq_thread = None
self.conn.close()
self.conn = None
self.lbl_status.config(text="DISCONNECTED", foreground=RED)
self.btn_connect.config(text="Connect")
self.cmb_usb_iface.config(state="readonly")
log.info("Disconnected")
return
@@ -1036,6 +1049,16 @@ class RadarDashboard:
if self._replay_active:
self._replay_stop()
# Create connection based on USB Interface selector
iface = self._usb_iface_var.get()
if "FT601" in iface:
self.conn = FT601Connection(mock=self._mock)
else:
self.conn = FT2232HConnection(mock=self._mock)
# Disable interface selector while connecting/connected
self.cmb_usb_iface.config(state="disabled")
# Open connection in a background thread to avoid blocking the GUI
self.lbl_status.config(text="CONNECTING...", foreground=YELLOW)
self.btn_connect.config(state="disabled")
@@ -1062,6 +1085,8 @@ class RadarDashboard:
else:
self.lbl_status.config(text="CONNECT FAILED", foreground=RED)
self.btn_connect.config(text="Connect")
self.cmb_usb_iface.config(state="readonly")
self.conn = None
def _on_record(self):
if self.recorder.recording:
@@ -1110,6 +1135,9 @@ class RadarDashboard:
f"Opcode 0x{opcode:02X} is hardware-only (ignored in replay)"))
return
cmd = RadarProtocol.build_command(opcode, value)
if self.conn is None:
log.warning("No connection — command not sent")
return
ok = self.conn.write(cmd)
log.info(f"CMD 0x{opcode:02X} val={value} ({'OK' if ok else 'FAIL'})")
@@ -1148,7 +1176,7 @@ class RadarDashboard:
if self._replay_active or self._replay_ctrl is not None:
self._replay_stop()
if self._acq_thread is not None:
if self.conn.is_open:
if self.conn is not None and self.conn.is_open:
self._on_connect() # disconnect
else:
# Connection dropped unexpectedly — just clean up the thread
@@ -1547,17 +1575,17 @@ def main():
args = parser.parse_args()
if args.live:
conn = FT2232HConnection(mock=False)
mock = False
mode_str = "LIVE"
else:
conn = FT2232HConnection(mock=True)
mock = True
mode_str = "MOCK"
recorder = DataRecorder()
root = tk.Tk()
dashboard = RadarDashboard(root, conn, recorder, device_index=args.device)
dashboard = RadarDashboard(root, mock, recorder, device_index=args.device)
if args.record:
filepath = os.path.join(
@@ -1582,8 +1610,8 @@ def main():
if dashboard._acq_thread is not None:
dashboard._acq_thread.stop()
dashboard._acq_thread.join(timeout=2)
if conn.is_open:
conn.close()
if dashboard.conn is not None and dashboard.conn.is_open:
dashboard.conn.close()
if recorder.recording:
recorder.stop()
root.destroy()
9_Firmware/9_3_GUI/GUI_V6_Demo.py
+6
View File
@@ -1,5 +1,11 @@
#!/usr/bin/env python3
# =============================================================================
# DEPRECATED: GUI V6 Demo is superseded by GUI_V65_Tk and V7.
# This file is retained for reference only. Do not use for new development.
# Removal planned for next major release.
# =============================================================================
"""
Radar System GUI - Fully Functional Demo Version
All buttons work, simulated radar data is generated in real-time
9_Firmware/9_3_GUI/GUI_versions.txt
+1 -1
View File
@@ -6,7 +6,7 @@ GUI_V4 ==> Added pitch correction
GUI_V5 ==> Added Mercury Color
GUI_V6 ==> Added USB3 FT601 support
GUI_V6 ==> Added USB3 FT601 support [DEPRECATED — superseded by V65/V7]
GUI_V65_Tk ==> Board bring-up dashboard (FT2232H reader, real-time R-D heatmap, CFAR overlay, waterfall, host commands, HDF5 recording, replay, demo mode)
radar_protocol ==> Protocol layer (packet parsing, command building, FT2232H connection, data recorder, acquisition thread)
9_Firmware/9_3_GUI/radar_protocol.py
+200 -6
View File
@@ -6,6 +6,7 @@ Pure-logic module for USB packet parsing and command building.
No GUI dependencies — safe to import from tests and headless scripts.
USB Interface: FT2232H USB 2.0 (8-bit, 50T production board) via pyftdi
FT601 USB 3.0 (32-bit, 200T premium board) via ftd3xx
USB Packet Protocol (11-byte):
TX (FPGA→Host):
@@ -22,7 +23,7 @@ import queue
import logging
import contextlib
from dataclasses import dataclass, field
from typing import Any
from typing import Any, ClassVar
from enum import IntEnum
@@ -200,7 +201,9 @@ class RadarProtocol:
range_i = _to_signed16(struct.unpack_from(">H", raw, 3)[0])
doppler_i = _to_signed16(struct.unpack_from(">H", raw, 5)[0])
doppler_q = _to_signed16(struct.unpack_from(">H", raw, 7)[0])
detection = raw[9] & 0x01
det_byte = raw[9]
detection = det_byte & 0x01
frame_start = (det_byte >> 7) & 0x01
return {
"range_i": range_i,
@@ -208,6 +211,7 @@ class RadarProtocol:
"doppler_i": doppler_i,
"doppler_q": doppler_q,
"detection": detection,
"frame_start": frame_start,
}
@staticmethod
@@ -433,7 +437,191 @@ class FT2232HConnection:
pkt += struct.pack(">h", np.clip(range_i, -32768, 32767))
pkt += struct.pack(">h", np.clip(dop_i, -32768, 32767))
pkt += struct.pack(">h", np.clip(dop_q, -32768, 32767))
pkt.append(detection & 0x01)
# Bit 7 = frame_start (sample_counter == 0), bit 0 = detection
det_byte = (detection & 0x01) | (0x80 if idx == 0 else 0x00)
pkt.append(det_byte)
pkt.append(FOOTER_BYTE)
buf += pkt
self._mock_seq_idx = (start_idx + num_packets) % NUM_CELLS
return bytes(buf)
# ============================================================================
# FT601 USB 3.0 Connection (premium board only)
# ============================================================================
# Optional ftd3xx import (FTDI's proprietary driver for FT60x USB 3.0 chips).
# pyftdi does NOT support FT601 — it only handles USB 2.0 chips (FT232H, etc.)
try:
import ftd3xx # type: ignore[import-untyped]
FTD3XX_AVAILABLE = True
_Ftd3xxError: type = ftd3xx.FTD3XXError # type: ignore[attr-defined]
except ImportError:
FTD3XX_AVAILABLE = False
_Ftd3xxError = OSError # fallback for type-checking; never raised
class FT601Connection:
"""
FT601 USB 3.0 SuperSpeed FIFO bridge — premium board only.
The FT601 has a 32-bit data bus and runs at 100 MHz.
VID:PID = 0x0403:0x6030 or 0x6031 (FTDI FT60x).
Requires the ``ftd3xx`` library (``pip install ftd3xx`` on Windows,
or ``libft60x`` on Linux). This is FTDI's proprietary USB 3.0 driver;
``pyftdi`` only supports USB 2.0 and will NOT work with FT601.
Public contract matches FT2232HConnection so callers can swap freely.
"""
VID = 0x0403
PID_LIST: ClassVar[list[int]] = [0x6030, 0x6031]
def __init__(self, mock: bool = True):
self._mock = mock
self._dev = None
self._lock = threading.Lock()
self.is_open = False
# Mock state (reuses same synthetic data pattern)
self._mock_frame_num = 0
self._mock_rng = np.random.RandomState(42)
def open(self, device_index: int = 0) -> bool:
if self._mock:
self.is_open = True
log.info("FT601 mock device opened (no hardware)")
return True
if not FTD3XX_AVAILABLE:
log.error(
"ftd3xx library required for FT601 hardware — "
"install with: pip install ftd3xx"
)
return False
try:
self._dev = ftd3xx.create(device_index, ftd3xx.OPEN_BY_INDEX)
if self._dev is None:
log.error("No FT601 device found at index %d", device_index)
return False
# Verify chip configuration — only reconfigure if needed.
# setChipConfiguration triggers USB re-enumeration, which
# invalidates the device handle and requires a re-open cycle.
cfg = self._dev.getChipConfiguration()
needs_reconfig = (
cfg.FIFOMode != 0 # 245 FIFO mode
or cfg.ChannelConfig != 0 # 1 channel, 32-bit
or cfg.OptionalFeatureSupport != 0
)
if needs_reconfig:
cfg.FIFOMode = 0
cfg.ChannelConfig = 0
cfg.OptionalFeatureSupport = 0
self._dev.setChipConfiguration(cfg)
# Device re-enumerates — close stale handle, wait, re-open
self._dev.close()
self._dev = None
import time
time.sleep(2.0) # wait for USB re-enumeration
self._dev = ftd3xx.create(device_index, ftd3xx.OPEN_BY_INDEX)
if self._dev is None:
log.error("FT601 not found after reconfiguration")
return False
log.info("FT601 reconfigured and re-opened (index %d)", device_index)
self.is_open = True
log.info("FT601 device opened (index %d)", device_index)
return True
except (OSError, _Ftd3xxError) as e:
log.error("FT601 open failed: %s", e)
self._dev = None
return False
def close(self):
if self._dev is not None:
with contextlib.suppress(Exception):
self._dev.close()
self._dev = None
self.is_open = False
def read(self, size: int = 4096) -> bytes | None:
"""Read raw bytes from FT601. Returns None on error/timeout."""
if not self.is_open:
return None
if self._mock:
return self._mock_read(size)
with self._lock:
try:
data = self._dev.readPipe(0x82, size, raw=True)
return bytes(data) if data else None
except (OSError, _Ftd3xxError) as e:
log.error("FT601 read error: %s", e)
return None
def write(self, data: bytes) -> bool:
"""Write raw bytes to FT601. Data must be 4-byte aligned for 32-bit bus."""
if not self.is_open:
return False
if self._mock:
log.info(f"FT601 mock write: {data.hex()}")
return True
# Pad to 4-byte alignment (FT601 32-bit bus requirement).
# NOTE: Radar commands are already 4 bytes, so this should be a no-op.
remainder = len(data) % 4
if remainder:
data = data + b"\x00" * (4 - remainder)
with self._lock:
try:
written = self._dev.writePipe(0x02, data, raw=True)
return written == len(data)
except (OSError, _Ftd3xxError) as e:
log.error("FT601 write error: %s", e)
return False
def _mock_read(self, size: int) -> bytes:
"""Generate synthetic radar packets (same pattern as FT2232H mock)."""
time.sleep(0.05)
self._mock_frame_num += 1
buf = bytearray()
num_packets = min(NUM_CELLS, size // DATA_PACKET_SIZE)
start_idx = getattr(self, "_mock_seq_idx", 0)
for n in range(num_packets):
idx = (start_idx + n) % NUM_CELLS
rbin = idx // NUM_DOPPLER_BINS
dbin = idx % NUM_DOPPLER_BINS
range_i = int(self._mock_rng.normal(0, 100))
range_q = int(self._mock_rng.normal(0, 100))
if abs(rbin - 20) < 3:
range_i += 5000
range_q += 3000
dop_i = int(self._mock_rng.normal(0, 50))
dop_q = int(self._mock_rng.normal(0, 50))
if abs(rbin - 20) < 3 and abs(dbin - 8) < 2:
dop_i += 8000
dop_q += 4000
detection = 1 if (abs(rbin - 20) < 2 and abs(dbin - 8) < 2) else 0
pkt = bytearray()
pkt.append(HEADER_BYTE)
pkt += struct.pack(">h", np.clip(range_q, -32768, 32767))
pkt += struct.pack(">h", np.clip(range_i, -32768, 32767))
pkt += struct.pack(">h", np.clip(dop_i, -32768, 32767))
pkt += struct.pack(">h", np.clip(dop_q, -32768, 32767))
# Bit 7 = frame_start (sample_counter == 0), bit 0 = detection
det_byte = (detection & 0x01) | (0x80 if idx == 0 else 0x00)
pkt.append(det_byte)
pkt.append(FOOTER_BYTE)
buf += pkt
@@ -600,6 +788,12 @@ class RadarAcquisition(threading.Thread):
if sample.get("detection", 0):
self._frame.detections[rbin, dbin] = 1
self._frame.detection_count += 1
# Accumulate FPGA range profile data (matched-filter output)
# Each sample carries the range_i/range_q for this range bin.
# Accumulate magnitude across Doppler bins for the range profile.
ri = int(sample.get("range_i", 0))
rq = int(sample.get("range_q", 0))
self._frame.range_profile[rbin] += abs(ri) + abs(rq)
self._sample_idx += 1
@@ -607,11 +801,11 @@ class RadarAcquisition(threading.Thread):
self._finalize_frame()
def _finalize_frame(self):
"""Complete frame: compute range profile, push to queue, record."""
"""Complete frame: push to queue, record."""
self._frame.timestamp = time.time()
self._frame.frame_number = self._frame_num
# Range profile = sum of magnitude across Doppler bins
self._frame.range_profile = np.sum(self._frame.magnitude, axis=1)
# range_profile is already accumulated from FPGA range_i/range_q
# data in _ingest_sample(). No need to synthesize from doppler magnitude.
# Push to display queue (drop old if backed up)
try:
9_Firmware/9_3_GUI/test_GUI_V65_Tk.py
+56 -1
View File
@@ -16,7 +16,7 @@ import unittest
import numpy as np
from radar_protocol import (
RadarProtocol, FT2232HConnection, DataRecorder, RadarAcquisition,
RadarProtocol, FT2232HConnection, FT601Connection, DataRecorder, RadarAcquisition,
RadarFrame, StatusResponse, Opcode,
HEADER_BYTE, FOOTER_BYTE, STATUS_HEADER_BYTE,
NUM_RANGE_BINS, NUM_DOPPLER_BINS,
@@ -312,6 +312,61 @@ class TestFT2232HConnection(unittest.TestCase):
self.assertFalse(conn.write(b"\x00\x00\x00\x00"))
class TestFT601Connection(unittest.TestCase):
"""Test mock FT601 connection (mirrors FT2232H tests)."""
def test_mock_open_close(self):
conn = FT601Connection(mock=True)
self.assertTrue(conn.open())
self.assertTrue(conn.is_open)
conn.close()
self.assertFalse(conn.is_open)
def test_mock_read_returns_data(self):
conn = FT601Connection(mock=True)
conn.open()
data = conn.read(4096)
self.assertIsNotNone(data)
self.assertGreater(len(data), 0)
conn.close()
def test_mock_read_contains_valid_packets(self):
"""Mock data should contain parseable data packets."""
conn = FT601Connection(mock=True)
conn.open()
raw = conn.read(4096)
packets = RadarProtocol.find_packet_boundaries(raw)
self.assertGreater(len(packets), 0)
for start, end, ptype in packets:
if ptype == "data":
result = RadarProtocol.parse_data_packet(raw[start:end])
self.assertIsNotNone(result)
conn.close()
def test_mock_write(self):
conn = FT601Connection(mock=True)
conn.open()
cmd = RadarProtocol.build_command(0x01, 1)
self.assertTrue(conn.write(cmd))
conn.close()
def test_write_pads_to_4_bytes(self):
"""FT601 write() should pad data to 4-byte alignment."""
conn = FT601Connection(mock=True)
conn.open()
# 3-byte payload should be padded internally (no error)
self.assertTrue(conn.write(b"\x01\x02\x03"))
conn.close()
def test_read_when_closed(self):
conn = FT601Connection(mock=True)
self.assertIsNone(conn.read())
def test_write_when_closed(self):
conn = FT601Connection(mock=True)
self.assertFalse(conn.write(b"\x00\x00\x00\x00"))
class TestDataRecorder(unittest.TestCase):
"""Test HDF5 recording (skipped if h5py not available)."""
9_Firmware/9_3_GUI/test_v7.py
+16 -14
View File
@@ -65,9 +65,9 @@ class TestRadarSettings(unittest.TestCase):
def test_defaults(self):
s = _models().RadarSettings()
self.assertEqual(s.system_frequency, 10e9)
self.assertEqual(s.coverage_radius, 50000)
self.assertEqual(s.max_distance, 50000)
self.assertEqual(s.system_frequency, 10.5e9)
self.assertEqual(s.coverage_radius, 1536)
self.assertEqual(s.max_distance, 1536)
class TestGPSData(unittest.TestCase):
@@ -425,26 +425,28 @@ class TestWaveformConfig(unittest.TestCase):
def test_defaults(self):
from v7.models import WaveformConfig
wc = WaveformConfig()
self.assertEqual(wc.sample_rate_hz, 4e6)
self.assertEqual(wc.bandwidth_hz, 500e6)
self.assertEqual(wc.chirp_duration_s, 300e-6)
self.assertEqual(wc.center_freq_hz, 10.525e9)
self.assertEqual(wc.sample_rate_hz, 100e6)
self.assertEqual(wc.bandwidth_hz, 20e6)
self.assertEqual(wc.chirp_duration_s, 30e-6)
self.assertEqual(wc.pri_s, 167e-6)
self.assertEqual(wc.center_freq_hz, 10.5e9)
self.assertEqual(wc.n_range_bins, 64)
self.assertEqual(wc.n_doppler_bins, 32)
self.assertEqual(wc.chirps_per_subframe, 16)
self.assertEqual(wc.fft_size, 1024)
self.assertEqual(wc.decimation_factor, 16)
def test_range_resolution(self):
"""range_resolution_m should be ~5.62 m/bin with ADI defaults."""
"""range_resolution_m should be ~23.98 m/bin (matched filter, 100 MSPS)."""
from v7.models import WaveformConfig
wc = WaveformConfig()
self.assertAlmostEqual(wc.range_resolution_m, 5.621, places=1)
self.assertAlmostEqual(wc.range_resolution_m, 23.983, places=1)
def test_velocity_resolution(self):
"""velocity_resolution_mps should be ~1.484 m/s/bin."""
"""velocity_resolution_mps should be ~5.34 m/s/bin (PRI=167us, 16 chirps)."""
from v7.models import WaveformConfig
wc = WaveformConfig()
self.assertAlmostEqual(wc.velocity_resolution_mps, 1.484, places=2)
self.assertAlmostEqual(wc.velocity_resolution_mps, 5.343, places=1)
def test_max_range(self):
"""max_range_m = range_resolution * n_range_bins."""
@@ -466,7 +468,7 @@ class TestWaveformConfig(unittest.TestCase):
"""Non-default parameters correctly change derived values."""
from v7.models import WaveformConfig
wc1 = WaveformConfig()
wc2 = WaveformConfig(bandwidth_hz=1e9) # double BW → halve range res
wc2 = WaveformConfig(sample_rate_hz=200e6) # double Fs → halve range bin
self.assertAlmostEqual(wc2.range_resolution_m, wc1.range_resolution_m / 2, places=2)
def test_zero_center_freq_velocity(self):
@@ -925,9 +927,9 @@ class TestExtractTargetsFromFrame(unittest.TestCase):
"""Detection at range bin 10 → range = 10 * range_resolution."""
from v7.processing import extract_targets_from_frame
frame = self._make_frame(det_cells=[(10, 16)]) # dbin=16 = center → vel=0
targets = extract_targets_from_frame(frame, range_resolution=5.621)
targets = extract_targets_from_frame(frame, range_resolution=23.983)
self.assertEqual(len(targets), 1)
self.assertAlmostEqual(targets[0].range, 10 * 5.621, places=2)
self.assertAlmostEqual(targets[0].range, 10 * 23.983, places=1)
self.assertAlmostEqual(targets[0].velocity, 0.0, places=2)
def test_velocity_sign(self):
9_Firmware/9_3_GUI/v7/__init__.py
+2 -1
View File
@@ -26,6 +26,7 @@ from .models import (
# Hardware interfaces — production protocol via radar_protocol.py
from .hardware import (
FT2232HConnection,
FT601Connection,
RadarProtocol,
Opcode,
RadarAcquisition,
@@ -89,7 +90,7 @@ __all__ = [ # noqa: RUF022
"USB_AVAILABLE", "FTDI_AVAILABLE", "SCIPY_AVAILABLE",
"SKLEARN_AVAILABLE", "FILTERPY_AVAILABLE",
# hardware — production FPGA protocol
"FT2232HConnection", "RadarProtocol", "Opcode",
"FT2232HConnection", "FT601Connection", "RadarProtocol", "Opcode",
"RadarAcquisition", "RadarFrame", "StatusResponse", "DataRecorder",
"STM32USBInterface",
# processing
9_Firmware/9_3_GUI/v7/dashboard.py
+39 -10
View File
@@ -13,13 +13,14 @@ RadarDashboard is a QMainWindow with six tabs:
6. Settings — Host-side DSP parameters + About section
Uses production radar_protocol.py for all FPGA communication:
- FT2232HConnection for real hardware
- FT2232HConnection for production board (FT2232H USB 2.0)
- FT601Connection for premium board (FT601 USB 3.0) — selectable from GUI
- Unified replay via SoftwareFPGA + ReplayEngine + ReplayWorker
- Mock mode (FT2232HConnection(mock=True)) for development
The old STM32 magic-packet start flow has been removed. FPGA registers
are controlled directly via 4-byte {opcode, addr, value_hi, value_lo}
commands sent over FT2232H.
commands sent over FT2232H or FT601.
"""
from __future__ import annotations
@@ -55,6 +56,7 @@ from .models import (
)
from .hardware import (
FT2232HConnection,
FT601Connection,
RadarProtocol,
RadarFrame,
StatusResponse,
@@ -142,7 +144,7 @@ class RadarDashboard(QMainWindow):
)
# Hardware interfaces — production protocol
self._connection: FT2232HConnection | None = None
self._connection: FT2232HConnection | FT601Connection | None = None
self._stm32 = STM32USBInterface()
self._recorder = DataRecorder()
@@ -364,7 +366,7 @@ class RadarDashboard(QMainWindow):
# Row 0: connection mode + device combos + buttons
ctrl_layout.addWidget(QLabel("Mode:"), 0, 0)
self._mode_combo = QComboBox()
self._mode_combo.addItems(["Mock", "Live FT2232H", "Replay"])
self._mode_combo.addItems(["Mock", "Live", "Replay"])
self._mode_combo.setCurrentIndex(0)
ctrl_layout.addWidget(self._mode_combo, 0, 1)
@@ -377,6 +379,13 @@ class RadarDashboard(QMainWindow):
refresh_btn.clicked.connect(self._refresh_devices)
ctrl_layout.addWidget(refresh_btn, 0, 4)
# USB Interface selector (production FT2232H / premium FT601)
ctrl_layout.addWidget(QLabel("USB Interface:"), 0, 5)
self._usb_iface_combo = QComboBox()
self._usb_iface_combo.addItems(["FT2232H (Production)", "FT601 (Premium)"])
self._usb_iface_combo.setCurrentIndex(0)
ctrl_layout.addWidget(self._usb_iface_combo, 0, 6)
self._start_btn = QPushButton("Start Radar")
self._start_btn.setStyleSheet(
f"QPushButton {{ background-color: {DARK_SUCCESS}; color: white; font-weight: bold; }}"
@@ -1001,7 +1010,8 @@ class RadarDashboard(QMainWindow):
self._conn_ft2232h = self._make_status_label("FT2232H")
self._conn_stm32 = self._make_status_label("STM32 USB")
conn_layout.addWidget(QLabel("FT2232H:"), 0, 0)
self._conn_usb_label = QLabel("USB Data:")
conn_layout.addWidget(self._conn_usb_label, 0, 0)
conn_layout.addWidget(self._conn_ft2232h, 0, 1)
conn_layout.addWidget(QLabel("STM32 USB:"), 1, 0)
conn_layout.addWidget(self._conn_stm32, 1, 1)
@@ -1167,7 +1177,7 @@ class RadarDashboard(QMainWindow):
about_lbl = QLabel(
"<b>AERIS-10 Radar System V7</b><br>"
"PyQt6 Edition with Embedded Leaflet Map<br><br>"
"<b>Data Interface:</b> FT2232H USB 2.0 (production protocol)<br>"
"<b>Data Interface:</b> FT2232H USB 2.0 (production) / FT601 USB 3.0 (premium)<br>"
"<b>FPGA Protocol:</b> 4-byte register commands, 0xAA/0xBB packets<br>"
"<b>Map:</b> OpenStreetMap + Leaflet.js<br>"
"<b>Framework:</b> PyQt6 + QWebEngine<br>"
@@ -1224,7 +1234,7 @@ class RadarDashboard(QMainWindow):
# =====================================================================
def _send_fpga_cmd(self, opcode: int, value: int):
"""Send a 4-byte register command to the FPGA via FT2232H."""
"""Send a 4-byte register command to the FPGA via USB (FT2232H or FT601)."""
if self._connection is None or not self._connection.is_open:
logger.warning(f"Cannot send 0x{opcode:02X}={value}: no connection")
return
@@ -1287,16 +1297,26 @@ class RadarDashboard(QMainWindow):
if "Mock" in mode:
self._replay_mode = False
self._connection = FT2232HConnection(mock=True)
iface = self._usb_iface_combo.currentText()
if "FT601" in iface:
self._connection = FT601Connection(mock=True)
else:
self._connection = FT2232HConnection(mock=True)
if not self._connection.open():
QMessageBox.critical(self, "Error", "Failed to open mock connection.")
return
elif "Live" in mode:
self._replay_mode = False
self._connection = FT2232HConnection(mock=False)
iface = self._usb_iface_combo.currentText()
if "FT601" in iface:
self._connection = FT601Connection(mock=False)
iface_name = "FT601"
else:
self._connection = FT2232HConnection(mock=False)
iface_name = "FT2232H"
if not self._connection.open():
QMessageBox.critical(self, "Error",
"Failed to open FT2232H. Check USB connection.")
f"Failed to open {iface_name}. Check USB connection.")
return
elif "Replay" in mode:
self._replay_mode = True
@@ -1368,6 +1388,7 @@ class RadarDashboard(QMainWindow):
self._start_btn.setEnabled(False)
self._stop_btn.setEnabled(True)
self._mode_combo.setEnabled(False)
self._usb_iface_combo.setEnabled(False)
self._demo_btn_main.setEnabled(False)
self._demo_btn_map.setEnabled(False)
n_frames = self._replay_engine.total_frames
@@ -1417,6 +1438,7 @@ class RadarDashboard(QMainWindow):
self._start_btn.setEnabled(False)
self._stop_btn.setEnabled(True)
self._mode_combo.setEnabled(False)
self._usb_iface_combo.setEnabled(False)
self._demo_btn_main.setEnabled(False)
self._demo_btn_map.setEnabled(False)
self._status_label_main.setText(f"Status: Running ({mode})")
@@ -1462,6 +1484,7 @@ class RadarDashboard(QMainWindow):
self._start_btn.setEnabled(True)
self._stop_btn.setEnabled(False)
self._mode_combo.setEnabled(True)
self._usb_iface_combo.setEnabled(True)
self._demo_btn_main.setEnabled(True)
self._demo_btn_map.setEnabled(True)
self._status_label_main.setText("Status: Radar stopped")
@@ -1954,6 +1977,12 @@ class RadarDashboard(QMainWindow):
self._set_conn_indicator(self._conn_ft2232h, conn_open)
self._set_conn_indicator(self._conn_stm32, self._stm32.is_open)
# Update USB label to reflect which interface is active
if isinstance(self._connection, FT601Connection):
self._conn_usb_label.setText("FT601:")
else:
self._conn_usb_label.setText("FT2232H:")
gps_count = self._gps_packet_count
if self._gps_worker:
gps_count = self._gps_worker.gps_count
9_Firmware/9_3_GUI/v7/hardware.py
+4 -2
View File
@@ -25,6 +25,7 @@ if USB_AVAILABLE:
sys.path.insert(0, os.path.join(os.path.dirname(__file__), ".."))
from radar_protocol import ( # noqa: F401 — re-exported for v7 package
FT2232HConnection,
FT601Connection,
RadarProtocol,
Opcode,
RadarAcquisition,
@@ -46,8 +47,9 @@ class STM32USBInterface:
Used ONLY for receiving GPS data from the MCU.
FPGA register commands are sent via FT2232H (see FT2232HConnection
from radar_protocol.py). The old send_start_flag() / send_settings()
FPGA register commands are sent via the USB data interface — either
FT2232HConnection (production) or FT601Connection (premium), both
from radar_protocol.py. The old send_start_flag() / send_settings()
methods have been removed — they used an incompatible magic-packet
protocol that the FPGA does not understand.
"""
9_Firmware/9_3_GUI/v7/map_widget.py
+1 -1
View File
@@ -98,7 +98,7 @@ class RadarMapWidget(QWidget):
)
self._targets: list[RadarTarget] = []
self._pending_targets: list[RadarTarget] | None = None
self._coverage_radius = 50_000 # metres
self._coverage_radius = 1_536 # metres (64 bins x ~24 m/bin)
self._tile_server = TileServer.OPENSTREETMAP
self._show_coverage = True
self._show_trails = False
9_Firmware/9_3_GUI/v7/models.py
+29 -22
View File
@@ -108,12 +108,12 @@ class RadarSettings:
range_resolution and velocity_resolution should be calibrated to
the actual waveform parameters.
"""
system_frequency: float = 10e9 # Hz (carrier, used for velocity calc)
range_resolution: float = 781.25 # Meters per range bin (default: 50km/64)
velocity_resolution: float = 1.0 # m/s per Doppler bin (calibrate to waveform)
max_distance: float = 50000 # Max detection range (m)
map_size: float = 50000 # Map display size (m)
coverage_radius: float = 50000 # Map coverage radius (m)
system_frequency: float = 10.5e9 # Hz (carrier, used for velocity calc)
range_resolution: float = 24.0 # Meters per range bin (c/(2*Fs)*decim)
velocity_resolution: float = 1.0 # m/s per Doppler bin (calibrate to waveform)
max_distance: float = 1536 # Max detection range (m)
map_size: float = 2000 # Map display size (m)
coverage_radius: float = 1536 # Map coverage radius (m)
@dataclass
@@ -199,39 +199,46 @@ class WaveformConfig:
Encapsulates the radar waveform so that range/velocity resolution
can be derived automatically instead of hardcoded in RadarSettings.
Defaults match the ADI CN0566 Phaser capture parameters used in
the golden_reference cosim (4 MSPS, 500 MHz BW, 300 us chirp).
Defaults match the AERIS-10 production system parameters from
radar_scene.py / plfm_chirp_controller.v:
100 MSPS DDC output, 20 MHz chirp BW, 30 us long chirp,
167 us long-chirp PRI, X-band 10.5 GHz carrier.
"""
sample_rate_hz: float = 4e6 # ADC sample rate
bandwidth_hz: float = 500e6 # Chirp bandwidth
chirp_duration_s: float = 300e-6 # Chirp ramp time
center_freq_hz: float = 10.525e9 # Carrier frequency
sample_rate_hz: float = 100e6 # DDC output I/Q rate (matched filter input)
bandwidth_hz: float = 20e6 # Chirp bandwidth (not used in range calc;
# retained for time-bandwidth product / display)
chirp_duration_s: float = 30e-6 # Long chirp ramp time
pri_s: float = 167e-6 # Pulse repetition interval (chirp + listen)
center_freq_hz: float = 10.5e9 # Carrier frequency (radar_scene.py: F_CARRIER)
n_range_bins: int = 64 # After decimation
n_doppler_bins: int = 32 # After Doppler FFT
n_doppler_bins: int = 32 # Total Doppler bins (2 sub-frames x 16)
chirps_per_subframe: int = 16 # Chirps in one Doppler sub-frame
fft_size: int = 1024 # Pre-decimation FFT length
decimation_factor: int = 16 # 1024 → 64
@property
def range_resolution_m(self) -> float:
"""Meters per decimated range bin (FMCW deramped baseband).
"""Meters per decimated range bin (matched-filter pulse compression).
For deramped FMCW: bin spacing = c * Fs * T / (2 * N_FFT * BW).
After decimation the bin spacing grows by *decimation_factor*.
For FFT-based matched filtering, each IFFT output bin spans
c / (2 * Fs) in range, where Fs is the I/Q sample rate at the
matched-filter input (DDC output). After decimation the bin
spacing grows by *decimation_factor*.
"""
c = 299_792_458.0
raw_bin = (
c * self.sample_rate_hz * self.chirp_duration_s
/ (2.0 * self.fft_size * self.bandwidth_hz)
)
raw_bin = c / (2.0 * self.sample_rate_hz)
return raw_bin * self.decimation_factor
@property
def velocity_resolution_mps(self) -> float:
"""m/s per Doppler bin. lambda / (2 * n_doppler * chirp_duration)."""
"""m/s per Doppler bin.
lambda / (2 * chirps_per_subframe * PRI), matching radar_scene.py.
"""
c = 299_792_458.0
wavelength = c / self.center_freq_hz
return wavelength / (2.0 * self.n_doppler_bins * self.chirp_duration_s)
return wavelength / (2.0 * self.chirps_per_subframe * self.pri_s)
@property
def max_range_m(self) -> float:
9_Firmware/9_3_GUI/v7/workers.py
+2 -2
View File
@@ -334,7 +334,7 @@ class TargetSimulator(QObject):
self._add_random_target()
def _add_random_target(self):
range_m = random.uniform(5000, 40000)
range_m = random.uniform(50, 1400)
azimuth = random.uniform(0, 360)
velocity = random.uniform(-100, 100)
elevation = random.uniform(-5, 45)
@@ -368,7 +368,7 @@ class TargetSimulator(QObject):
for t in self._targets:
new_range = t.range - t.velocity * 0.5
if new_range < 500 or new_range > 50000:
if new_range < 10 or new_range > 1536:
continue # target exits coverage — drop it
new_vel = max(-150, min(150, t.velocity + random.uniform(-2, 2)))
9_Firmware/tests/cross_layer/adar1000_vm_reference.py
+216
View File
@@ -0,0 +1,216 @@
"""ADAR1000 vector-modulator ground-truth table and firmware parser.
This module is a pure data + helpers library imported by the cross-layer
test suite (`9_Firmware/tests/cross_layer/test_cross_layer_contract.py`,
class `TestTier2Adar1000VmTableGroundTruth`). It has no CLI entry point
and no side effects on import beyond the structural assertion on the
table length.
Ground-truth source
-------------------
The 128-entry `(I, Q)` byte pairs below are transcribed from the ADAR1000
datasheet Rev. B, Tables 13-16, page 34 ("Phase Shifter Programming"),
which is the primary normative reference. The same values appear in the
Analog Devices Linux beamformer driver
(`drivers/iio/beamformer/adar1000.c`, `adar1000_phase_values[]`) and were
cross-checked against that driver as a secondary, independent
transcription. The byte values are factual data (5-bit unsigned magnitude
in bits[4:0], polarity bit at bit[5], bits[7:6] reserved zero); no
copyrightable creative expression. Only the datasheet is the
licensing-relevant source.
PLFM_RADAR firmware indexing convention
---------------------------------------
`adarSetRxPhase` / `adarSetTxPhase` in
`9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp`
write `VM_I[phase % 128]` and `VM_Q[phase % 128]` to the chip. Each index
N corresponds to commanded beam phase `N * 360/128 = N * 2.8125 deg`. The
ADI table is also on a uniform 2.8125 deg grid (verified by
`check_uniform_2p8125_deg_step` below), so a 1:1 mapping is correct:
PLFM index N == ADI table row N.
"""
from __future__ import annotations
import re
# ----------------------------------------------------------------------------
# Ground truth: ADAR1000 datasheet Rev. B Tables 13-16 p.34
# Each entry: (angle_int_deg, angle_frac_x10000, vm_byte_I, vm_byte_Q)
# ----------------------------------------------------------------------------
GROUND_TRUTH: list[tuple[int, int, int, int]] = [
(0, 0, 0x3F, 0x20), (2, 8125, 0x3F, 0x21), (5, 6250, 0x3F, 0x23),
(8, 4375, 0x3F, 0x24), (11, 2500, 0x3F, 0x26), (14, 625, 0x3E, 0x27),
(16, 8750, 0x3E, 0x28), (19, 6875, 0x3D, 0x2A), (22, 5000, 0x3D, 0x2B),
(25, 3125, 0x3C, 0x2D), (28, 1250, 0x3C, 0x2E), (30, 9375, 0x3B, 0x2F),
(33, 7500, 0x3A, 0x30), (36, 5625, 0x39, 0x31), (39, 3750, 0x38, 0x33),
(42, 1875, 0x37, 0x34), (45, 0, 0x36, 0x35), (47, 8125, 0x35, 0x36),
(50, 6250, 0x34, 0x37), (53, 4375, 0x33, 0x38), (56, 2500, 0x32, 0x38),
(59, 625, 0x30, 0x39), (61, 8750, 0x2F, 0x3A), (64, 6875, 0x2E, 0x3A),
(67, 5000, 0x2C, 0x3B), (70, 3125, 0x2B, 0x3C), (73, 1250, 0x2A, 0x3C),
(75, 9375, 0x28, 0x3C), (78, 7500, 0x27, 0x3D), (81, 5625, 0x25, 0x3D),
(84, 3750, 0x24, 0x3D), (87, 1875, 0x22, 0x3D), (90, 0, 0x21, 0x3D),
(92, 8125, 0x01, 0x3D), (95, 6250, 0x03, 0x3D), (98, 4375, 0x04, 0x3D),
(101, 2500, 0x06, 0x3D), (104, 625, 0x07, 0x3C), (106, 8750, 0x08, 0x3C),
(109, 6875, 0x0A, 0x3C), (112, 5000, 0x0B, 0x3B), (115, 3125, 0x0D, 0x3A),
(118, 1250, 0x0E, 0x3A), (120, 9375, 0x0F, 0x39), (123, 7500, 0x11, 0x38),
(126, 5625, 0x12, 0x38), (129, 3750, 0x13, 0x37), (132, 1875, 0x14, 0x36),
(135, 0, 0x16, 0x35), (137, 8125, 0x17, 0x34), (140, 6250, 0x18, 0x33),
(143, 4375, 0x19, 0x31), (146, 2500, 0x19, 0x30), (149, 625, 0x1A, 0x2F),
(151, 8750, 0x1B, 0x2E), (154, 6875, 0x1C, 0x2D), (157, 5000, 0x1C, 0x2B),
(160, 3125, 0x1D, 0x2A), (163, 1250, 0x1E, 0x28), (165, 9375, 0x1E, 0x27),
(168, 7500, 0x1E, 0x26), (171, 5625, 0x1F, 0x24), (174, 3750, 0x1F, 0x23),
(177, 1875, 0x1F, 0x21), (180, 0, 0x1F, 0x20), (182, 8125, 0x1F, 0x01),
(185, 6250, 0x1F, 0x03), (188, 4375, 0x1F, 0x04), (191, 2500, 0x1F, 0x06),
(194, 625, 0x1E, 0x07), (196, 8750, 0x1E, 0x08), (199, 6875, 0x1D, 0x0A),
(202, 5000, 0x1D, 0x0B), (205, 3125, 0x1C, 0x0D), (208, 1250, 0x1C, 0x0E),
(210, 9375, 0x1B, 0x0F), (213, 7500, 0x1A, 0x10), (216, 5625, 0x19, 0x11),
(219, 3750, 0x18, 0x13), (222, 1875, 0x17, 0x14), (225, 0, 0x16, 0x15),
(227, 8125, 0x15, 0x16), (230, 6250, 0x14, 0x17), (233, 4375, 0x13, 0x18),
(236, 2500, 0x12, 0x18), (239, 625, 0x10, 0x19), (241, 8750, 0x0F, 0x1A),
(244, 6875, 0x0E, 0x1A), (247, 5000, 0x0C, 0x1B), (250, 3125, 0x0B, 0x1C),
(253, 1250, 0x0A, 0x1C), (255, 9375, 0x08, 0x1C), (258, 7500, 0x07, 0x1D),
(261, 5625, 0x05, 0x1D), (264, 3750, 0x04, 0x1D), (267, 1875, 0x02, 0x1D),
(270, 0, 0x01, 0x1D), (272, 8125, 0x21, 0x1D), (275, 6250, 0x23, 0x1D),
(278, 4375, 0x24, 0x1D), (281, 2500, 0x26, 0x1D), (284, 625, 0x27, 0x1C),
(286, 8750, 0x28, 0x1C), (289, 6875, 0x2A, 0x1C), (292, 5000, 0x2B, 0x1B),
(295, 3125, 0x2D, 0x1A), (298, 1250, 0x2E, 0x1A), (300, 9375, 0x2F, 0x19),
(303, 7500, 0x31, 0x18), (306, 5625, 0x32, 0x18), (309, 3750, 0x33, 0x17),
(312, 1875, 0x34, 0x16), (315, 0, 0x36, 0x15), (317, 8125, 0x37, 0x14),
(320, 6250, 0x38, 0x13), (323, 4375, 0x39, 0x11), (326, 2500, 0x39, 0x10),
(329, 625, 0x3A, 0x0F), (331, 8750, 0x3B, 0x0E), (334, 6875, 0x3C, 0x0D),
(337, 5000, 0x3C, 0x0B), (340, 3125, 0x3D, 0x0A), (343, 1250, 0x3E, 0x08),
(345, 9375, 0x3E, 0x07), (348, 7500, 0x3E, 0x06), (351, 5625, 0x3F, 0x04),
(354, 3750, 0x3F, 0x03), (357, 1875, 0x3F, 0x01),
]
assert len(GROUND_TRUTH) == 128, f"GROUND_TRUTH must have 128 entries, has {len(GROUND_TRUTH)}"
VM_I_REF: list[int] = [row[2] for row in GROUND_TRUTH]
VM_Q_REF: list[int] = [row[3] for row in GROUND_TRUTH]
# ----------------------------------------------------------------------------
# Structural-invariant checks on the embedded ground-truth transcription.
# These defend against typos during the copy-paste from the datasheet / ADI
# driver. Each function returns a list of error strings (empty == pass) so
# callers (the pytest class) can assert-on-empty with a useful message.
# ----------------------------------------------------------------------------
def check_byte_format(label: str, table: list[int]) -> list[str]:
"""Each byte must have bits[7:6] == 0 (reserved)."""
errors = []
for i, byte in enumerate(table):
if byte & 0xC0:
errors.append(f"{label}[{i}]=0x{byte:02X}: reserved bits[7:6] non-zero")
return errors
def check_uniform_2p8125_deg_step() -> list[str]:
"""Angles must form a uniform 2.8125 deg grid: angle[N] == N * 2.8125."""
errors = []
for i, (deg_int, deg_frac, _, _) in enumerate(GROUND_TRUTH):
# angle in units of 1/10000 degree; 2.8125 deg = 28125/10000 exactly
angle_e4 = deg_int * 10000 + deg_frac
expected_e4 = i * 28125
if angle_e4 != expected_e4:
errors.append(
f"GROUND_TRUTH[{i}]: angle {deg_int}.{deg_frac:04d} deg "
f"(={angle_e4}/10000) != expected {expected_e4}/10000 "
f"(=i*2.8125)"
)
return errors
def check_quadrant_symmetry() -> list[str]:
"""Angle and angle+180 deg must have inverted polarity bits but identical
magnitudes. Index offset 64 corresponds to 180 deg on the 128-step grid.
Exemption: when magnitude is zero the polarity bit is physically
meaningless (sign of zero is undefined for the IQ phasor projection).
The datasheet uses POL=1 for both 0 and 180 deg Q components (both
encode Q=0). Skip the polarity assertion for zero-magnitude entries.
"""
errors = []
POL = 0x20
MAG = 0x1F
for i in range(64):
j = i + 64
mag_i_a, mag_i_b = VM_I_REF[i] & MAG, VM_I_REF[j] & MAG
if mag_i_a != mag_i_b:
errors.append(
f"VM_I[{i}]=0x{VM_I_REF[i]:02X} vs VM_I[{j}]=0x{VM_I_REF[j]:02X}: "
f"180 deg pair has different magnitude"
)
if mag_i_a != 0 and (VM_I_REF[i] & POL) == (VM_I_REF[j] & POL):
errors.append(
f"VM_I[{i}]=0x{VM_I_REF[i]:02X} vs VM_I[{j}]=0x{VM_I_REF[j]:02X}: "
f"180 deg pair has same polarity (should be inverted, mag={mag_i_a})"
)
mag_q_a, mag_q_b = VM_Q_REF[i] & MAG, VM_Q_REF[j] & MAG
if mag_q_a != mag_q_b:
errors.append(
f"VM_Q[{i}]=0x{VM_Q_REF[i]:02X} vs VM_Q[{j}]=0x{VM_Q_REF[j]:02X}: "
f"180 deg pair has different magnitude"
)
if mag_q_a != 0 and (VM_Q_REF[i] & POL) == (VM_Q_REF[j] & POL):
errors.append(
f"VM_Q[{i}]=0x{VM_Q_REF[i]:02X} vs VM_Q[{j}]=0x{VM_Q_REF[j]:02X}: "
f"180 deg pair has same polarity (should be inverted, mag={mag_q_a})"
)
return errors
def check_cardinal_points() -> list[str]:
"""Spot-check cardinal phase points against datasheet expectations."""
errors = []
expectations = [
(0, 0x3F, 0x20, "0 deg: max +I, ~zero Q"),
(32, 0x21, 0x3D, "90 deg: ~zero I, max +Q"),
(64, 0x1F, 0x20, "180 deg: max -I, ~zero Q"),
(96, 0x01, 0x1D, "270 deg: ~zero I, max -Q"),
]
for idx, exp_i, exp_q, desc in expectations:
if VM_I_REF[idx] != exp_i or VM_Q_REF[idx] != exp_q:
errors.append(
f"index {idx} ({desc}): expected (0x{exp_i:02X}, 0x{exp_q:02X}), "
f"got (0x{VM_I_REF[idx]:02X}, 0x{VM_Q_REF[idx]:02X})"
)
return errors
# ----------------------------------------------------------------------------
# Parse VM_I[] / VM_Q[] from firmware C++ source.
# ----------------------------------------------------------------------------
ARRAY_RE = re.compile(
r"const\s+uint8_t\s+ADAR1000Manager::(?P<name>VM_I|VM_Q|VM_GAIN)\s*"
r"\[\s*128\s*\]\s*=\s*\{(?P<body>[^}]*)\}\s*;",
re.DOTALL,
)
HEX_RE = re.compile(r"0[xX][0-9a-fA-F]{1,2}")
def parse_array(source: str, name: str) -> list[int] | None:
"""Extract a 128-entry uint8_t array from C++ source by name.
Returns None if the array is not found. Returns a list (possibly shorter
than 128) of the parsed bytes if found; caller is responsible for length
validation.
LIMITATION (intentional, see PR fix/adar1000-vm-tables review finding #2):
ARRAY_RE uses `[^}]*` for the body, which terminates at the first `}`.
This is sufficient for the *flat* `const uint8_t NAME[128] = { ... };`
declarations VM_I/VM_Q use today, but it would mis-parse if the array
body ever contained nested braces (e.g. designated initialisers, struct
aggregates, or macro-expansions producing braces). If the firmware ever
needs such a form for the VM tables, replace ARRAY_RE with a balanced
brace-counting parser. Until then, the current regex is preferred for
its simplicity and the round-trip tests will catch any silent breakage.
"""
for m in ARRAY_RE.finditer(source):
if m.group("name") != name:
continue
body = m.group("body")
body = re.sub(r"//[^\n]*", "", body)
body = re.sub(r"/\*.*?\*/", "", body, flags=re.DOTALL)
return [int(tok, 16) for tok in HEX_RE.findall(body)]
return None
9_Firmware/tests/cross_layer/contract_parser.py
+42 -9
View File
@@ -188,7 +188,7 @@ def parse_python_data_packet_fields(filepath: Path | None = None) -> list[DataPa
width_bits=size * 8
))
# Match detection = raw[9] & 0x01
# Match detection = raw[9] & 0x01 (direct access)
for m in re.finditer(r'(\w+)\s*=\s*raw\[(\d+)\]\s*&\s*(0x[0-9a-fA-F]+|\d+)', body):
name = m.group(1)
offset = int(m.group(2))
@@ -196,6 +196,24 @@ def parse_python_data_packet_fields(filepath: Path | None = None) -> list[DataPa
name=name, byte_start=offset, byte_end=offset, width_bits=1
))
# Match intermediate variable pattern: var = raw[N], then field = var & MASK
for m in re.finditer(r'(\w+)\s*=\s*raw\[(\d+)\]', body):
var_name = m.group(1)
offset = int(m.group(2))
# Find fields derived from this intermediate variable
for m2 in re.finditer(
rf'(\w+)\s*=\s*(?:\({var_name}\s*>>\s*\d+\)\s*&|{var_name}\s*&)\s*'
r'(0x[0-9a-fA-F]+|\d+)',
body,
):
name = m2.group(1)
# Skip if already captured by direct raw[] access pattern
if not any(f.name == name for f in fields):
fields.append(DataPacketField(
name=name, byte_start=offset, byte_end=offset,
width_bits=1
))
fields.sort(key=lambda f: f.byte_start)
return fields
@@ -584,12 +602,28 @@ def parse_verilog_data_mux(
for m in re.finditer(
r"5'd(\d+)\s*:\s*data_pkt_byte\s*=\s*(.+?);",
mux_body
mux_body, re.DOTALL
):
idx = int(m.group(1))
expr = m.group(2).strip()
entries.append((idx, expr))
# Helper: extract the dominant signal name from a mux expression.
# Handles direct refs like ``range_profile_cap[31:24]``, ternaries
# like ``stream_doppler_en ? doppler_real_cap[15:8] : 8'd0``, and
# concat-ternaries like ``stream_cfar_en ? {…, cfar_detection_cap} : …``.
def _extract_signal(expr: str) -> str | None:
# If it's a ternary, use the true-branch to find the data signal
tern = re.match(r'\w+\s*\?\s*(.+?)\s*:\s*.+', expr, re.DOTALL)
target = tern.group(1) if tern else expr
# Look for a known data signal (xxx_cap pattern or cfar_detection_cap)
cap_match = re.search(r'(\w+_cap)\b', target)
if cap_match:
return cap_match.group(1)
# Fall back to first identifier before a bit-select
sig_match = re.match(r'(\w+?)(?:\[|$)', target)
return sig_match.group(1) if sig_match else None
# Group consecutive bytes by signal root name
fields: list[DataPacketField] = []
i = 0
@@ -599,22 +633,21 @@ def parse_verilog_data_mux(
i += 1
continue
# Extract signal name (e.g., range_profile_cap from range_profile_cap[31:24])
sig_match = re.match(r'(\w+?)(?:\[|$)', expr)
if not sig_match:
signal = _extract_signal(expr)
if not signal:
i += 1
continue
signal = sig_match.group(1)
start_byte = idx
end_byte = idx
# Find consecutive bytes of the same signal
j = i + 1
while j < len(entries):
next_idx, next_expr = entries[j]
if next_expr.startswith(signal):
end_byte = next_idx
_next_idx, next_expr = entries[j]
next_sig = _extract_signal(next_expr)
if next_sig == signal:
end_byte = _next_idx
j += 1
else:
break
9_Firmware/tests/cross_layer/tb_cross_layer_ft2232h.v
+4 -2
View File
@@ -620,8 +620,10 @@ module tb_cross_layer_ft2232h;
"Data pkt: byte 7 = 0x56 (doppler_imag MSB)");
check(captured_bytes[8] === 8'h78,
"Data pkt: byte 8 = 0x78 (doppler_imag LSB)");
check(captured_bytes[9] === 8'h01,
"Data pkt: byte 9 = 0x01 (cfar_detection=1)");
// Byte 9 = {frame_start, 6'b0, cfar_detection}
// After reset sample_counter==0, so frame_start=1 → 0x81
check(captured_bytes[9] === 8'h81,
"Data pkt: byte 9 = 0x81 (frame_start=1, cfar_detection=1)");
check(captured_bytes[10] === 8'h55,
"Data pkt: byte 10 = 0x55 (footer)");
9_Firmware/tests/cross_layer/test_cross_layer_contract.py
+870
View File
@@ -26,11 +26,14 @@ layers agree (because both could be wrong).
from __future__ import annotations
import ast
import os
import re
import struct
import subprocess
import tempfile
from pathlib import Path
from typing import ClassVar
import pytest
@@ -40,6 +43,7 @@ import sys
THIS_DIR = Path(__file__).resolve().parent
sys.path.insert(0, str(THIS_DIR))
import contract_parser as cp # noqa: E402
import adar1000_vm_reference as adar_vm # noqa: E402
# Also add the GUI dir to import radar_protocol
sys.path.insert(0, str(cp.GUI_DIR))
@@ -76,6 +80,78 @@ if _in_ci:
)
def _strip_cxx_comments_and_strings(src: str) -> str:
"""Return src with all C/C++ comments and string/char literals removed.
Tokenising state machine with four states:
* CODE — default; watches for `"`, `'`, `//`, `/*`
* STRING ("...") — handles `\\"` and `\\\\` escapes
* CHAR ('...') — handles `\\'` and `\\\\` escapes
* LINE_COMMENT — until next `\\n`
* BLOCK_COMMENT — until next `*/`
Used by test_vm_gain_table_is_not_reintroduced to ensure the substring
"VM_GAIN" appearing only inside an explanatory comment or a string
literal does NOT count as code reintroduction. We replace stripped
regions with a single space so token boundaries (and line counts, by
approximation — newlines preserved) are not collapsed.
"""
out: list[str] = []
i = 0
n = len(src)
CODE, STRING, CHAR, LINE_C, BLOCK_C = 0, 1, 2, 3, 4
state = CODE
while i < n:
c = src[i]
nxt = src[i + 1] if i + 1 < n else ""
if state == CODE:
if c == "/" and nxt == "/":
state = LINE_C
i += 2
elif c == "/" and nxt == "*":
state = BLOCK_C
i += 2
elif c == '"':
state = STRING
i += 1
elif c == "'":
state = CHAR
i += 1
else:
out.append(c)
i += 1
elif state == STRING:
if c == "\\" and i + 1 < n:
i += 2 # skip escape pair (handles \" and \\)
elif c == '"':
state = CODE
i += 1
else:
i += 1
elif state == CHAR:
if c == "\\" and i + 1 < n:
i += 2
elif c == "'":
state = CODE
i += 1
else:
i += 1
elif state == LINE_C:
if c == "\n":
out.append("\n") # preserve line numbering
state = CODE
i += 1
elif state == BLOCK_C:
if c == "*" and nxt == "/":
state = CODE
i += 2
else:
if c == "\n":
out.append("\n")
i += 1
return "".join(out)
def _parse_hex_results(text: str) -> list[dict[str, str]]:
"""Parse space-separated hex lines from TB output files."""
rows = []
@@ -369,6 +445,602 @@ class TestTier1ResetDefaults:
)
class TestTier1AgcCrossLayerInvariant:
"""
Verify AGC enable/disable is consistent across FPGA, MCU, and GUI layers.
System-level invariant: the FPGA register host_agc_enable is the single
source of truth for AGC state. It propagates to MCU via DIG_6 GPIO and
to GUI via status word 4 bit[11]. At boot, all layers must agree AGC=OFF.
At runtime, the MCU must read DIG_6 every frame to sync its outer-loop AGC.
"""
def test_fpga_dig6_drives_agc_enable(self):
"""FPGA must drive gpio_dig6 from host_agc_enable, NOT tied low."""
rtl = (cp.FPGA_DIR / "radar_system_top.v").read_text()
# Must find: assign gpio_dig6 = host_agc_enable;
assert re.search(
r'assign\s+gpio_dig6\s*=\s*host_agc_enable\s*;', rtl
), "gpio_dig6 must be driven by host_agc_enable (not tied low)"
# Must NOT have the old tied-low pattern
assert not re.search(
r"assign\s+gpio_dig6\s*=\s*1'b0\s*;", rtl
), "gpio_dig6 must NOT be tied low — it carries AGC enable"
def test_fpga_agc_enable_boot_default_off(self):
"""FPGA host_agc_enable must reset to 0 (AGC off at boot)."""
v_defaults = cp.parse_verilog_reset_defaults()
assert "host_agc_enable" in v_defaults, (
"host_agc_enable not found in reset block"
)
assert v_defaults["host_agc_enable"] == 0, (
f"host_agc_enable reset default is {v_defaults['host_agc_enable']}, "
"expected 0 (AGC off at boot)"
)
def test_mcu_agc_constructor_default_off(self):
"""MCU ADAR1000_AGC constructor must default enabled=false."""
agc_cpp = (cp.MCU_LIB_DIR / "ADAR1000_AGC.cpp").read_text()
# The constructor initializer list must have enabled(false)
assert re.search(
r'enabled\s*\(\s*false\s*\)', agc_cpp
), "ADAR1000_AGC constructor must initialize enabled(false)"
assert not re.search(
r'enabled\s*\(\s*true\s*\)', agc_cpp
), "ADAR1000_AGC constructor must NOT initialize enabled(true)"
def test_mcu_reads_dig6_before_agc_gate(self):
"""MCU main loop must read DIG_6 GPIO to sync outerAgc.enabled."""
main_cpp = (cp.MCU_CODE_DIR / "main.cpp").read_text()
# DIG_6 must be read via HAL_GPIO_ReadPin
assert re.search(
r'HAL_GPIO_ReadPin\s*\(\s*FPGA_DIG6', main_cpp,
), "main.cpp must read DIG_6 GPIO via HAL_GPIO_ReadPin"
# outerAgc.enabled must be assigned from the DIG_6 reading
# (may be indirect via debounce variable like dig6_now)
assert re.search(
r'outerAgc\.enabled\s*=', main_cpp,
), "main.cpp must assign outerAgc.enabled from DIG_6 state"
def test_boot_invariant_all_layers_agc_off(self):
"""
At boot, all three layers must agree: AGC is OFF.
- FPGA: host_agc_enable resets to 0 -> DIG_6 low
- MCU: ADAR1000_AGC.enabled defaults to false
- GUI: reads status word 4 bit[11] = 0 -> reports MANUAL
"""
# FPGA
v_defaults = cp.parse_verilog_reset_defaults()
assert v_defaults.get("host_agc_enable") == 0
# MCU
agc_cpp = (cp.MCU_LIB_DIR / "ADAR1000_AGC.cpp").read_text()
assert re.search(r'enabled\s*\(\s*false\s*\)', agc_cpp)
# GUI: status word 4 bit[11] is host_agc_enable, which resets to 0.
# Verify the GUI parses bit[11] of status word 4 as the AGC flag.
gui_py = (cp.GUI_DIR / "radar_protocol.py").read_text()
assert re.search(
r'words\[4\].*>>\s*11|status_words\[4\].*>>\s*11',
gui_py,
), "GUI must parse AGC status from words[4] bit[11]"
def test_status_word4_agc_bit_matches_dig6_source(self):
"""
Status word 4 bit[11] and DIG_6 must both derive from host_agc_enable.
This guarantees the GUI status display can never lie about MCU AGC state.
"""
rtl = (cp.FPGA_DIR / "radar_system_top.v").read_text()
# DIG_6 driven by host_agc_enable
assert re.search(
r'assign\s+gpio_dig6\s*=\s*host_agc_enable\s*;', rtl
)
# Status word 4 must contain host_agc_enable (may be named
# status_agc_enable at the USB interface port boundary).
# Also verify the top-level wiring connects them.
usb_ft2232h = (cp.FPGA_DIR / "usb_data_interface_ft2232h.v").read_text()
usb_ft601 = (cp.FPGA_DIR / "usb_data_interface.v").read_text()
# USB interfaces use the port name status_agc_enable
found_in_ft2232h = "status_agc_enable" in usb_ft2232h
found_in_ft601 = "status_agc_enable" in usb_ft601
assert found_in_ft2232h or found_in_ft601, (
"status_agc_enable must appear in at least one USB interface's "
"status word to guarantee GUI status matches DIG_6"
)
# Verify top-level wiring: status_agc_enable port is connected
# to host_agc_enable (same signal that drives DIG_6)
assert re.search(
r'\.status_agc_enable\s*\(\s*host_agc_enable\s*\)', rtl
), (
"Top-level must wire .status_agc_enable(host_agc_enable) "
"so status word and DIG_6 derive from the same signal"
)
def test_mcu_dig6_debounce_guards_enable_assignment(self):
"""
MCU must apply a 2-frame confirmation debounce before mutating
outerAgc.enabled from DIG_6 reads. A naive assignment straight from
the latest GPIO sample would let a single-cycle glitch flip the AGC
state for one frame — defeating the debounce claim in the PR body.
"""
main_cpp = (cp.MCU_CODE_DIR / "main.cpp").read_text()
# (1) Current-frame DIG_6 sample must be captured in a local variable
# so it can be compared against the previous-frame value.
now_match = re.search(
r'(bool|int|uint8_t)\s+(\w*dig6\w*)\s*=\s*[^;]*?'
r'HAL_GPIO_ReadPin\s*\(\s*FPGA_DIG6[^;]*;',
main_cpp,
re.DOTALL,
)
assert now_match, (
"DIG_6 read must be stored in a local variable (e.g. `dig6_now`) "
"so the current sample can be compared against the previous frame"
)
now_var = now_match.group(2)
# (2) Previous-frame state must persist across iterations via static
# storage, and must default to false (matches FPGA boot: AGC off).
prev_match = re.search(
r'static\s+(bool|int|uint8_t)\s+(\w*dig6\w*)\s*=\s*(false|0)\s*;',
main_cpp,
)
assert prev_match, (
"A static previous-frame variable (e.g. "
"`static bool dig6_prev = false;`) must exist, initialized to "
"false so the debounce starts in sync with the FPGA boot default"
)
prev_var = prev_match.group(2)
assert prev_var != now_var, (
f"Current and previous DIG_6 variables must be distinct "
f"(both are '{now_var}')"
)
# (3) outerAgc.enabled assignment must be gated by now == prev.
guarded_assign = re.search(
rf'if\s*\(\s*{now_var}\s*==\s*{prev_var}\s*\)\s*\{{[^}}]*?'
rf'outerAgc\.enabled\s*=\s*{now_var}\s*;',
main_cpp,
re.DOTALL,
)
assert guarded_assign, (
f"`outerAgc.enabled = {now_var};` must be inside "
f"`if ({now_var} == {prev_var}) {{ ... }}` — the confirmation "
"guard that absorbs single-sample GPIO glitches. A naive "
"assignment without this guard reintroduces the glitch bug."
)
# (4) Previous-frame variable must advance each frame.
prev_update = re.search(
rf'{prev_var}\s*=\s*{now_var}\s*;',
main_cpp,
)
assert prev_update, (
f"`{prev_var} = {now_var};` must run each frame so the "
"debounce window slides forward; without it the guard is "
"stuck and enable changes never confirm"
)
# ===================================================================
# ADAR1000 channel→register round-trip invariant (issue #90)
# ===================================================================
#
# Ground-truth invariant crossing three system layers:
# Chip (datasheet) -> Driver (MCU helpers) -> Application (callers).
#
# For every logical element ch in {0,1,2,3} (hardware channels CH1..CH4),
# the round-trip
# caller_expr(ch) --> helper_offset(channel) * stride --> base + off
# must land on the physical register REG_CH{ch+1}_* defined in the ADI
# ADAR1000 register map parsed from ADAR1000_Manager.h.
#
# Catches:
# * #90 channel rotation regardless of which side is fixed (caller OR helper).
# * Wrong stride (e.g. phase written with stride 1 instead of 2).
# * Bad mask (e.g. `channel & 0x07`, `channel & 0x01`).
# * Wrong base register in a helper.
# * New setter added with mismatched convention.
# * Caller moved to a file the test no longer scans (fails loudly).
#
# Cannot be defeated by:
# * Renaming/refactoring helper layout: the setter coverage test
# (`test_helper_sites_exist_for_all_setters`) catches missing parse.
# * Changing 0x03 to 3 or adding a named constant: the offset is
# evaluated symbolically via AST, not matched by regex.
def _parse_adar_register_map(header_text):
"""Extract `#define REG_CHn_(RX|TX)_(GAIN|PHS_I|PHS_Q)` values."""
regs = {}
for m in re.finditer(
r"^#define\s+(REG_CH[1-4]_(?:RX|TX)_(?:GAIN|PHS_I|PHS_Q))\s+(0x[0-9A-Fa-f]+)",
header_text,
re.MULTILINE,
):
regs[m.group(1)] = int(m.group(2), 16)
return regs
def _safe_eval_int_expr(expr, **variables):
"""
Evaluate a small integer expression with +, -, *, &, |, ^, ~, <<, >>.
Python's & / | / ^ / ~ / << / >> have the same semantics as C for the
operand widths we care about here (uint8_t after the mask makes the
result fit in 0..3). No floating point, no function calls, no names
outside ``variables``.
SECURITY: ``expr`` MUST come from a trusted source -- specifically,
C/C++ source text under version control in this repository (e.g.
arguments parsed out of ``main.cpp``/``ADAR1000_AGC.cpp``). Although
the AST whitelist below rejects function calls, attribute access,
subscripts, and any name not in ``variables``, ``eval`` is still
invoked on the compiled tree. Do NOT pass user-supplied / network /
GUI input here.
"""
tree = ast.parse(expr, mode="eval")
allowed = (
ast.Expression, ast.BinOp, ast.UnaryOp, ast.Constant,
ast.Name, ast.Load,
ast.Add, ast.Sub, ast.Mult, ast.Mod, ast.FloorDiv,
ast.BitAnd, ast.BitOr, ast.BitXor,
ast.USub, ast.UAdd, ast.Invert,
ast.LShift, ast.RShift,
)
for node in ast.walk(tree):
if not isinstance(node, allowed):
raise ValueError(
f"disallowed AST node {type(node).__name__!s} in `{expr}`"
)
return eval(
compile(tree, "<expr>", "eval"),
{"__builtins__": {}},
variables,
)
def _extract_adar_helper_sites(manager_cpp, setter_names):
"""
For each setter, locate the body of ``void ADAR1000Manager::<setter>``
and return a list of (setter, base_register, offset_expr_c, stride)
for every ``REG_CHn_XXX + <expr>`` memory-address assignment.
"""
sites = []
for setter in setter_names:
m = re.search(
rf"void\s+ADAR1000Manager::{setter}\s*\([^)]*\)\s*\{{(.+?)^\}}",
manager_cpp,
re.MULTILINE | re.DOTALL,
)
if not m:
continue
body = m.group(1)
for access in re.finditer(
r"=\s*(REG_CH[1-4]_(?:RX|TX)_(?:GAIN|PHS_I|PHS_Q))\s*\+\s*([^;]+);",
body,
):
base = access.group(1)
rhs = access.group(2).strip()
# Trailing `* <integer>` = stride multiplier (2 for phase I/Q).
stride_match = re.match(r"(.+?)\s*\*\s*(\d+)\s*$", rhs)
if stride_match:
offset_expr = stride_match.group(1).strip()
stride = int(stride_match.group(2))
else:
offset_expr = rhs
stride = 1
sites.append((setter, base, offset_expr, stride))
return sites
# Method-definition line pattern: `[qualifier...] <ret-type> <Class>::<setter>(`
# Covers: plain `void X::f(`, `inline void X::f(`, `static bool X::f(`, etc.
_DEFN_RE = re.compile(
r"^\s*(?:inline\s+|static\s+|virtual\s+|constexpr\s+|explicit\s+)*"
r"(?:void|bool|uint\w+|int\w*|auto)\s+\S+::\w+\s*\("
)
def _extract_adar_caller_sites(sources, setter):
"""
Find every call ``<obj>.<setter>(dev, <channel_expr>, ...)`` across
``sources = [(filename, text), ...]``. Returns (filename, line_no,
channel_expr) for each. Skips function declarations/definitions.
Arg list up to matching `)`: restricted to a single line. All existing
call sites fit on one line; a future multi-line refactor would drop
callers from the scan, which the round-trip test surfaces loudly via
`assert callers` (rather than silently missing a site).
"""
out = []
call_re = re.compile(rf"\b{setter}\s*\(([^;]*?)\)\s*;")
for filename, text in sources:
for line_no, line in enumerate(text.splitlines(), start=1):
# Skip method definition / declaration lines.
if _DEFN_RE.match(line):
continue
cm = call_re.search(line)
if not cm:
continue
args = _split_top_level_commas(cm.group(1))
if len(args) < 2:
continue
channel_expr = args[1].strip()
out.append((filename, line_no, channel_expr))
return out
def _split_top_level_commas(text):
"""Split on commas that sit at paren-depth 0 (ignores nested calls)."""
parts, depth, cur = [], 0, []
for ch in text:
if ch == "(":
depth += 1
cur.append(ch)
elif ch == ")":
depth -= 1
cur.append(ch)
elif ch == "," and depth == 0:
parts.append("".join(cur))
cur = []
else:
cur.append(ch)
if cur:
parts.append("".join(cur))
return parts
class TestTier1Adar1000ChannelRegisterRoundTrip:
"""
Cross-layer round-trip: caller channel expr -> helper offset formula
-> physical register address must equal REG_CH{ch+1}_* for every
caller and every ch in {0,1,2,3}.
See module-level block comment above and upstream issue #90.
"""
_SETTERS = (
"adarSetRxPhase",
"adarSetTxPhase",
"adarSetRxVgaGain",
"adarSetTxVgaGain",
)
# Register base -> stride override. Parsed values of stride are
# trusted; this table is the independent ground truth for cross-check.
_EXPECTED_STRIDE: ClassVar[dict[str, int]] = {
"REG_CH1_RX_GAIN": 1,
"REG_CH1_TX_GAIN": 1,
"REG_CH1_RX_PHS_I": 2,
"REG_CH1_RX_PHS_Q": 2,
"REG_CH1_TX_PHS_I": 2,
"REG_CH1_TX_PHS_Q": 2,
}
@classmethod
def setup_class(cls):
cls.header_txt = (cp.MCU_LIB_DIR / "ADAR1000_Manager.h").read_text()
cls.manager_txt = (cp.MCU_LIB_DIR / "ADAR1000_Manager.cpp").read_text()
cls.reg_map = _parse_adar_register_map(cls.header_txt)
cls.helper_sites = _extract_adar_helper_sites(
cls.manager_txt, cls._SETTERS,
)
# Auto-discover every C++ TU under the MCU tree so a new caller
# added to e.g. a future ``ADAR1000_Calibration.cpp`` cannot
# silently escape the round-trip check (issue #90 reviewer note).
# Exclude any path containing a ``tests`` segment so this test
# does not parse its own fixtures. The resulting list is
# deterministic (sorted) for reproducible parametrization.
scanned = []
seen = set()
for root in (cp.MCU_LIB_DIR, cp.MCU_CODE_DIR):
for path in sorted(root.rglob("*.cpp")):
if "tests" in path.parts:
continue
if path in seen:
continue
seen.add(path)
scanned.append((path.name, path.read_text()))
cls.sources = scanned
# Sanity: the two TUs known to call ADAR1000 setters at the time
# of issue #90 must be in scope. If a future refactor renames or
# moves them this assert fires loudly rather than silently
# passing an empty round-trip.
scanned_names = {n for (n, _) in scanned}
for required in ("ADAR1000_AGC.cpp", "main.cpp", "ADAR1000_Manager.cpp"):
assert required in scanned_names, (
f"Auto-discovery missed `{required}`; check MCU_LIB_DIR / "
f"MCU_CODE_DIR roots in contract_parser.py."
)
# ---------- Tier A: chip ground truth ----------------------------
def test_register_map_gain_stride_is_one_per_channel(self):
"""Datasheet invariant: RX/TX VGA gain registers are 1 byte apart."""
for kind in ("RX_GAIN", "TX_GAIN"):
for n in range(1, 4):
delta = (
self.reg_map[f"REG_CH{n+1}_{kind}"]
- self.reg_map[f"REG_CH{n}_{kind}"]
)
assert delta == 1, (
f"ADAR1000 register map invariant broken: "
f"REG_CH{n+1}_{kind} - REG_CH{n}_{kind} = {delta}, "
f"datasheet says 1. Either the header was mis-edited "
f"or ADI released a part with a different map."
)
def test_register_map_phase_stride_is_two_per_channel(self):
"""Datasheet invariant: phase I/Q pairs occupy 2 bytes per channel."""
for kind in ("RX_PHS_I", "RX_PHS_Q", "TX_PHS_I", "TX_PHS_Q"):
for n in range(1, 4):
delta = (
self.reg_map[f"REG_CH{n+1}_{kind}"]
- self.reg_map[f"REG_CH{n}_{kind}"]
)
assert delta == 2, (
f"ADAR1000 register map invariant broken: "
f"REG_CH{n+1}_{kind} - REG_CH{n}_{kind} = {delta}, "
f"datasheet says 2."
)
# ---------- Tier B: driver parses cleanly -------------------------
def test_helper_sites_exist_for_all_setters(self):
"""Every channel-indexed setter must parse at least one register access."""
found = {s for (s, _, _, _) in self.helper_sites}
missing = set(self._SETTERS) - found
assert not missing, (
f"Helper parse failed for: {sorted(missing)}. "
f"Either a setter was renamed (update _SETTERS), moved out of "
f"ADAR1000_Manager.cpp (extend scan scope), or the register-"
f"access form changed beyond `REG_CHn_XXX + <expr>`. "
f"DO NOT weaken this test without reviewing issue #90."
)
def test_helper_parsed_stride_matches_datasheet(self):
"""Parsed helper strides must match the datasheet register spacing."""
for setter, base, offset_expr, stride in self.helper_sites:
expected = self._EXPECTED_STRIDE.get(base)
assert expected is not None, (
f"{setter} writes to unrecognised base `{base}`. "
f"If ADI added a new channel-indexed register block, "
f"extend _EXPECTED_STRIDE with its datasheet stride."
)
assert stride == expected, (
f"{setter} helper uses stride {stride} for `{base}` "
f"(`{offset_expr} * {stride}`), datasheet says {expected}. "
f"Writes will overlap or skip channels."
)
# ---------- Tier C: round-trip to physical register ---------------
def test_all_callers_pass_one_based_channel(self):
"""
INVARIANT: every caller's channel argument must, for ch in
{0,1,2,3}, evaluate to a 1-based ADI channel index in {1,2,3,4}.
The bug fixed in #90 was that helpers used ``channel & 0x03``
directly, so a caller passing bare ``ch`` (0..3) appeared to
work for ch=0..2 and silently aliased ch=3 onto CH4-then-CH1.
After the fix, helpers do ``(channel - 1) & 0x03`` and reject
``channel < 1 || channel > 4``. A future caller written as
``adarSetRxPhase(dev, ch, ...)`` (bare 0-based) or
``adarSetRxPhase(dev, 0, ...)`` (literal 0) would silently be
dropped by the bounds-check at runtime; this test catches it at
CI time instead.
The check intentionally lives one tier above the round-trip test
so the failure message points the reader at the API contract
(1-based per ADI datasheet & ADAR1000_AGC.cpp:76) rather than at
a register-arithmetic mismatch.
"""
offenders = []
for setter in self._SETTERS:
callers = _extract_adar_caller_sites(self.sources, setter)
for filename, line_no, ch_expr in callers:
for ch in range(4):
try:
channel_val = _safe_eval_int_expr(ch_expr, ch=ch)
except (NameError, KeyError, ValueError) as e:
offenders.append(
f" - {filename}:{line_no} {setter}("
f"…, `{ch_expr}`, …) -- ch={ch}: "
f"unparseable ({e})"
)
continue
if channel_val not in (1, 2, 3, 4):
offenders.append(
f" - {filename}:{line_no} {setter}("
f"…, `{ch_expr}`, …) -- ch={ch}: "
f"channel={channel_val}, expected 1..4"
)
assert not offenders, (
"ADAR1000 1-based channel API contract violated. The fix "
"for issue #90 requires every caller to pass channel in "
"{1,2,3,4} (CH1..CH4 per ADI datasheet). Bare 0-based ch "
"or a literal 0 will be silently dropped by the helper's "
"bounds check. Offenders:\n" + "\n".join(offenders)
)
@pytest.mark.parametrize(
"setter",
[
"adarSetRxPhase",
"adarSetTxPhase",
"adarSetRxVgaGain",
"adarSetTxVgaGain",
],
)
def test_round_trip_lands_on_intended_physical_channel(self, setter):
"""
INVARIANT: for every caller of ``<setter>`` and every logical ch
in {0,1,2,3}, the effective register address equals
REG_CH{ch+1}_*. Catches #90 regardless of fix direction.
"""
callers = _extract_adar_caller_sites(self.sources, setter)
assert callers, (
f"No callers of `{setter}` found. Either the test scope is "
f"incomplete (extend `setup_class.sources`) or the symbol was "
f"inlined/removed. A blind test is a dangerous test — "
f"investigate before weakening."
)
helpers = [
(b, e, s) for (nm, b, e, s) in self.helper_sites if nm == setter
]
assert helpers, f"helper body for `{setter}` not parseable"
errors = []
for filename, line_no, ch_expr in callers:
for ch in range(4):
try:
channel_val = _safe_eval_int_expr(ch_expr, ch=ch)
except (NameError, KeyError, ValueError) as e:
pytest.fail(
f"{filename}:{line_no}: caller channel expression "
f"`{ch_expr}` uses symbol outside {{ch}} or a "
f"disallowed operator ({e}). Extend "
f"_safe_eval_int_expr variables or rewrite the "
f"call site with a supported expression."
)
for base_sym, offset_expr, stride in helpers:
try:
offset = _safe_eval_int_expr(
offset_expr, channel=channel_val,
)
except (NameError, KeyError, ValueError) as e:
pytest.fail(
f"helper `{setter}` offset expr "
f"`{offset_expr}` uses symbol outside "
f"{{channel}} or a disallowed operator ({e}). "
f"Extend _safe_eval_int_expr variables if new "
f"driver state is introduced."
)
final = self.reg_map[base_sym] + offset * stride
expected_sym = base_sym.replace("CH1", f"CH{ch + 1}")
expected = self.reg_map[expected_sym]
if final != expected:
errors.append(
f" - {filename}:{line_no} {setter} "
f"caller `{ch_expr}` | ch={ch} -> "
f"channel={channel_val} -> "
f"`{base_sym} + ({offset_expr})"
f"{' * ' + str(stride) if stride != 1 else ''}`"
f" = 0x{final:03X} "
f"(expected {expected_sym} = 0x{expected:03X})"
)
assert not errors, (
f"ADAR1000 channel round-trip FAILED for {setter} "
f"({len(errors)} mismatches) — writes routed to wrong physical "
f"channel. This is issue #90.\n" + "\n".join(errors)
)
class TestTier1DataPacketLayout:
"""Verify data packet byte layout matches between Python and Verilog."""
@@ -482,6 +1154,204 @@ class TestTier1STM32SettingsPacket:
assert flag == [23, 46, 158, 237], f"Start flag: {flag}"
# ===================================================================
# TIER 2: ADAR1000 Vector Modulator Lookup-Table Ground Truth
# ===================================================================
#
# Cross-layer contract: the firmware constants
# ADAR1000Manager::VM_I[128] / VM_Q[128]
# (in 9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp)
# MUST equal the byte values published in the ADAR1000 datasheet Rev. B,
# Tables 13-16 page 34 ("Phase Shifter Programming"), on a uniform 2.8125 deg
# grid (index N == phase N * 360/128 deg).
#
# Independent ground truth lives in tools/verify_adar1000_vm_tables.py
# (transcribed from the datasheet, cross-checked against the ADI Linux
# beamformer driver as a secondary source). This test imports that
# reference and asserts a byte-exact match.
#
# Historical bug guarded against: from initial commit through PR #94 the
# arrays shipped as empty placeholders ("// ... (same as in your original
# file)"), so every adarSetRxPhase / adarSetTxPhase call wrote I=Q=0 and
# beam steering was non-functional. A separate VM_GAIN[128] table was
# declared but never read anywhere; this test also enforces its removal so
# it cannot be reintroduced and silently shadow real bugs.
class TestTier2Adar1000VmTableGroundTruth:
"""Firmware ADAR1000 VM_I/VM_Q must match datasheet ground truth byte-exact."""
@pytest.fixture(scope="class")
def cpp_source(self):
path = (
cp.REPO_ROOT
/ "9_Firmware"
/ "9_1_Microcontroller"
/ "9_1_1_C_Cpp_Libraries"
/ "ADAR1000_Manager.cpp"
)
assert path.is_file(), f"Firmware source missing: {path}"
return path.read_text()
def test_ground_truth_table_shape(self):
"""Sanity-check the imported reference (defends against import-path mishap)."""
gt = adar_vm.GROUND_TRUTH
assert len(gt) == 128, "Ground-truth table must have exactly 128 entries"
# Each row is (deg_int, deg_frac_e4, vm_i_byte, vm_q_byte)
for k, row in enumerate(gt):
assert len(row) == 4, f"Row {k} malformed: {row}"
assert 0 <= row[2] <= 0xFF, f"VM_I[{k}] out of byte range: {row[2]:#x}"
assert 0 <= row[3] <= 0xFF, f"VM_Q[{k}] out of byte range: {row[3]:#x}"
# Byte format: bits[7:6] reserved zero, bits[5] polarity, bits[4:0] mag
assert (row[2] & 0xC0) == 0, f"VM_I[{k}] reserved bits set: {row[2]:#x}"
assert (row[3] & 0xC0) == 0, f"VM_Q[{k}] reserved bits set: {row[3]:#x}"
def test_ground_truth_byte_format(self):
"""Transcription self-check: every VM_I/VM_Q byte has reserved bits clear."""
errors = adar_vm.check_byte_format("VM_I_REF", adar_vm.VM_I_REF)
errors += adar_vm.check_byte_format("VM_Q_REF", adar_vm.VM_Q_REF)
assert not errors, (
"Byte-format violations in embedded GROUND_TRUTH (likely transcription "
"typo from ADAR1000 datasheet Tables 13-16):\n " + "\n ".join(errors)
)
def test_ground_truth_uniform_2p8125_deg_grid(self):
"""Transcription self-check: angles form a uniform 2.8125 deg grid.
This is the assumption that lets the firmware use `VM_*[phase % 128]`
as a direct index (no nearest-neighbour search). If the embedded
angles drift off the grid, the firmware's indexing model is wrong.
"""
errors = adar_vm.check_uniform_2p8125_deg_step()
assert not errors, (
"Non-uniform angle grid in GROUND_TRUTH:\n " + "\n ".join(errors)
)
def test_ground_truth_quadrant_symmetry(self):
"""Transcription self-check: phi and phi+180 deg have same magnitude,
opposite polarity. Catches swapped/rotated rows in the table.
"""
errors = adar_vm.check_quadrant_symmetry()
assert not errors, (
"Quadrant-symmetry violation in GROUND_TRUTH (table rows may be "
"transposed or mis-transcribed):\n " + "\n ".join(errors)
)
def test_ground_truth_cardinal_points(self):
"""Transcription self-check: the four cardinal phases (0, 90, 180,
270 deg) match the datasheet-published extrema exactly.
"""
errors = adar_vm.check_cardinal_points()
assert not errors, (
"Cardinal-point mismatch in GROUND_TRUTH vs ADAR1000 datasheet "
"Tables 13-16:\n " + "\n ".join(errors)
)
def test_firmware_vm_i_matches_datasheet(self, cpp_source):
gt = adar_vm.GROUND_TRUTH
firmware = adar_vm.parse_array(cpp_source, "VM_I")
assert firmware is not None, (
"Could not parse VM_I[128] from ADAR1000_Manager.cpp; "
"definition pattern may have drifted"
)
assert len(firmware) == 128, (
f"VM_I has {len(firmware)} entries, expected 128. "
"Empty placeholder regression — every phase write would emit I=0 "
"and beam steering would be silently broken."
)
mismatches = [
(k, firmware[k], gt[k][2])
for k in range(128)
if firmware[k] != gt[k][2]
]
assert not mismatches, (
f"VM_I diverges from datasheet at {len(mismatches)} indices; "
f"first 5: {mismatches[:5]}"
)
def test_firmware_vm_q_matches_datasheet(self, cpp_source):
gt = adar_vm.GROUND_TRUTH
firmware = adar_vm.parse_array(cpp_source, "VM_Q")
assert firmware is not None, (
"Could not parse VM_Q[128] from ADAR1000_Manager.cpp; "
"definition pattern may have drifted"
)
assert len(firmware) == 128, (
f"VM_Q has {len(firmware)} entries, expected 128. "
"Empty placeholder regression — every phase write would emit Q=0."
)
mismatches = [
(k, firmware[k], gt[k][3])
for k in range(128)
if firmware[k] != gt[k][3]
]
assert not mismatches, (
f"VM_Q diverges from datasheet at {len(mismatches)} indices; "
f"first 5: {mismatches[:5]}"
)
def test_vm_gain_table_is_not_reintroduced(self, cpp_source):
"""Dead-code regression guard: VM_GAIN[128] must not exist as code.
The ADAR1000 vector modulator has no separate gain register; magnitude
is bits[4:0] of the I/Q bytes themselves. Per-channel VGA gain uses
registers CHx_RX_GAIN (0x10-0x13) / CHx_TX_GAIN (0x1C-0x1F) written
directly by adarSetRxVgaGain / adarSetTxVgaGain. A VM_GAIN[] array
was declared in early development, never populated, never read, and
was removed in PR fix/adar1000-vm-tables. Reintroducing it would
suggest (falsely) that an extra lookup is needed and could mask the
real signal path.
Uses a tokenising comment/string stripper so that the historical
explanation comment in the cpp file, as well as any string literal
containing the substring "VM_GAIN", does not trip the check.
"""
stripped = _strip_cxx_comments_and_strings(cpp_source)
assert "VM_GAIN" not in stripped, (
"VM_GAIN symbol reappeared in ADAR1000_Manager.cpp executable code. "
"This array has no hardware backing and must not be reintroduced. "
"If you need to scale phase-state magnitude, modify VM_I/VM_Q "
"bits[4:0] directly per the datasheet."
)
def test_adversarial_corruption_is_detected(self):
"""Adversarial self-test: a flipped byte in firmware MUST fail comparison.
Defends against silent bypass — e.g. a future refactor that mocks
parse_array() or compares len() only. We synthesise a corrupted cpp
source string, run the same parser, and assert mismatch is detected.
"""
gt = adar_vm.GROUND_TRUTH
# Build a minimal valid-looking cpp snippet with one corrupted byte.
good_i = ", ".join(f"0x{gt[k][2]:02X}" for k in range(128))
good_q = ", ".join(f"0x{gt[k][3]:02X}" for k in range(128))
snippet_good = (
f"const uint8_t ADAR1000Manager::VM_I[128] = {{ {good_i} }};\n"
f"const uint8_t ADAR1000Manager::VM_Q[128] = {{ {good_q} }};\n"
)
# Sanity: the unmodified snippet must parse and match.
parsed_i = adar_vm.parse_array(snippet_good, "VM_I")
assert parsed_i is not None and len(parsed_i) == 128
assert all(parsed_i[k] == gt[k][2] for k in range(128)), (
"Self-test setup error: golden snippet does not match GROUND_TRUTH"
)
# Now flip the low bit of VM_I[42] and confirm detection.
corrupted_byte = gt[42][2] ^ 0x01
bad_i = ", ".join(
f"0x{(corrupted_byte if k == 42 else gt[k][2]):02X}"
for k in range(128)
)
snippet_bad = (
f"const uint8_t ADAR1000Manager::VM_I[128] = {{ {bad_i} }};\n"
f"const uint8_t ADAR1000Manager::VM_Q[128] = {{ {good_q} }};\n"
)
parsed_bad = adar_vm.parse_array(snippet_bad, "VM_I")
assert parsed_bad is not None and len(parsed_bad) == 128
assert parsed_bad[42] != gt[42][2], (
"Adversarial self-test FAILED: corrupted byte at index 42 was "
"not detected by parse_array. The cross-layer test is bypassable."
)
# ===================================================================
# TIER 2: Verilog Cosimulation
# ===================================================================
9_Firmware/tests/cross_layer/test_ddc_cosim_fuzz.py
+185
View File
@@ -0,0 +1,185 @@
"""
DDC Cosim Fuzz Runner (audit F-3.2)
===================================
Parameterized seed sweep over the existing DDC cosim testbench.
For each seed the runner:
1. Generates a random plausible radar scene (1-4 targets, random range /
velocity / RCS, random noise level) via tb/cosim/radar_scene.py, using
the seed for full determinism.
2. Writes a temporary ADC hex file.
3. Compiles tb_ddc_cosim.v with -DSCENARIO_FUZZ (once, cached across seeds)
and runs vvp with +hex, +csv, +tag plusargs.
4. Parses the RTL output CSV and checks:
- non-empty output (the pipeline produced baseband samples)
- all I/Q values are within signed-18-bit range
- no NaN / parse errors
- sample count is within the expected bound from CIC decimation ratio
The intent is liveness / crash-fuzz, not bit-exact cross-check. Bit-exact
validation is covered by the static scenarios (single_target, multi_target,
etc) in the existing suite. Fuzz complements that by surfacing edge-case
corruption, saturation, or overflow on random-but-valid inputs.
Marks:
- The default fuzz sweep uses 8 seeds for fast CI.
- Use `-m slow` to unlock the full 100-seed sweep matched to the audit ask.
Compile + run times per seed on a laptop with iverilog 13: ~6 s. The default
8-seed sweep fits in a ~1 minute pytest run; the 100-seed sweep takes ~10-12
minutes.
"""
from __future__ import annotations
import os
import random
import subprocess
import sys
import tempfile
from pathlib import Path
import pytest
THIS_DIR = Path(__file__).resolve().parent
REPO_ROOT = THIS_DIR.parent.parent.parent
FPGA_DIR = REPO_ROOT / "9_Firmware" / "9_2_FPGA"
COSIM_DIR = FPGA_DIR / "tb" / "cosim"
sys.path.insert(0, str(COSIM_DIR))
import radar_scene # noqa: E402
FAST_SEEDS = list(range(8))
SLOW_SEEDS = list(range(100))
# Pipeline constants
N_ADC_SAMPLES = 16384
CIC_DECIMATION = 4
FIR_DECIMATION = 1
EXPECTED_BB_MIN = N_ADC_SAMPLES // (CIC_DECIMATION * 4) # pessimistic lower bound
EXPECTED_BB_MAX = N_ADC_SAMPLES // CIC_DECIMATION # upper bound before FIR drain
SIGNED_18_MIN = -(1 << 17)
SIGNED_18_MAX = (1 << 17) - 1
SOURCE_FILES = [
"tb/tb_ddc_cosim.v",
"ddc_400m.v",
"nco_400m_enhanced.v",
"cic_decimator_4x_enhanced.v",
"fir_lowpass.v",
"cdc_modules.v",
]
@pytest.fixture(scope="module")
def compiled_fuzz_vvp(tmp_path_factory):
"""Compile tb_ddc_cosim.v once per pytest session with SCENARIO_FUZZ."""
iverilog = _iverilog_bin()
if not iverilog:
pytest.skip("iverilog not available on PATH")
out_dir = tmp_path_factory.mktemp("ddc_fuzz_build")
vvp = out_dir / "tb_ddc_cosim_fuzz.vvp"
sources = [str(FPGA_DIR / p) for p in SOURCE_FILES]
cmd = [
iverilog, "-g2001", "-DSIMULATION", "-DSCENARIO_FUZZ",
"-o", str(vvp), *sources,
]
res = subprocess.run(cmd, cwd=FPGA_DIR, capture_output=True, text=True, check=False)
if res.returncode != 0:
pytest.skip(f"iverilog compile failed:\n{res.stderr}")
return vvp
def _iverilog_bin() -> str | None:
from shutil import which
return which("iverilog")
def _random_scene(seed: int) -> list[radar_scene.Target]:
rng = random.Random(seed)
n = rng.randint(1, 4)
return [
radar_scene.Target(
range_m=rng.uniform(50, 1500),
velocity_mps=rng.uniform(-40, 40),
rcs_dbsm=rng.uniform(-10, 20),
phase_deg=rng.uniform(0, 360),
)
for _ in range(n)
]
def _run_seed(seed: int, vvp: Path, work: Path) -> tuple[int, list[tuple[int, int]]]:
"""Generate stimulus, run the DUT, return (bb_sample_count, [(i,q)...])."""
targets = _random_scene(seed)
noise = random.Random(seed ^ 0xA5A5).uniform(0.5, 6.0)
adc = radar_scene.generate_adc_samples(
targets, N_ADC_SAMPLES, noise_stddev=noise, seed=seed
)
hex_path = work / f"adc_fuzz_{seed:04d}.hex"
csv_path = work / f"rtl_bb_fuzz_{seed:04d}.csv"
radar_scene.write_hex_file(str(hex_path), adc, bits=8)
vvp_bin = _vvp_bin()
if not vvp_bin:
pytest.skip("vvp not available")
cmd = [
vvp_bin, str(vvp),
f"+hex={hex_path}",
f"+csv={csv_path}",
f"+tag=seed{seed:04d}",
]
res = subprocess.run(cmd, cwd=FPGA_DIR, capture_output=True, text=True, check=False, timeout=120)
assert res.returncode == 0, f"vvp exit={res.returncode}\nstdout:\n{res.stdout}\nstderr:\n{res.stderr}"
assert csv_path.exists(), (
f"vvp completed rc=0 but CSV was not produced at {csv_path}\n"
f"cmd: {cmd}\nstdout:\n{res.stdout[-2000:]}\nstderr:\n{res.stderr[-500:]}"
)
rows = []
with csv_path.open() as fh:
header = fh.readline()
assert "baseband_i" in header and "baseband_q" in header, f"unexpected CSV header: {header!r}"
for line in fh:
parts = line.strip().split(",")
if len(parts) != 3:
continue
_, i_str, q_str = parts
rows.append((int(i_str), int(q_str)))
return len(rows), rows
def _vvp_bin() -> str | None:
from shutil import which
return which("vvp")
def _fuzz_assertions(seed: int, rows: list[tuple[int, int]]) -> None:
n = len(rows)
assert EXPECTED_BB_MIN <= n <= EXPECTED_BB_MAX, (
f"seed {seed}: bb sample count {n} outside [{EXPECTED_BB_MIN},{EXPECTED_BB_MAX}]"
)
for idx, (i, q) in enumerate(rows):
assert SIGNED_18_MIN <= i <= SIGNED_18_MAX, (
f"seed {seed} row {idx}: baseband_i={i} out of signed-18 range"
)
assert SIGNED_18_MIN <= q <= SIGNED_18_MAX, (
f"seed {seed} row {idx}: baseband_q={q} out of signed-18 range"
)
all_zero = all(i == 0 and q == 0 for i, q in rows)
assert not all_zero, f"seed {seed}: all-zero baseband output — pipeline likely stalled"
@pytest.mark.parametrize("seed", FAST_SEEDS)
def test_ddc_fuzz_fast(seed: int, compiled_fuzz_vvp: Path, tmp_path: Path) -> None:
_, rows = _run_seed(seed, compiled_fuzz_vvp, tmp_path)
_fuzz_assertions(seed, rows)
@pytest.mark.slow
@pytest.mark.parametrize("seed", SLOW_SEEDS)
def test_ddc_fuzz_full(seed: int, compiled_fuzz_vvp: Path, tmp_path: Path) -> None:
_, rows = _run_seed(seed, compiled_fuzz_vvp, tmp_path)
_fuzz_assertions(seed, rows)
CONTRIBUTING.md
+69 -100
View File
@@ -5,140 +5,109 @@ for getting a change reviewed and merged.
## Getting started
1. Fork the repository and create a topic branch from `develop`.
2. Keep generated outputs (Vivado projects, bitstreams, build logs)
out of version control — the `.gitignore` already covers most of
these.
1. Fork the repository and create a topic branch from `develop`. The `main` branch is for production releases only.
2. Keep generated outputs (Vivado projects, bitstreams, build logs) out of version control.
### Security Mandate: Package Installation
Due to supply chain attack risks, **ALL package installations MUST use the `sfw` (secure firewall) prefix**.
- Python: `sfw uv pip install <package>` (Do not use raw pip)
- Node/JS: `sfw npm install <package>`
- Rust/Cargo: `sfw cargo <command>`
Never run bare package installation commands without the `sfw` prefix.
## Repository layout
| Path | Contents |
|------|----------|
| `4_Schematics and Boards Layout/` | KiCad schematics, Gerbers, BOM/CPL |
| `9_Firmware/9_1_Microcontroller/` | STM32 MCU C/C++ firmware and unit tests |
| `9_Firmware/9_2_FPGA/` | Verilog RTL, constraints, testbenches, build scripts |
| `9_Firmware/9_2_FPGA/formal/` | SymbiYosys formal-verification wrappers |
| `9_Firmware/9_2_FPGA/scripts/` | Vivado TCL build & debug scripts |
| `9_Firmware/9_3_GUI/` | Python radar dashboard (Tkinter + matplotlib) |
| `9_Firmware/9_3_GUI/` | Python radar dashboard (Tkinter/PyQt6) and CLI tools |
| `9_Firmware/tests/cross_layer/` | Python-based system invariant/contract tests |
| `docs/` | GitHub Pages documentation site |
## Before submitting a pull request
## Code Standards & Tooling
- **Python** — verify syntax: `python3 -m py_compile <file>`
- **Verilog** — if you have Vivado, run the relevant `build*.tcl`;
if not, note which scripts your change affects
- **Whitespace** — `git diff --check` should be clean
- Keep PRs focused: one logical change per PR is easier to review
- **Run the regression tests** (see below)
- **Python (GUI, Scripts, Tests)**:
- We use `uv` for dependency management.
- We strictly enforce linting with `ruff`. Run `uv run ruff check .` before committing.
- Test with `pytest`.
- **Verilog (FPGA)**:
- The RTL (`radar_system_top.v`) is the single source of truth for opcode values, bit widths, reset defaults, and valid ranges.
- Testbenches must include **adversarial validation**: actively test boundary conditions, race conditions, unexpected input sequences, and reset mid-operation.
- Use `iverilog` for simulation.
- **C/C++ (MCU)**:
- Use `make test` for host-side unit testing (cpputest).
- **System-Level Invariants**:
- Whenever adding code, verify that system-level invariants (across module, process, and chip boundaries) hold true.
## Running regression tests
## AI Usage Policy
After any change, run the relevant test suites to verify nothing is
broken. All commands assume you are at the repository root.
The use of AI is permitted but we have to make sure that the quality and control of the codebase doesn't depend on the agents but the maintainer pushing the changes, meaning they are fully responsible for the code they commit.
### Prerequisites
1. **Human Accountability** — The committing engineer is fully responsible for AI-generated code as if they wrote it. Every PR must be understood and defensible by a human.
2. **Mandatory Review** — No raw AI output may be committed unread. AI code must pass the same review bar as hand-written code.
3. **Full CI Before Commit** — All AI-assisted changes must pass the complete CI suite locally (lint, unit, regression, cross-layer) before commit.
| Tool | Used by | Install |
|------|---------|---------|
| [Icarus Verilog](http://iverilog.icarus.com/) (`iverilog`) | FPGA regression | `brew install icarus-verilog` / `apt install iverilog` |
| Python 3.8+ | GUI tests, co-sim | Usually pre-installed |
| GNU Make | MCU tests | Usually pre-installed |
| [SymbiYosys](https://symbiyosys.readthedocs.io/) (`sby`) | Formal verification | Optional — see SymbiYosys docs |
## Running the Test Suites
### FPGA regression (RTL lint + unit/integration/signal-processing tests)
We use GitHub Actions for CI, which runs four main jobs on every PR. Run these locally before pushing.
### 1. Python & Linting
```bash
uv run ruff check .
cd 9_Firmware/9_3_GUI
uv run pytest test_GUI_V65_Tk.py test_v7.py -v
```
### 2. FPGA Regression
```bash
cd 9_Firmware/9_2_FPGA
bash run_regression.sh
```
This runs five phases (Lint, Changed Modules, Integration, Signal Processing, Infrastructure, and **P0 Adversarial Tests**). All must pass.
This runs four phases:
| Phase | What it checks |
|-------|----------------|
| 0 — Lint | `iverilog -Wall` on all production RTL + static regex checks |
| 1 — Changed Modules | Unit tests for individual blocks (CIC, Doppler, CFAR, etc.) |
| 2 — Integration | DDC chain, receiver golden-compare, system-top, end-to-end |
| 3 — Signal Processing | FFT engine, NCO, FIR, matched filter chain |
| 4 — Infrastructure | CDC modules, edge detector, USB interface, range-bin decimator, mode controller |
All tests must pass (exit code 0). Advisory lint warnings (e.g., `case
without default`) are non-blocking.
### MCU unit tests
### 3. MCU Unit Tests
```bash
cd 9_Firmware/9_1_Microcontroller/tests
make clean && make all
make clean && make
```
Runs 20 C-based unit tests covering safety, bug-fix, and gap-3 tests.
Every test binary must exit 0.
### GUI / dashboard tests
### 4. Cross-Layer Contract Tests
```bash
cd 9_Firmware/9_3_GUI
python3 -m pytest test_GUI_V65_Tk.py -v
# or without pytest:
python3 -m unittest test_GUI_V65_Tk -v
uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py -v
```
57+ protocol and rendering tests. The `test_record_and_stop` test
requires `h5py` and will be skipped if it is not installed.
## Before merging: CI checklist
### Co-simulation (Python vs RTL golden comparison)
All PRs must pass CI:
Run from the co-sim directory after a successful FPGA regression (the
regression generates the RTL CSV outputs that the co-sim scripts compare
against):
| Job | What it checks |
|----|---------------|
| `python-tests` | ruff clean + pytest green |
| `mcu-tests` | make all exits 0 |
| `fpga-regression` | run_regression.sh exits 0 |
| `cross-layer-tests` | pytest exits 0 |
```bash
cd 9_Firmware/9_2_FPGA/tb/cosim
## Important Notes
# Validate all .mem files (twiddles, chirp ROMs, addressing)
python3 validate_mem_files.py
- **NO LEGACY COMPATIBILITY** unless explicitly requested by the maintainer.
- **The FPGA RTL (`radar_system_top.v`) is the single source of truth** for opcode values, bit widths, reset defaults, and valid ranges. All other layers must align to it.
- **Adversarial testing is mandatory**: Every test must actively try to break the code.
- **Testbench timing**: Always add a `#1` delay after `@(posedge clk)` before driving DUT inputs with blocking assignments.
- **Pre-fetch FIFO**: Remember `wr_full` is asserted after DEPTH+1 writes, not just DEPTH.
# DDC chain: RTL vs Python model (5 scenarios)
python3 compare.py dc
python3 compare.py single_target
python3 compare.py multi_target
python3 compare.py noise_only
python3 compare.py sine_1mhz
## Checklist Before Push
# Doppler processor: RTL vs golden reference
python3 compare_doppler.py stationary
# Matched filter: RTL vs Python model (4 scenarios)
python3 compare_mf.py all
```
Each script prints PASS/FAIL per scenario and exits non-zero on failure.
### Formal verification (optional)
Requires SymbiYosys (`sby`), Yosys, and a solver (z3 or boolector):
```bash
cd 9_Firmware/9_2_FPGA/formal
sby -f fv_doppler_processor.sby
sby -f fv_radar_mode_controller.sby
```
### Quick checklist
Before pushing, confirm:
1. `bash run_regression.sh` — all phases pass
2. `make all` (MCU tests) — 20/20 pass
3. `python3 -m unittest test_GUI_V65_Tk -v` — all pass
4. `python3 validate_mem_files.py` — all checks pass
5. `python3 compare.py dc && python3 compare_doppler.py stationary && python3 compare_mf.py all`
6. `git diff --check` — no whitespace issues
## Areas where help is especially welcome
See the list in [README.md](README.md#-contributing).
- [ ] `uv run ruff check .` — no lint errors
- [ ] `uv run pytest test_GUI_V65_Tk.py test_v7.py -v` — all pass
- [ ] `cd 9_Firmware/9_2_FPGA && bash run_regression.sh` — all 5 phases pass
- [ ] `cd 9_Firmware/9_1_Microcontroller/tests && make clean && make` — pass
- [ ] `uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py` — pass
- [ ] `git diff --check` — no whitespace issues
- [ ] PR targets `develop` branch
## Questions?
Open a GitHub issue — that way the discussion is visible to everyone.
Open a GitHub issue — discussion is visible to everyone.
README.md
+9 -9
View File
@@ -7,7 +7,6 @@
[![Frequency: 10.5GHz](https://img.shields.io/badge/Frequency-10.5GHz-blue)](https://github.com/NawfalMotii79/PLFM_RADAR)
[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg)](https://github.com/NawfalMotii79/PLFM_RADAR/pulls)
![AERIS-10 Radar System](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/3fb1dabf-2c6d-4b5d-b471-48bc461ce914.jpg)
AERIS-10 is an open-source, low-cost 10.5 GHz phased array radar system featuring Pulse Linear Frequency Modulated (LFM) modulation. Available in two versions (3km and 20km range), it's designed for researchers, drone developers, and serious SDR enthusiasts who want to explore and experiment with phased array radar technology.
@@ -47,13 +46,13 @@ The AERIS-10 main sub-systems are:
- **Main Board** containing:
- **DAC** - Generates the RADAR Chirps
- **2x Microwave Mixers (LT5552)** - For up-conversion and IF-down-conversion
- **2x Microwave Mixers (LTC5552)** - For up-conversion and IF-down-conversion
- **4x 4-Channel Phase Shifters (ADAR1000)** - For RX and TX chain beamforming
- **16x Front End Chips (ADTR1107)** - Used for both Low Noise Amplifying (RX) and Power Amplifying (TX) stages
- **XC7A50T FPGA** - Handles RADAR Signal Processing on the upstream FTG256 board:
- PLFM Chirps generation via the DAC
- Raw ADC data read
- Digital Gain Control (host-configurable gain shift)
- Hybrid Automatic Gain Control (AGC) — cross-layer FPGA/STM32/GUI loop
- I/Q Baseband Down-Conversion
- Decimation
- Filtering
@@ -68,13 +67,13 @@ The AERIS-10 main sub-systems are:
- Clock Generator (AD9523-1)
- 2x Frequency Synthesizers (ADF4382)
- 4x 4-Channel Phase Shifters (ADAR1000) for RADAR pulse sequencing
- 2x ADS7830 ADCs (on Power Amplifier Boards) for Idq measurement
- 2x DAC5578 (on Power Amplifier Boards) for Vg control
- GPS module for GUI map centering
- 2x ADS7830 8-channel I²C ADCs (Main Board, U88 @ 0x48 / U89 @ 0x4A) for 16x Idq measurement, one per PA channel, each sensed through a 5 mΩ shunt on the PA board and an INA241A3 current-sense amplifier (x50) on the Main Board
- 2x DAC5578 8-channel I²C DACs (Main Board, U7 @ 0x48 / U69 @ 0x49) for 16x Vg control, one per PA channel; closed-loop calibrated at boot to the target Idq
- GPS module (UM982) for GUI map centering and per-detection position tagging
- GY-85 IMU for pitch/roll correction of target coordinates
- BMP180 Barometer
- Stepper Motor
- 8x ADS7830 Temperature Sensors for cooling fan control
- 1x ADS7830 8-channel I²C ADC (Main Board, U10) reading 8 thermistors for thermal monitoring; a single GPIO (EN_DIS_COOLING) switches the cooling fans on when any channel exceeds the threshold
- RF switches
- **16x Power Amplifier Boards** - Used only for AERIS-10E version, featuring 10Watt QPA2962 GaN amplifier for extended range
@@ -92,7 +91,7 @@ The AERIS-10 main sub-systems are:
### Processing Pipeline
1. **Waveform Generation** - DAC creates LFM chirps
2. **Up/Down Conversion** - LT5552 mixers handle frequency translation
2. **Up/Down Conversion** - LTC5552 mixers handle frequency translation
3. **Beam Steering** - ADAR1000 phase shifters control 16 elements
4. **Signal Processing (FPGA)**:
- Raw ADC data capture
@@ -111,7 +110,8 @@ The AERIS-10 main sub-systems are:
- Map integration
- Radar control interface
![AERIS-10 GUI Demo](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/GUI_V6.gif)
![AERIS-10 Dashboard](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/GUI_V6.gif)
<!-- V6 GIF removed — V6 is deprecated. V65 Tk and V7 PyQt6 are the active GUIs. -->
## 📊 Technical Specifications
docs/index.html
+5
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@@ -32,6 +32,11 @@
</section>
<section class="stats-grid">
<article class="card stat notice">
<h2>Production Board USB</h2>
<p class="metric">FT2232H (USB 2.0)</p>
<p class="muted">50T production board uses FT2232H. FT601 USB 3.0 is available on 200T premium dev board only.</p>
</article>
<article class="card stat">
<h2>Tracked Timing Baseline</h2>
<p class="metric">WNS +0.058 ns</p>
pyproject.toml
+5
View File
@@ -19,6 +19,11 @@ dev = [
# ---------------------------------------------------------------------------
# Ruff configuration
# ---------------------------------------------------------------------------
[tool.pytest.ini_options]
markers = [
"slow: full-sweep tests (opt-in via -m slow); audit F-3.2 100-seed fuzz",
]
[tool.ruff]
target-version = "py312"
line-length = 100
uv.lock
Generated
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version = 1
revision = 1
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