fix: close all FPGA timing — CFAR pipeline + CIC reset path (Build 19)

CFAR pipeline fix (clk_100m WNS: -0.331ns → +0.156ns):
- Pre-register col_buf reads during ST_CFAR_THR pipeline stage
- 8 pipeline registers (4 values + 4 valids) break 15-level mux tree
- Delta wires use registered values, eliminating combinatorial depth

CIC reset path fix (clk_mmcm_out0 WNS: -0.074ns → +0.068ns):
- Add reset_h input port to cic_decimator_4x_enhanced.v
- Remove internal wire reset_h = ~reset_n (LUT1 inverter was root cause)
- Wire pre-registered reset_400m from ddc_400m.v into both CIC instances
- 3 sync reset blocks changed from if(!reset_n) to if(reset_h)

Build 19 results (xc7a50tftg256-2, Vivado 2025.2):
- All 5 clock domains timing met, 0 failing endpoints
- WNS: +0.068ns (400MHz), +0.156ns (100MHz), +0.627ns (120MHz)
- Utilization: 66.67% LUT, 22.36% FF, 74% BRAM, 93.33% DSP
- Bitstream: 2,140 KB

.gitattributes

@@ -0,0 +1,21 @@
+# Enforce LF line endings for all text files going forward.
+# Existing CRLF files are left as-is to avoid polluting git blame.
+* text=auto eol=lf
+
+# Binary files — ensure git doesn't mangle these
+*.npy binary
+*.h5 binary
+*.hdf5 binary
+*.png binary
+*.jpg binary
+*.pdf binary
+*.zip binary
+*.bin binary
+*.mem binary
+*.hex binary
+*.vvp binary
+*.s2p binary
+*.s3p binary
+*.step binary
+*.FCStd binary
+*.FCBak binary

.gitignore

@@ -32,6 +32,12 @@
 9_Firmware/9_2_FPGA/tb/cosim/rtl_doppler_*.csv
 9_Firmware/9_2_FPGA/tb/cosim/compare_doppler_*.csv
 9_Firmware/9_2_FPGA/tb/cosim/rtl_multiseg_*.csv
+9_Firmware/9_2_FPGA/tb/cosim/rx_final_doppler_out.csv
+9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_*.csv
+9_Firmware/9_2_FPGA/tb/cosim/compare_mf_*.csv
+
+# Golden reference outputs (regenerated by testbenches)
+9_Firmware/9_2_FPGA/tb/golden/
 
 # macOS
 .DS_Store
@@ -57,3 +63,17 @@ build*_reports/
 
 # UART capture logs (generated by tools/uart_capture.py)
 logs/
+
+# Local schematic files
+# Schematic and board files (untracked)
+4_Schematics and Boards Layout/4_6_Schematics/FMC_TestBoard/*
+4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.kicad_sch
+4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.kicad_pcb
+4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.bak
+4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.tmp
+4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.net
+4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.dcm
+4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.svg
+4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.pdf
+4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.sch-bak
+4_Schematics and Boards Layout/4_6_Schematics/Main_Board/backup/

8_Utils/Python/LUT.py

@@ -1,7 +1,10 @@
 import numpy as np
 
 # Define parameters
-fs = 120e6  # Sampling frequency
+# NOTE: This is a standalone LUT generation utility. The production chirp LUT
+# is generated by 9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py with
+# CHIRP_BW=20e6 (target: 30e6 Phase 1) and DAC_CLK=120e6.
+fs = 120e6  # Sampling frequency (DAC clock from AD9523 OUT10)
 Ts = 1 / fs  # Sampling time
 Tb = 1e-6  # Burst time
 Tau = 30e-6  # Pulse repetition time

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/RadarSettings.cpp

@@ -6,16 +6,16 @@ RadarSettings::RadarSettings() {
 }
 
 void RadarSettings::resetToDefaults() {
-    system_frequency = 10.0e9;    // 10 GHz
-    chirp_duration_1 = 30.0e-6;   // 30 �s
-    chirp_duration_2 = 0.5e-6;    // 0.5 �s
+    system_frequency = 10.5e9;    // 10.5 GHz (PLFM TX LO, ADF4382 config)
+    chirp_duration_1 = 30.0e-6;   // 30 µs
+    chirp_duration_2 = 0.5e-6;    // 0.5 µs
     chirps_per_position = 32;
     freq_min = 10.0e6;           // 10 MHz
     freq_max = 30.0e6;           // 30 MHz
     prf1 = 1000.0;               // 1 kHz
     prf2 = 2000.0;               // 2 kHz
-    max_distance = 50000.0;      // 50 km
-    map_size = 50000.0;          // 50 km
+    max_distance = 3072.0;       // 3072 m (512 bins × 6 m, 3 km mode)
+    map_size = 3072.0;           // 3072 m
     
     settings_valid = true;
 }
@@ -88,7 +88,7 @@ bool RadarSettings::validateSettings() {
     if (prf1 < 100 || prf1 > 10000) return false;
     if (prf2 < 100 || prf2 > 10000) return false;
     if (max_distance < 100 || max_distance > 100000) return false;
-    if (map_size < 1000 || map_size > 200000) return false;
+    if (map_size < 100 || map_size > 200000) return false;
     
     return true;
 }

9_Firmware/9_1_Microcontroller/tests/.gitignore

@@ -18,3 +18,10 @@ test_bug12_pa_cal_loop_inverted
 test_bug13_dac2_adc_buffer_mismatch
 test_bug14_diag_section_args
 test_bug15_htim3_dangling_extern
+test_agc_outer_loop
+test_gap3_emergency_state_ordering
+test_gap3_emergency_stop_rails
+test_gap3_idq_periodic_reread
+test_gap3_iwdg_config
+test_gap3_temperature_max
+test_gap3_overtemp_emergency_stop

9_Firmware/9_2_FPGA/cfar_ca.v

@@ -16,9 +16,9 @@
  *
  *   Phase 2 (CFAR): After frame_complete pulse from Doppler processor,
  *     process each Doppler column independently:
- *     a) Read 64 magnitudes from BRAM for one Doppler bin (ST_COL_LOAD)
+ *     a) Read 512 magnitudes from BRAM for one Doppler bin (ST_COL_LOAD)
  *     b) Compute initial sliding window sums (ST_CFAR_INIT)
- *     c) Slide CUT through all 64 range bins:
+ *     c) Slide CUT through all 512 range bins:
  *        - 3 sub-cycles per CUT:
  *          ST_CFAR_THR: register noise_sum (mode select + cross-multiply)
  *          ST_CFAR_MUL: compute alpha * noise_sum_reg in DSP
@@ -47,21 +47,23 @@
  *   typically clutter).
  *
  * Timing:
- *   Phase 2 takes ~(66 + T + 3*64) * 32 ≈ 8500 cycles per frame @ 100 MHz
- *   = 85 µs. Frame period @ PRF=1932 Hz, 32 chirps = 16.6 ms. Fits easily.
+ *   Phase 2 takes ~(514 + T + 3*512) * 32 ≈ 55000 cycles per frame @ 100 MHz
+ *   = 0.55 ms. Frame period @ PRF=1932 Hz, 32 chirps = 16.6 ms. Fits easily.
  *   (3 cycles per CUT due to pipeline: THR → MUL → CMP)
  *
  * Resources:
- *   - 1 BRAM18K for magnitude buffer (2048 x 17 bits)
+ *   - 1 BRAM36K for magnitude buffer (16384 x 17 bits)
  *   - 1 DSP48 for alpha multiply
  *   - ~300 LUTs for FSM + sliding window + comparators
  *
  * Clock domain: clk (100 MHz, same as Doppler processor)
  */
 
+`include "radar_params.vh"
+
 module cfar_ca #(
-    parameter NUM_RANGE_BINS   = 64,
-    parameter NUM_DOPPLER_BINS = 32,
+    parameter NUM_RANGE_BINS   = `RP_NUM_RANGE_BINS,    // 512
+    parameter NUM_DOPPLER_BINS = `RP_NUM_DOPPLER_BINS,  // 32
     parameter MAG_WIDTH        = 17,
     parameter ALPHA_WIDTH      = 8,
     parameter MAX_GUARD        = 8,
@@ -74,7 +76,7 @@ module cfar_ca #(
     input wire [31:0] doppler_data,
     input wire        doppler_valid,
     input wire [4:0]  doppler_bin_in,
-    input wire [5:0]  range_bin_in,
+    input wire [`RP_RANGE_BIN_BITS-1:0] range_bin_in,  // 9-bit
     input wire        frame_complete,
 
     // ========== CONFIGURATION ==========
@@ -88,7 +90,7 @@ module cfar_ca #(
     // ========== DETECTION OUTPUTS ==========
     output reg        detect_flag,
     output reg        detect_valid,
-    output reg [5:0]  detect_range,
+    output reg [`RP_RANGE_BIN_BITS-1:0] detect_range,  // 9-bit
     output reg [4:0]  detect_doppler,
     output reg [MAG_WIDTH-1:0] detect_magnitude,
     output reg [MAG_WIDTH-1:0] detect_threshold,
@@ -103,11 +105,11 @@ module cfar_ca #(
 // INTERNAL PARAMETERS
 // ============================================================================
 localparam TOTAL_CELLS = NUM_RANGE_BINS * NUM_DOPPLER_BINS;
-localparam ADDR_WIDTH  = 11;
+localparam ADDR_WIDTH  = `RP_CFAR_MAG_ADDR_W;  // 14
 localparam COL_BITS    = 5;
-localparam ROW_BITS    = 6;
-localparam SUM_WIDTH   = MAG_WIDTH + 6;  // 23 bits: sum of up to 64 magnitudes
-localparam PROD_WIDTH  = SUM_WIDTH + ALPHA_WIDTH;  // 31 bits
+localparam ROW_BITS    = `RP_RANGE_BIN_BITS;    // 9
+localparam SUM_WIDTH   = MAG_WIDTH + ROW_BITS;  // 26 bits: sum of up to 512 magnitudes
+localparam PROD_WIDTH  = SUM_WIDTH + ALPHA_WIDTH;  // 34 bits
 localparam ALPHA_FRAC_BITS = 4;  // Q4.4
 
 // ============================================================================
@@ -136,7 +138,7 @@ wire [15:0] abs_q = dop_q[15] ? (~dop_q + 16'd1) : dop_q;
 wire [MAG_WIDTH-1:0] cur_mag = {1'b0, abs_i} + {1'b0, abs_q};
 
 // ============================================================================
-// MAGNITUDE BRAM (2048 x 17 bits)
+// MAGNITUDE BRAM (16384 x 17 bits)
 // ============================================================================
 reg                    mag_we;
 reg [ADDR_WIDTH-1:0]   mag_waddr;
@@ -153,7 +155,7 @@ always @(posedge clk) begin
 end
 
 // ============================================================================
-// COLUMN LINE BUFFER (64 x 17 bits — distributed RAM)
+// COLUMN LINE BUFFER (512 x 17 bits — BRAM)
 // ============================================================================
 reg [MAG_WIDTH-1:0] col_buf [0:NUM_RANGE_BINS-1];
 reg [ROW_BITS:0] col_load_idx;
@@ -206,20 +208,31 @@ wire lead_rem_valid = (lead_rem_idx >= 0) && (lead_rem_idx < NUM_RANGE_BINS);
 wire lag_rem_valid  = (lag_rem_idx  >= 0) && (lag_rem_idx  < NUM_RANGE_BINS);
 wire lag_add_valid  = (lag_add_idx  >= 0) && (lag_add_idx  < NUM_RANGE_BINS);
 
-// Safe col_buf read with bounds checking (combinational)
+// Safe col_buf read with bounds checking (combinational — feeds pipeline regs)
 wire [MAG_WIDTH-1:0] lead_add_val = lead_add_valid ? col_buf[lead_add_idx[ROW_BITS-1:0]] : {MAG_WIDTH{1'b0}};
 wire [MAG_WIDTH-1:0] lead_rem_val = lead_rem_valid ? col_buf[lead_rem_idx[ROW_BITS-1:0]] : {MAG_WIDTH{1'b0}};
 wire [MAG_WIDTH-1:0] lag_rem_val  = lag_rem_valid  ? col_buf[lag_rem_idx[ROW_BITS-1:0]]  : {MAG_WIDTH{1'b0}};
 wire [MAG_WIDTH-1:0] lag_add_val  = lag_add_valid  ? col_buf[lag_add_idx[ROW_BITS-1:0]]  : {MAG_WIDTH{1'b0}};
 
-// Net deltas
-wire signed [SUM_WIDTH:0] lead_delta = (lead_add_valid ? $signed({1'b0, lead_add_val}) : 0)
-                                      - (lead_rem_valid ? $signed({1'b0, lead_rem_val}) : 0);
-wire signed [1:0] lead_cnt_delta = (lead_add_valid ? 1 : 0) - (lead_rem_valid ? 1 : 0);
+// ============================================================================
+// PIPELINE REGISTERS: Break col_buf mux tree out of ST_CFAR_CMP critical path
+// ============================================================================
+// Captured in ST_CFAR_THR (col_buf indices depend only on cut_idx/r_guard/r_train,
+// all stable during THR). Used in ST_CFAR_CMP for delta/sum computation.
+// This removes ~6-8 logic levels (9-level mux tree) from the CMP critical path.
+reg [MAG_WIDTH-1:0] lead_add_val_r, lead_rem_val_r;
+reg [MAG_WIDTH-1:0] lag_rem_val_r,  lag_add_val_r;
+reg                 lead_add_valid_r, lead_rem_valid_r;
+reg                 lag_rem_valid_r,  lag_add_valid_r;
 
-wire signed [SUM_WIDTH:0] lag_delta = (lag_add_valid ? $signed({1'b0, lag_add_val}) : 0)
-                                     - (lag_rem_valid ? $signed({1'b0, lag_rem_val}) : 0);
-wire signed [1:0] lag_cnt_delta = (lag_add_valid ? 1 : 0) - (lag_rem_valid ? 1 : 0);
+// Net deltas (computed from registered col_buf values — combinational in CMP)
+wire signed [SUM_WIDTH:0] lead_delta = (lead_add_valid_r ? $signed({1'b0, lead_add_val_r}) : 0)
+                                      - (lead_rem_valid_r ? $signed({1'b0, lead_rem_val_r}) : 0);
+wire signed [1:0] lead_cnt_delta = (lead_add_valid_r ? 1 : 0) - (lead_rem_valid_r ? 1 : 0);
+
+wire signed [SUM_WIDTH:0] lag_delta = (lag_add_valid_r ? $signed({1'b0, lag_add_val_r}) : 0)
+                                     - (lag_rem_valid_r ? $signed({1'b0, lag_rem_val_r}) : 0);
+wire signed [1:0] lag_cnt_delta = (lag_add_valid_r ? 1 : 0) - (lag_rem_valid_r ? 1 : 0);
 
 // ============================================================================
 // NOISE ESTIMATE COMPUTATION (combinational for CFAR mode selection)
@@ -267,7 +280,7 @@ always @(posedge clk or negedge reset_n) begin
         state          <= ST_IDLE;
         detect_flag    <= 1'b0;
         detect_valid   <= 1'b0;
-        detect_range   <= 6'd0;
+        detect_range   <= {ROW_BITS{1'b0}};
         detect_doppler <= 5'd0;
         detect_magnitude <= {MAG_WIDTH{1'b0}};
         detect_threshold <= {MAG_WIDTH{1'b0}};
@@ -288,6 +301,14 @@ always @(posedge clk or negedge reset_n) begin
         noise_sum_reg  <= 0;
         noise_product  <= 0;
         adaptive_thr   <= 0;
+        lead_add_val_r <= 0;
+        lead_rem_val_r <= 0;
+        lag_rem_val_r  <= 0;
+        lag_add_val_r  <= 0;
+        lead_add_valid_r <= 0;
+        lead_rem_valid_r <= 0;
+        lag_rem_valid_r  <= 0;
+        lag_add_valid_r  <= 0;
         r_guard        <= 4'd2;
         r_train        <= 5'd8;
         r_alpha        <= 8'h30;
@@ -364,7 +385,7 @@ always @(posedge clk or negedge reset_n) begin
                 if (r_enable) begin
                     col_idx      <= 0;
                     col_load_idx <= 0;
-                    mag_raddr    <= {6'd0, 5'd0};
+                    mag_raddr    <= {{ROW_BITS{1'b0}}, 5'd0};
                     state        <= ST_COL_LOAD;
                 end else begin
                     state <= ST_DONE;
@@ -382,14 +403,14 @@ always @(posedge clk or negedge reset_n) begin
 
             if (col_load_idx == 0) begin
                 // First address already presented, advance to range=1
-                mag_raddr    <= {6'd1, col_idx};
+                mag_raddr    <= {{{(ROW_BITS-1){1'b0}}, 1'b1}, col_idx};
                 col_load_idx <= 1;
             end else if (col_load_idx <= NUM_RANGE_BINS) begin
                 // Capture previous read
                 col_buf[col_load_idx - 1] <= mag_rdata;
 
                 if (col_load_idx < NUM_RANGE_BINS) begin
-                    mag_raddr <= {col_load_idx[ROW_BITS-1:0] + 6'd1, col_idx};
+                    mag_raddr <= {col_load_idx[ROW_BITS-1:0] + {{(ROW_BITS-1){1'b0}}, 1'b1}, col_idx};
                 end
 
                 col_load_idx <= col_load_idx + 1;
@@ -441,6 +462,19 @@ always @(posedge clk or negedge reset_n) begin
             cfar_status <= {4'd4, 1'b0, col_idx[2:0]};
 
             noise_sum_reg <= noise_sum_comb;
+
+            // Pipeline: register col_buf reads for next CUT's window update.
+            // Indices depend only on cut_idx/r_guard/r_train (all stable here).
+            // Breaks the 9-level col_buf mux tree out of ST_CFAR_CMP.
+            lead_add_val_r   <= lead_add_val;
+            lead_rem_val_r   <= lead_rem_val;
+            lag_rem_val_r    <= lag_rem_val;
+            lag_add_val_r    <= lag_add_val;
+            lead_add_valid_r <= lead_add_valid;
+            lead_rem_valid_r <= lead_rem_valid;
+            lag_rem_valid_r  <= lag_rem_valid;
+            lag_add_valid_r  <= lag_add_valid;
+
             state <= ST_CFAR_MUL;
         end
 
@@ -513,7 +547,7 @@ always @(posedge clk or negedge reset_n) begin
             if (col_idx < NUM_DOPPLER_BINS - 1) begin
                 col_idx      <= col_idx + 1;
                 col_load_idx <= 0;
-                mag_raddr    <= {6'd0, col_idx + 5'd1};
+                mag_raddr    <= {{ROW_BITS{1'b0}}, col_idx + 5'd1};
                 state        <= ST_COL_LOAD;
             end else begin
                 state <= ST_DONE;

9_Firmware/9_2_FPGA/chirp_memory_loader_param.v

@@ -4,10 +4,6 @@ module chirp_memory_loader_param #(
     parameter LONG_Q_FILE_SEG0 = "long_chirp_seg0_q.mem",
     parameter LONG_I_FILE_SEG1 = "long_chirp_seg1_i.mem",
     parameter LONG_Q_FILE_SEG1 = "long_chirp_seg1_q.mem",
-    parameter LONG_I_FILE_SEG2 = "long_chirp_seg2_i.mem",
-    parameter LONG_Q_FILE_SEG2 = "long_chirp_seg2_q.mem",
-    parameter LONG_I_FILE_SEG3 = "long_chirp_seg3_i.mem",
-    parameter LONG_Q_FILE_SEG3 = "long_chirp_seg3_q.mem",
     parameter SHORT_I_FILE = "short_chirp_i.mem",
     parameter SHORT_Q_FILE = "short_chirp_q.mem",
     parameter DEBUG = 1
@@ -17,17 +13,17 @@ module chirp_memory_loader_param #(
     input wire [1:0] segment_select,
     input wire mem_request,
     input wire use_long_chirp,
-    input wire [9:0] sample_addr,
+    input wire [10:0] sample_addr,
     output reg [15:0] ref_i,
     output reg [15:0] ref_q,
     output reg mem_ready
 );
 
-// Memory declarations - now 4096 samples for 4 segments
+// Memory declarations — 2 long segments × 2048 = 4096 samples
 (* ram_style = "block" *) reg [15:0] long_chirp_i [0:4095];
 (* ram_style = "block" *) reg [15:0] long_chirp_q [0:4095];
-(* ram_style = "block" *) reg [15:0] short_chirp_i [0:1023];
-(* ram_style = "block" *) reg [15:0] short_chirp_q [0:1023];
+(* ram_style = "block" *) reg [15:0] short_chirp_i [0:2047];
+(* ram_style = "block" *) reg [15:0] short_chirp_q [0:2047];
 
 // Initialize memory
 integer i;
@@ -35,66 +31,47 @@ integer i;
 initial begin
     `ifdef SIMULATION
     if (DEBUG) begin
-        $display("[MEM] Starting memory initialization for 4 long chirp segments");
+        $display("[MEM] Starting memory initialization for 2 long chirp segments");
     end
     `endif
-    
-    // === LOAD LONG CHIRP - 4 SEGMENTS ===
-    // Segment 0 (addresses 0-1023)
-    $readmemh(LONG_I_FILE_SEG0, long_chirp_i, 0, 1023);
-    $readmemh(LONG_Q_FILE_SEG0, long_chirp_q, 0, 1023);
+
+    // === LOAD LONG CHIRP — 2 SEGMENTS ===
+    // Segment 0 (addresses 0-2047)
+    $readmemh(LONG_I_FILE_SEG0, long_chirp_i, 0, 2047);
+    $readmemh(LONG_Q_FILE_SEG0, long_chirp_q, 0, 2047);
     `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 0 (0-1023)");
+    if (DEBUG) $display("[MEM] Loaded long chirp segment 0 (0-2047)");
     `endif
-    
-    // Segment 1 (addresses 1024-2047)
-    $readmemh(LONG_I_FILE_SEG1, long_chirp_i, 1024, 2047);
-    $readmemh(LONG_Q_FILE_SEG1, long_chirp_q, 1024, 2047);
+
+    // Segment 1 (addresses 2048-4095)
+    $readmemh(LONG_I_FILE_SEG1, long_chirp_i, 2048, 4095);
+    $readmemh(LONG_Q_FILE_SEG1, long_chirp_q, 2048, 4095);
     `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 1 (1024-2047)");
+    if (DEBUG) $display("[MEM] Loaded long chirp segment 1 (2048-4095)");
     `endif
-    
-    // Segment 2 (addresses 2048-3071)
-    $readmemh(LONG_I_FILE_SEG2, long_chirp_i, 2048, 3071);
-    $readmemh(LONG_Q_FILE_SEG2, long_chirp_q, 2048, 3071);
-    `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 2 (2048-3071)");
-    `endif
-    
-    // Segment 3 (addresses 3072-4095)
-    $readmemh(LONG_I_FILE_SEG3, long_chirp_i, 3072, 4095);
-    $readmemh(LONG_Q_FILE_SEG3, long_chirp_q, 3072, 4095);
-    `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 3 (3072-4095)");
-    `endif
-    
+
     // === LOAD SHORT CHIRP ===
-    // Load first 50 samples (0-49). Explicit range prevents iverilog warning
-    // about insufficient words for the full [0:1023] array.
+    // Load first 50 samples (0-49)
     $readmemh(SHORT_I_FILE, short_chirp_i, 0, 49);
     $readmemh(SHORT_Q_FILE, short_chirp_q, 0, 49);
     `ifdef SIMULATION
     if (DEBUG) $display("[MEM] Loaded short chirp (0-49)");
     `endif
-    
-    // Zero pad remaining 974 samples (50-1023)
-    for (i = 50; i < 1024; i = i + 1) begin
+
+    // Zero pad remaining samples (50-2047)
+    for (i = 50; i < 2048; i = i + 1) begin
         short_chirp_i[i] = 16'h0000;
         short_chirp_q[i] = 16'h0000;
     end
     `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Zero-padded short chirp from 50-1023");
-    
+    if (DEBUG) $display("[MEM] Zero-padded short chirp from 50-2047");
+
     // === VERIFICATION ===
     if (DEBUG) begin
         $display("[MEM] Memory loading complete. Verification samples:");
         $display("  Long[0]:     I=%h Q=%h", long_chirp_i[0], long_chirp_q[0]);
-        $display("  Long[1023]:  I=%h Q=%h", long_chirp_i[1023], long_chirp_q[1023]);
-        $display("  Long[1024]:  I=%h Q=%h", long_chirp_i[1024], long_chirp_q[1024]);
         $display("  Long[2047]:  I=%h Q=%h", long_chirp_i[2047], long_chirp_q[2047]);
         $display("  Long[2048]:  I=%h Q=%h", long_chirp_i[2048], long_chirp_q[2048]);
-        $display("  Long[3071]:  I=%h Q=%h", long_chirp_i[3071], long_chirp_q[3071]);
-        $display("  Long[3072]:  I=%h Q=%h", long_chirp_i[3072], long_chirp_q[3072]);
         $display("  Long[4095]:  I=%h Q=%h", long_chirp_i[4095], long_chirp_q[4095]);
         $display("  Short[0]:    I=%h Q=%h", short_chirp_i[0], short_chirp_q[0]);
         $display("  Short[49]:   I=%h Q=%h", short_chirp_i[49], short_chirp_q[49]);
@@ -104,8 +81,8 @@ initial begin
 end
 
 // Memory access logic
-// long_addr is combinational — segment_select[1:0] concatenated with sample_addr[9:0]
-wire [11:0] long_addr = {segment_select, sample_addr};
+// long_addr: segment_select[0] selects segment (0 or 1), sample_addr[10:0] selects within
+wire [11:0] long_addr = {segment_select[0], sample_addr};
 
 // ---- BRAM read block (sync-only, sync reset) ----
 // REQP-1839/1840 fix: BRAM output registers cannot have async resets.
@@ -119,7 +96,7 @@ always @(posedge clk) begin
         if (use_long_chirp) begin
             ref_i <= long_chirp_i[long_addr];
             ref_q <= long_chirp_q[long_addr];
-            
+
             `ifdef SIMULATION
             if (DEBUG && $time < 100) begin
                 $display("[MEM @%0t] Long chirp: seg=%b, addr=%d, I=%h, Q=%h",
@@ -128,10 +105,10 @@ always @(posedge clk) begin
             end
             `endif
         end else begin
-            // Short chirp (0-1023)
+            // Short chirp (0-2047)
             ref_i <= short_chirp_i[sample_addr];
             ref_q <= short_chirp_q[sample_addr];
-            
+
             `ifdef SIMULATION
             if (DEBUG && $time < 100) begin
                 $display("[MEM @%0t] Short chirp: addr=%d, I=%h, Q=%h",
@@ -151,4 +128,4 @@ always @(posedge clk or negedge reset_n) begin
     end
 end
 
-endmodule
+endmodule

9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v

@@ -1,6 +1,7 @@
 module cic_decimator_4x_enhanced (
     input wire clk,                 // 400MHz input clock
     input wire reset_n,
+    input wire reset_h,             // Pre-registered active-high reset from parent (avoids LUT1 inverter)
     input wire signed [17:0] data_in,  // 18-bit input
     input wire data_valid,
     output reg signed [17:0] data_out, // 18-bit output
@@ -32,11 +33,15 @@ localparam COMB_WIDTH = 28;
 // adjacent DSP48E1 tiles — zero fabric delay, guaranteed to meet 400+ MHz
 // on 7-series regardless of speed grade.
 //
-// Active-high reset derived from reset_n (inverted).
+// Active-high reset provided by parent module (pre-registered).
 // CEP (clock enable for P register) gated by data_valid.
 // ============================================================================
 
-wire reset_h = ~reset_n;  // active-high reset for DSP48E1 RSTP
+// reset_h is now an input port from parent module (pre-registered active-high).
+// Previously: wire reset_h = ~reset_n; — this LUT1 inverter + long routing to
+// 8 DSP48E1 RSTB pins was the root cause of 400 MHz timing failure (WNS=-0.074ns).
+// The parent ddc_400m.v already has a registered reset_400m derived from
+// the 2-stage sync reset, so we use that directly.
 
 // Sign-extended input for integrator_0 C port (48-bit)
 wire [ACC_WIDTH-1:0] data_in_c = {{(ACC_WIDTH-18){data_in[17]}}, data_in};
@@ -702,7 +707,7 @@ end
 // Sync reset: enables FDRE inference for better timing at 400 MHz.
 // Reset is already synchronous to clk via reset synchronizer in parent module.
 always @(posedge clk) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         integrator_sampled <= 0;
         decimation_counter <= 0;
         data_valid_delayed <= 0;
@@ -757,7 +762,7 @@ end
 // Pipeline the valid signal for comb section
 // Sync reset: matches decimation control block reset style.
 always @(posedge clk) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         data_valid_comb <= 0;
         data_valid_comb_pipe <= 0;
         data_valid_comb_0_out <= 0;
@@ -792,7 +797,7 @@ end
 //   - Each stage: comb[i] = comb[i-1] - comb_delay[i][last]
 
 always @(posedge clk) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         for (i = 0; i < STAGES; i = i + 1) begin
             comb[i] <= 0;
             for (j = 0; j < COMB_DELAY; j = j + 1) begin

9_Firmware/9_2_FPGA/ddc_400m.v

@@ -565,7 +565,8 @@ wire cic_valid_i, cic_valid_q;
 
 cic_decimator_4x_enhanced cic_i_inst (
     .clk(clk_400m),
-    .reset_n(reset_n_400m),
+    .reset_n(reset_n_400m),
+    .reset_h(reset_400m),
     .data_in(mixed_i[33:16]),
     .data_valid(mixed_valid),
     .data_out(cic_i_out),
@@ -574,7 +575,8 @@ cic_decimator_4x_enhanced cic_i_inst (
 
 cic_decimator_4x_enhanced cic_q_inst (
     .clk(clk_400m),
-    .reset_n(reset_n_400m),
+    .reset_n(reset_n_400m),
+    .reset_h(reset_400m),
     .data_in(mixed_q[33:16]),
     .data_valid(mixed_valid),
     .data_out(cic_q_out),

9_Firmware/9_2_FPGA/doppler_processor.v

@@ -32,13 +32,15 @@
 //     w[n] = 0.54 - 0.46 * cos(2*pi*n/15), n=0..15
 // ============================================================================
 
+`include "radar_params.vh"
+
 module doppler_processor_optimized #(
-    parameter DOPPLER_FFT_SIZE   = 16,     // FFT size per sub-frame (was 32)
-    parameter RANGE_BINS         = 64,
-    parameter CHIRPS_PER_FRAME   = 32,     // Total chirps in frame (16+16)
-    parameter CHIRPS_PER_SUBFRAME = 16,    // Chirps per sub-frame
+    parameter DOPPLER_FFT_SIZE   = `RP_DOPPLER_FFT_SIZE,    // 16
+    parameter RANGE_BINS         = `RP_NUM_RANGE_BINS,      // 512
+    parameter CHIRPS_PER_FRAME   = `RP_CHIRPS_PER_FRAME,    // 32
+    parameter CHIRPS_PER_SUBFRAME = `RP_CHIRPS_PER_SUBFRAME, // 16
     parameter WINDOW_TYPE        = 0,      // 0=Hamming, 1=Rectangular
-    parameter DATA_WIDTH         = 16
+    parameter DATA_WIDTH         = `RP_DATA_WIDTH           // 16
 )(
     input wire clk,
     input wire reset_n,
@@ -48,7 +50,7 @@ module doppler_processor_optimized #(
     output reg [31:0] doppler_output,
     output reg doppler_valid,
     output reg [4:0] doppler_bin,      // {sub_frame, bin[3:0]}
-    output reg [5:0] range_bin,
+    output reg [`RP_RANGE_BIN_BITS-1:0] range_bin,  // 9-bit
     output reg sub_frame,              // 0=long PRI, 1=short PRI
     output wire processing_active,
     output wire frame_complete,
@@ -57,16 +59,16 @@ module doppler_processor_optimized #(
 `ifdef FORMAL
     ,
     output wire [2:0]  fv_state,
-    output wire [10:0] fv_mem_write_addr,
-    output wire [10:0] fv_mem_read_addr,
-    output wire [5:0]  fv_write_range_bin,
+    output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_write_addr,
+    output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_read_addr,
+    output wire [`RP_RANGE_BIN_BITS-1:0]     fv_write_range_bin,
     output wire [4:0]  fv_write_chirp_index,
-    output wire [5:0]  fv_read_range_bin,
+    output wire [`RP_RANGE_BIN_BITS-1:0]     fv_read_range_bin,
     output wire [4:0]  fv_read_doppler_index,
     output wire [9:0]  fv_processing_timeout,
     output wire        fv_frame_buffer_full,
     output wire        fv_mem_we,
-    output wire [10:0] fv_mem_waddr_r
+    output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_waddr_r
 `endif
 );
 
@@ -115,9 +117,9 @@ localparam MEM_DEPTH = RANGE_BINS * CHIRPS_PER_FRAME;
 // ==============================================
 // Control Registers
 // ==============================================
-reg [5:0] write_range_bin;
+reg [`RP_RANGE_BIN_BITS-1:0] write_range_bin;
 reg [4:0] write_chirp_index;
-reg [5:0] read_range_bin;
+reg [`RP_RANGE_BIN_BITS-1:0] read_range_bin;
 reg [4:0] read_doppler_index;
 reg frame_buffer_full;
 reg [9:0] chirps_received;
@@ -147,8 +149,8 @@ wire fft_output_last;
 // ==============================================
 // Addressing
 // ==============================================
-wire [10:0] mem_write_addr;
-wire [10:0] mem_read_addr;
+wire [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_write_addr;
+wire [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_read_addr;
 
 assign mem_write_addr = (write_chirp_index * RANGE_BINS) + write_range_bin;
 assign mem_read_addr = (read_doppler_index * RANGE_BINS) + read_range_bin;
@@ -180,7 +182,7 @@ reg [9:0] processing_timeout;
 
 // Memory write enable and data signals
 reg mem_we;
-reg [10:0] mem_waddr_r;
+reg [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_waddr_r;
 reg [DATA_WIDTH-1:0] mem_wdata_i, mem_wdata_q;
 
 // Memory read data
@@ -531,6 +533,11 @@ xfft_16 fft_inst (
 // Status Outputs
 // ==============================================
 assign processing_active = (state != S_IDLE);
+// NOTE: frame_complete is a LEVEL, not a pulse. It is high whenever the
+// doppler processor is idle with no buffered frame. radar_receiver_final.v
+// converts this to a single-cycle rising-edge pulse before routing to
+// downstream consumers (USB FT2232H, AGC, CFAR). Do NOT connect this
+// level output directly to modules that expect a pulse.
 assign frame_complete = (state == S_IDLE && frame_buffer_full == 0);
 
 endmodule

9_Firmware/9_2_FPGA/fft_engine.v

@@ -28,13 +28,16 @@
  * Clock domain: single clock (clk), active-low async reset (reset_n).
  */
 
+// Include single source of truth for default parameters
+`include "radar_params.vh"
+
 module fft_engine #(
-    parameter N            = 1024,
-    parameter LOG2N        = 10,
+    parameter N            = `RP_FFT_SIZE,       // 2048
+    parameter LOG2N        = `RP_LOG2_FFT_SIZE,  // 11
     parameter DATA_W       = 16,
     parameter INTERNAL_W   = 32,
     parameter TWIDDLE_W    = 16,
-    parameter TWIDDLE_FILE = "fft_twiddle_1024.mem"
+    parameter TWIDDLE_FILE = "fft_twiddle_2048.mem"
 )(
     input wire clk,
     input wire reset_n,

9_Firmware/9_2_FPGA/fft_twiddle_2048.mem

@@ -0,0 +1,515 @@
+// Quarter-wave cosine ROM for 2048-point FFT
+// 512 entries, 16-bit signed Q15 ($readmemh format)
+// cos(2*pi*k/2048) for k = 0..511
+7FFF
+7FFF
+7FFE
+7FFE
+7FFD
+7FFB
+7FF9
+7FF7
+7FF5
+7FF3
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+0065

9_Firmware/9_2_FPGA/matched_filter_multi_segment.v

@@ -1,5 +1,8 @@
 `timescale 1ns / 1ps
 // matched_filter_multi_segment.v
+
+`include "radar_params.vh"
+
 module matched_filter_multi_segment (
     input wire clk,           // 100MHz
     input wire reset_n,
@@ -18,14 +21,13 @@ module matched_filter_multi_segment (
     input wire mc_new_elevation,    // Toggle for new elevation (32)
     input wire mc_new_azimuth,      // Toggle for new azimuth (50)
     
-    input wire [15:0] long_chirp_real,
-    input wire [15:0] long_chirp_imag,
-    input wire [15:0] short_chirp_real,
-    input wire [15:0] short_chirp_imag,
+    // Reference chirp (upstream memory loader selects long/short via use_long_chirp)
+    input wire [15:0] ref_chirp_real,
+    input wire [15:0] ref_chirp_imag,
     
     // Memory system interface
     output reg [1:0] segment_request,
-    output wire [9:0] sample_addr_out,  // Tell memory which sample we need
+    output wire [10:0] sample_addr_out,  // Tell memory which sample we need (11-bit for 2048)
     output reg mem_request,
     input wire mem_ready,
     
@@ -39,18 +41,18 @@ module matched_filter_multi_segment (
 );
 
 // ========== FIXED PARAMETERS ==========
-parameter BUFFER_SIZE = 1024;
-parameter LONG_CHIRP_SAMPLES = 3000;  // Still 3000 samples total
-parameter SHORT_CHIRP_SAMPLES = 50;   // 0.5�s @ 100MHz
-parameter OVERLAP_SAMPLES = 128;      // Standard for 1024-pt FFT
-parameter SEGMENT_ADVANCE = BUFFER_SIZE - OVERLAP_SAMPLES;  // 896 samples
-parameter DEBUG = 1;                  // Debug output control
+parameter BUFFER_SIZE = `RP_FFT_SIZE;              // 2048
+parameter LONG_CHIRP_SAMPLES = 3000;               // Still 3000 samples total
+parameter SHORT_CHIRP_SAMPLES = 50;                // 0.5 us @ 100MHz
+parameter OVERLAP_SAMPLES = `RP_OVERLAP_SAMPLES;   // 128
+parameter SEGMENT_ADVANCE = `RP_SEGMENT_ADVANCE;   // 2048 - 128 = 1920 samples
+parameter DEBUG = 1;                               // Debug output control
 
 // Calculate segments needed with overlap
-// For 3072 samples with 128 overlap: 
-// Segments = ceil((3072 - 128) / 896) = ceil(2944/896) = 4
-parameter LONG_SEGMENTS = 4;          // Now exactly 4 segments!
-parameter SHORT_SEGMENTS = 1;         // 50 samples padded to 1024
+// For 3000 samples with 128 overlap:
+// Segments = ceil((3000 - 2048) / 1920) + 1 = ceil(952/1920) + 1 = 2
+parameter LONG_SEGMENTS = `RP_LONG_SEGMENTS_3KM;   // 2 segments
+parameter SHORT_SEGMENTS = 1;                      // 50 samples padded to 2048
 
 // ========== FIXED INTERNAL SIGNALS ==========
 reg signed [31:0] pc_i, pc_q;
@@ -59,19 +61,19 @@ reg pc_valid;
 // Dual buffer for overlap-save — BRAM inferred for synthesis
 (* ram_style = "block" *) reg signed [15:0] input_buffer_i [0:BUFFER_SIZE-1];
 (* ram_style = "block" *) reg signed [15:0] input_buffer_q [0:BUFFER_SIZE-1];
-reg [10:0] buffer_write_ptr;
-reg [10:0] buffer_read_ptr;
+reg [11:0] buffer_write_ptr;    // 12-bit for 0..2048
+reg [11:0] buffer_read_ptr;     // 12-bit for 0..2048
 reg buffer_has_data;
 reg buffer_processing;
 reg [15:0] chirp_samples_collected;
 
 // BRAM write port signals
 reg        buf_we;
-reg [9:0]  buf_waddr;
+reg [10:0] buf_waddr;           // 11-bit for 0..2047
 reg signed [15:0] buf_wdata_i, buf_wdata_q;
 
 // BRAM read port signals
-reg [9:0]  buf_raddr;
+reg [10:0] buf_raddr;           // 11-bit for 0..2047
 reg signed [15:0] buf_rdata_i, buf_rdata_q;
 
 // State machine
@@ -94,15 +96,22 @@ reg chirp_complete;
 reg saw_chain_output;             // Flag: chain started producing output
 
 // Overlap cache — captured during ST_PROCESSING, written back in ST_OVERLAP_COPY
+// Uses sync-only write block to allow distributed RAM inference (not FFs).
+// 128 entries = distributed RAM (LUTRAM), NOT BRAM (too shallow).
 reg signed [15:0] overlap_cache_i [0:OVERLAP_SAMPLES-1];
 reg signed [15:0] overlap_cache_q [0:OVERLAP_SAMPLES-1];
 reg [7:0] overlap_copy_count;
 
+// Overlap cache write port signals (driven from FSM, used in sync-only block)
+reg        ov_we;
+reg [6:0]  ov_waddr;
+reg signed [15:0] ov_wdata_i, ov_wdata_q;
+
 // Microcontroller sync detection
 reg mc_new_chirp_prev, mc_new_elevation_prev, mc_new_azimuth_prev;
-wire chirp_start_pulse = mc_new_chirp && !mc_new_chirp_prev;
-wire elevation_change_pulse = mc_new_elevation && !mc_new_elevation_prev;
-wire azimuth_change_pulse = mc_new_azimuth && !mc_new_azimuth_prev;
+wire chirp_start_pulse = mc_new_chirp ^ mc_new_chirp_prev;           // Toggle-to-pulse (any edge)
+wire elevation_change_pulse = mc_new_elevation ^ mc_new_elevation_prev; // Toggle-to-pulse
+wire azimuth_change_pulse = mc_new_azimuth ^ mc_new_azimuth_prev;     // Toggle-to-pulse
 
 // Processing chain signals
 wire [15:0] fft_pc_i, fft_pc_q;
@@ -115,7 +124,7 @@ reg fft_input_valid;
 reg fft_start;
 
 // ========== SAMPLE ADDRESS OUTPUT ==========
-assign sample_addr_out = buffer_read_ptr;
+assign sample_addr_out = buffer_read_ptr[10:0];
 
 // ========== MICROCONTROLLER SYNC ==========
 always @(posedge clk or negedge reset_n) begin
@@ -152,6 +161,16 @@ always @(posedge clk) begin
     end
 end
 
+// ========== OVERLAP CACHE WRITE PORT (sync only — distributed RAM inference) ==========
+// Removing async reset from memory write path prevents Vivado from
+// synthesizing the 128x16 arrays as FFs + mux trees.
+always @(posedge clk) begin
+    if (ov_we) begin
+        overlap_cache_i[ov_waddr] <= ov_wdata_i;
+        overlap_cache_q[ov_waddr] <= ov_wdata_q;
+    end
+end
+
 // ========== BRAM READ PORT (synchronous, no async reset) ==========
 always @(posedge clk) begin
     buf_rdata_i <= input_buffer_i[buf_raddr];
@@ -183,12 +202,17 @@ always @(posedge clk or negedge reset_n) begin
         buf_wdata_i <= 0;
         buf_wdata_q <= 0;
         buf_raddr <= 0;
+        ov_we <= 0;
+        ov_waddr <= 0;
+        ov_wdata_i <= 0;
+        ov_wdata_q <= 0;
         overlap_copy_count <= 0;
     end else begin
         pc_valid <= 0;
         mem_request <= 0;
         fft_input_valid <= 0;
         buf_we <= 0;  // Default: no write
+        ov_we <= 0;   // Default: no overlap write
         
         case (state)
             ST_IDLE: begin
@@ -223,7 +247,7 @@ always @(posedge clk or negedge reset_n) begin
                 if (ddc_valid && buffer_write_ptr < BUFFER_SIZE) begin
                     // Store in buffer via BRAM write port
                     buf_we <= 1;
-                    buf_waddr <= buffer_write_ptr[9:0];
+                    buf_waddr <= buffer_write_ptr[10:0];
                     buf_wdata_i <= ddc_i[17:2] + ddc_i[1];
                     buf_wdata_q <= ddc_q[17:2] + ddc_q[1];
                     
@@ -244,6 +268,7 @@ always @(posedge clk or negedge reset_n) begin
                     if (!use_long_chirp) begin
                         if (chirp_samples_collected >= SHORT_CHIRP_SAMPLES - 1) begin
                             state <= ST_ZERO_PAD;
+                            chirp_complete <= 1;  // Bug A fix: mark chirp done so ST_OUTPUT exits to IDLE
                             `ifdef SIMULATION
                             $display("[MULTI_SEG_FIXED] Short chirp: collected %d samples, starting zero-pad",
                                      chirp_samples_collected + 1);
@@ -257,8 +282,8 @@ always @(posedge clk or negedge reset_n) begin
                 // missing the transition when buffer_write_ptr updates via
                 // non-blocking assignment one cycle after the last write.
                 //
-                // Overlap-save fix: fill the FULL 1024-sample buffer before
-                // processing.  For segment 0 this means 1024 fresh samples.
+                // Overlap-save fix: fill the FULL FFT_SIZE-sample buffer before
+                // processing.  For segment 0 this means FFT_SIZE fresh samples.
                 // For segments 1+, write_ptr starts at OVERLAP_SAMPLES (128)
                 // so we collect 896 new samples to fill the buffer.
                 if (use_long_chirp) begin
@@ -295,7 +320,7 @@ always @(posedge clk or negedge reset_n) begin
             ST_ZERO_PAD: begin
                 // Zero-pad remaining buffer via BRAM write port
                 buf_we <= 1;
-                buf_waddr <= buffer_write_ptr[9:0];
+                buf_waddr <= buffer_write_ptr[10:0];
                 buf_wdata_i <= 16'd0;
                 buf_wdata_q <= 16'd0;
                 buffer_write_ptr <= buffer_write_ptr + 1;
@@ -315,7 +340,7 @@ always @(posedge clk or negedge reset_n) begin
             
             ST_WAIT_REF: begin
                 // Wait for memory to provide reference coefficients
-                buf_raddr <= 10'd0;  // Pre-present addr 0 so buf_rdata is ready next cycle
+                buf_raddr <= 11'd0;  // Pre-present addr 0 so buf_rdata is ready next cycle
                 if (mem_ready) begin
                     // Start processing — buf_rdata[0] will be valid on FIRST clock of ST_PROCESSING
                     buffer_processing <= 1;
@@ -344,10 +369,12 @@ always @(posedge clk or negedge reset_n) begin
                     // 2. Request corresponding reference sample
                     mem_request <= 1'b1;
                     
-                    // 3. Cache tail samples for overlap-save
+                    // 3. Cache tail samples for overlap-save (via sync-only write port)
                     if (buffer_read_ptr >= SEGMENT_ADVANCE) begin
-                        overlap_cache_i[buffer_read_ptr - SEGMENT_ADVANCE] <= buf_rdata_i;
-                        overlap_cache_q[buffer_read_ptr - SEGMENT_ADVANCE] <= buf_rdata_q;
+                        ov_we <= 1;
+                        ov_waddr <= buffer_read_ptr - SEGMENT_ADVANCE;  // 0..OVERLAP-1
+                        ov_wdata_i <= buf_rdata_i;
+                        ov_wdata_q <= buf_rdata_q;
                     end
                     
                     // Debug every 100 samples
@@ -361,7 +388,7 @@ always @(posedge clk or negedge reset_n) begin
                     end
                     
                     // Present NEXT read address (for next cycle)
-                    buf_raddr <= buffer_read_ptr[9:0] + 10'd1;
+                    buf_raddr <= buffer_read_ptr[10:0] + 11'd1;
                     buffer_read_ptr <= buffer_read_ptr + 1;
                     
                 end else if (buffer_read_ptr >= BUFFER_SIZE) begin
@@ -382,7 +409,7 @@ always @(posedge clk or negedge reset_n) begin
             
             ST_WAIT_FFT: begin
                 // Wait for the processing chain to complete ALL outputs.
-                // The chain streams 1024 samples (fft_pc_valid=1 for 1024 clocks),
+                // The chain streams FFT_SIZE samples (fft_pc_valid=1 for FFT_SIZE clocks),
                 // then transitions to ST_DONE (9) -> ST_IDLE (0).
                 // We track when output starts (saw_chain_output) and only
                 // proceed once the chain returns to idle after outputting.
@@ -454,7 +481,7 @@ always @(posedge clk or negedge reset_n) begin
             ST_OVERLAP_COPY: begin
                 // Write one cached overlap sample per cycle to BRAM
                 buf_we <= 1;
-                buf_waddr <= {{2{1'b0}}, overlap_copy_count};
+                buf_waddr <= {{3{1'b0}}, overlap_copy_count};
                 buf_wdata_i <= overlap_cache_i[overlap_copy_count];
                 buf_wdata_q <= overlap_cache_q[overlap_copy_count];
                 
@@ -500,11 +527,9 @@ matched_filter_processing_chain m_f_p_c(
     // Chirp Selection
     .chirp_counter(chirp_counter),
     
-    // Reference Chirp Memory Interfaces
-    .long_chirp_real(long_chirp_real),
-    .long_chirp_imag(long_chirp_imag),
-    .short_chirp_real(short_chirp_real),
-    .short_chirp_imag(short_chirp_imag),
+    // Reference Chirp Memory Interface (single pair — upstream selects long/short)
+    .ref_chirp_real(ref_chirp_real),
+    .ref_chirp_imag(ref_chirp_imag),
     
     // Output
     .range_profile_i(fft_pc_i),

9_Firmware/9_2_FPGA/matched_filter_processing_chain.v

@@ -15,26 +15,28 @@
  *   .clk, .reset_n
  *   .adc_data_i, .adc_data_q, .adc_valid      <- from input buffer
  *   .chirp_counter                              <- 6-bit frame counter
- *   .long_chirp_real/imag, .short_chirp_real/imag <- reference (time-domain)
+ *   .ref_chirp_real/imag                     <- reference (time-domain)
  *   .range_profile_i, .range_profile_q, .range_profile_valid -> output
  *   .chain_state                                -> 4-bit status
  *
  * Clock domain: clk (100 MHz system clock)
  * Data format:  16-bit signed (Q15 fixed-point)
- * FFT size:     1024 points
+ * FFT size:     2048 points (parameterized via radar_params.vh)
  *
  * Pipeline states:
- *   IDLE -> FWD_FFT (collect 1024 samples + bit-reverse copy)
+ *   IDLE -> FWD_FFT (collect 2048 samples + bit-reverse copy)
  *        -> FWD_BUTTERFLY (forward FFT of signal)
  *        -> REF_BITREV (bit-reverse copy reference into work arrays)
  *        -> REF_BUTTERFLY (forward FFT of reference)
  *        -> MULTIPLY (conjugate multiply in freq domain)
  *        -> INV_BITREV (bit-reverse copy product)
  *        -> INV_BUTTERFLY (inverse FFT + 1/N scaling)
- *        -> OUTPUT (stream 1024 samples)
+ *        -> OUTPUT (stream 2048 samples)
  *        -> DONE -> IDLE
  */
 
+`include "radar_params.vh"
+
 module matched_filter_processing_chain (
     input wire clk,
     input wire reset_n,
@@ -48,10 +50,10 @@ module matched_filter_processing_chain (
     input wire [5:0] chirp_counter,
 
     // Reference chirp (time-domain, latency-aligned by upstream buffer)
-    input wire [15:0] long_chirp_real,
-    input wire [15:0] long_chirp_imag,
-    input wire [15:0] short_chirp_real,
-    input wire [15:0] short_chirp_imag,
+    // Upstream chirp_memory_loader_param selects long/short reference
+    // via use_long_chirp — this single pair carries whichever is active.
+    input wire [15:0] ref_chirp_real,
+    input wire [15:0] ref_chirp_imag,
 
     // Output: range profile (pulse-compressed)
     output wire signed [15:0] range_profile_i,
@@ -66,8 +68,8 @@ module matched_filter_processing_chain (
 // ============================================================================
 // PARAMETERS
 // ============================================================================
-localparam FFT_SIZE   = 1024;
-localparam ADDR_BITS  = 10;    // log2(1024)
+localparam FFT_SIZE   = `RP_FFT_SIZE;    // 2048
+localparam ADDR_BITS  = `RP_LOG2_FFT_SIZE; // log2(2048) = 11
 
 // State encoding (4-bit, up to 16 states)
 localparam [3:0] ST_IDLE           = 4'd0;
@@ -87,8 +89,8 @@ reg [3:0] state;
 // SIGNAL BUFFERS
 // ============================================================================
 // Input sample counter
-reg [ADDR_BITS:0] fwd_in_count;     // 0..1024
-reg fwd_frame_done;                  // All 1024 samples received
+reg [ADDR_BITS:0] fwd_in_count;     // 0..FFT_SIZE
+reg fwd_frame_done;                  // All FFT_SIZE samples received
 
 // Signal time-domain buffer
 reg signed [15:0] fwd_buf_i [0:FFT_SIZE-1];
@@ -175,7 +177,7 @@ always @(posedge clk or negedge reset_n) begin
 
         case (state)
         // ================================================================
-        // IDLE: Wait for valid ADC data, start collecting 1024 samples
+        // IDLE: Wait for valid ADC data, start collecting 2048 samples
         // ================================================================
         ST_IDLE: begin
             fwd_in_count   <= 0;
@@ -189,8 +191,8 @@ always @(posedge clk or negedge reset_n) begin
                 // Store first sample (signal + reference)
                 fwd_buf_i[0] <= $signed(adc_data_i);
                 fwd_buf_q[0] <= $signed(adc_data_q);
-                ref_buf_i[0] <= $signed(long_chirp_real);
-                ref_buf_q[0] <= $signed(long_chirp_imag);
+                ref_buf_i[0] <= $signed(ref_chirp_real);
+                ref_buf_q[0] <= $signed(ref_chirp_imag);
                 fwd_in_count <= 1;
                 state        <= ST_FWD_FFT;
             end
@@ -198,6 +200,7 @@ always @(posedge clk or negedge reset_n) begin
 
         // ================================================================
         // FWD_FFT: Collect remaining samples, then bit-reverse copy signal
+        // (2048 samples total)
         // ================================================================
         ST_FWD_FFT: begin
             if (!fwd_frame_done) begin
@@ -205,8 +208,8 @@ always @(posedge clk or negedge reset_n) begin
                 if (adc_valid && fwd_in_count < FFT_SIZE) begin
                     fwd_buf_i[fwd_in_count] <= $signed(adc_data_i);
                     fwd_buf_q[fwd_in_count] <= $signed(adc_data_q);
-                    ref_buf_i[fwd_in_count] <= $signed(long_chirp_real);
-                    ref_buf_q[fwd_in_count] <= $signed(long_chirp_imag);
+                    ref_buf_i[fwd_in_count] <= $signed(ref_chirp_real);
+                    ref_buf_q[fwd_in_count] <= $signed(ref_chirp_imag);
                     fwd_in_count <= fwd_in_count + 1;
                 end
 
@@ -437,7 +440,7 @@ always @(posedge clk or negedge reset_n) begin
                 end
             end
 
-            // Scale by 1/N (right shift by log2(1024) = 10) and store
+            // Scale by 1/N (right shift by log2(2048) = 11) and store
             for (i = 0; i < FFT_SIZE; i = i + 1) begin : ifft_scale
                 reg signed [31:0] scaled_re, scaled_im;
                 scaled_re = work_re[i] >>> ADDR_BITS;
@@ -467,7 +470,7 @@ always @(posedge clk or negedge reset_n) begin
         end
 
         // ================================================================
-        // OUTPUT: Stream out 1024 range profile samples, one per clock
+        // OUTPUT: Stream out 2048 range profile samples, one per clock
         // ================================================================
         ST_OUTPUT: begin
             if (out_count < FFT_SIZE) begin
@@ -531,16 +534,16 @@ end
 // ============================================================================
 // SYNTHESIS IMPLEMENTATION — Radix-2 DIT FFT via fft_engine
 // ============================================================================
-// Uses a single fft_engine instance (1024-pt) reused 3 times:
+// Uses a single fft_engine instance (2048-pt) reused 3 times:
 //   1. Forward FFT of signal
 //   2. Forward FFT of reference
 //   3. Inverse FFT of conjugate product
 // Conjugate multiply done via frequency_matched_filter (4-stage pipeline).
 //
 // Buffer scheme (BRAM-inferrable):
-//   sig_buf[1024]:  ADC input -> signal FFT output
-//   ref_buf[1024]:  Reference input -> reference FFT output
-//   prod_buf[1024]: Conjugate multiply output -> IFFT output
+//   sig_buf[2048]:  ADC input -> signal FFT output
+//   ref_buf[2048]:  Reference input -> reference FFT output
+//   prod_buf[2048]: Conjugate multiply output -> IFFT output
 //
 // Memory access is INSIDE always @(posedge clk) blocks (no async reset)
 // using local blocking variables. This eliminates NBA race conditions
@@ -552,12 +555,12 @@ end
 //   out_primed   — for output streaming
 // ============================================================================
 
-localparam FFT_SIZE  = 1024;
-localparam ADDR_BITS = 10;
+localparam FFT_SIZE  = `RP_FFT_SIZE;    // 2048
+localparam ADDR_BITS = `RP_LOG2_FFT_SIZE; // 11
 
 // State encoding
 localparam [3:0] ST_IDLE     = 4'd0,
-                 ST_COLLECT  = 4'd1,   // Collect 1024 ADC + ref samples
+                 ST_COLLECT  = 4'd1,   // Collect FFT_SIZE ADC + ref samples
                  ST_SIG_FFT  = 4'd2,   // Forward FFT of signal
                  ST_SIG_CAP  = 4'd3,   // Capture signal FFT output
                  ST_REF_FFT  = 4'd4,   // Forward FFT of reference
@@ -565,7 +568,7 @@ localparam [3:0] ST_IDLE     = 4'd0,
                  ST_MULTIPLY = 4'd6,   // Conjugate multiply (pipelined)
                  ST_INV_FFT  = 4'd7,   // Inverse FFT of product
                  ST_INV_CAP  = 4'd8,   // Capture IFFT output
-                 ST_OUTPUT   = 4'd9,   // Stream 1024 results
+                 ST_OUTPUT   = 4'd9,   // Stream FFT_SIZE results
                  ST_DONE     = 4'd10;
 
 reg [3:0] state;
@@ -588,11 +591,11 @@ reg signed [15:0] prod_rdata_i, prod_rdata_q;
 // ============================================================================
 // COUNTERS
 // ============================================================================
-reg [ADDR_BITS:0] collect_count;   // 0..1024 for sample collection
-reg [ADDR_BITS:0] feed_count;      // 0..1024 for feeding FFT engine
-reg [ADDR_BITS:0] cap_count;       // 0..1024 for capturing FFT output
-reg [ADDR_BITS:0] mult_count;      // 0..1024 for multiply feeding
-reg [ADDR_BITS:0] out_count;       // 0..1024 for output streaming
+reg [ADDR_BITS:0] collect_count;   // 0..FFT_SIZE for sample collection
+reg [ADDR_BITS:0] feed_count;      // 0..FFT_SIZE for feeding FFT engine
+reg [ADDR_BITS:0] cap_count;       // 0..FFT_SIZE for capturing FFT output
+reg [ADDR_BITS:0] mult_count;      // 0..FFT_SIZE for multiply feeding
+reg [ADDR_BITS:0] out_count;       // 0..FFT_SIZE for output streaming
 
 // BRAM read latency pipeline flags
 reg feed_primed;   // 1 = BRAM rdata valid for feed operations
@@ -617,7 +620,7 @@ fft_engine #(
     .DATA_W(16),
     .INTERNAL_W(32),
     .TWIDDLE_W(16),
-    .TWIDDLE_FILE("fft_twiddle_1024.mem")
+    .TWIDDLE_FILE("fft_twiddle_2048.mem")
 ) fft_inst (
     .clk(clk),
     .reset_n(reset_n),
@@ -775,16 +778,16 @@ always @(posedge clk) begin : ref_bram_port
         if (adc_valid) begin
             we      = 1'b1;
             addr    = 0;
-            wdata_i = $signed(long_chirp_real);
-            wdata_q = $signed(long_chirp_imag);
+            wdata_i = $signed(ref_chirp_real);
+            wdata_q = $signed(ref_chirp_imag);
         end
     end
     ST_COLLECT: begin
         if (adc_valid && collect_count < FFT_SIZE) begin
             we      = 1'b1;
             addr    = collect_count[ADDR_BITS-1:0];
-            wdata_i = $signed(long_chirp_real);
-            wdata_q = $signed(long_chirp_imag);
+            wdata_i = $signed(ref_chirp_real);
+            wdata_q = $signed(ref_chirp_imag);
         end
     end
     ST_REF_FFT: begin
@@ -968,7 +971,7 @@ always @(posedge clk or negedge reset_n) begin
         end
 
         // ================================================================
-        // COLLECT: Gather 1024 ADC + reference samples
+        // COLLECT: Gather 2048 ADC + reference samples
         // Writes happen in sig/ref BRAM ports (they see state==ST_COLLECT)
         // ================================================================
         ST_COLLECT: begin
@@ -977,7 +980,7 @@ always @(posedge clk or negedge reset_n) begin
             end
 
             if (collect_count == FFT_SIZE) begin
-                // All 1024 samples collected — start signal FFT
+                // All 2048 samples collected — start signal FFT
                 state       <= ST_SIG_FFT;
                 fft_start   <= 1'b1;
                 fft_inverse <= 1'b0;  // Forward FFT
@@ -1091,7 +1094,7 @@ always @(posedge clk or negedge reset_n) begin
         // ================================================================
         // MULTIPLY: Stream sig FFT and ref FFT through freq_matched_filter
         // Both sig_buf and ref_buf are read simultaneously (separate BRAM
-        // ports). Pipeline latency = 4 clocks. Feed 1024 pairs, then flush.
+        // ports). Pipeline latency = 4 clocks. Feed 2048 pairs, then flush.
         // ================================================================
         ST_MULTIPLY: begin
             if (mult_count < FFT_SIZE) begin
@@ -1180,7 +1183,7 @@ always @(posedge clk or negedge reset_n) begin
         end
 
         // ================================================================
-        // OUTPUT: Stream 1024 range profile samples
+        // OUTPUT: Stream 2048 range profile samples
         // BRAM read latency: present address, data valid next cycle.
         // ================================================================
         ST_OUTPUT: begin

9_Firmware/9_2_FPGA/mti_canceller.v

@@ -19,25 +19,33 @@
  *     mti_out_i[r] = current_i[r] - previous_i[r]
  *     mti_out_q[r] = current_q[r] - previous_q[r]
  *
- * The previous chirp's 64 range bins are stored in a small BRAM.
+ * The previous chirp's 512 range bins are stored in BRAM (inferred via
+ * sync-only read/write always blocks — NO async reset on memory arrays).
  * On the very first chirp after reset (or enable), there is no previous
  * data — output is zero (muted) for that first chirp.
  *
- * When mti_enable=0, the module is a transparent pass-through with zero
- * latency penalty (data goes straight through combinationally registered).
+ * When mti_enable=0, the module is a transparent pass-through.
  *
- * Resources:
- *   - 2 BRAM18 (64 x 16-bit I + 64 x 16-bit Q) or distributed RAM
- *   - ~30 LUTs (subtract + mux)
- *   - ~40 FFs (pipeline + control)
+ * BRAM inference note:
+ *   prev_i/prev_q arrays use dedicated sync-only always blocks for read
+ *   and write. This ensures Vivado infers BRAM (RAMB18) instead of fabric
+ *   FFs + mux trees. The registered read adds 1 cycle of latency, which
+ *   is compensated by a pipeline stage on the input data path.
+ *
+ * Resources (target):
+ *   - 2 BRAM18 (512 x 16-bit I + 512 x 16-bit Q)
+ *   - ~30 LUTs (subtract + mux + saturation)
+ *   - ~80 FFs (pipeline + control)
  *   - 0 DSP48
  *
  * Clock domain: clk (100 MHz)
  */
 
+`include "radar_params.vh"
+
 module mti_canceller #(
-    parameter NUM_RANGE_BINS = 64,
-    parameter DATA_WIDTH     = 16
+    parameter NUM_RANGE_BINS = `RP_NUM_RANGE_BINS,    // 512
+    parameter DATA_WIDTH     = `RP_DATA_WIDTH         // 16
 ) (
     input wire clk,
     input wire reset_n,
@@ -46,13 +54,13 @@ module mti_canceller #(
     input wire signed [DATA_WIDTH-1:0] range_i_in,
     input wire signed [DATA_WIDTH-1:0] range_q_in,
     input wire                         range_valid_in,
-    input wire [5:0]                   range_bin_in,
+    input wire [`RP_RANGE_BIN_BITS-1:0] range_bin_in,   // 9-bit
 
     // ========== OUTPUT (to Doppler processor) ==========
     output reg signed [DATA_WIDTH-1:0] range_i_out,
     output reg signed [DATA_WIDTH-1:0] range_q_out,
     output reg                         range_valid_out,
-    output reg [5:0]                   range_bin_out,
+    output reg [`RP_RANGE_BIN_BITS-1:0] range_bin_out,   // 9-bit
 
     // ========== CONFIGURATION ==========
     input wire mti_enable,   // 1=MTI active, 0=pass-through
@@ -62,30 +70,79 @@ module mti_canceller #(
 );
 
 // ============================================================================
-// PREVIOUS CHIRP BUFFER (64 x 16-bit I, 64 x 16-bit Q)
+// PREVIOUS CHIRP BUFFER (512 x 16-bit I, 512 x 16-bit Q)
 // ============================================================================
-// Small enough for distributed RAM on XC7A200T (64 entries).
-// Using separate I/Q arrays for clean read/write.
+// BRAM-inferred on XC7A50T/200T (512 entries, sync-only read/write).
+// Using separate I/Q arrays for clean dual-port inference.
 
-reg signed [DATA_WIDTH-1:0] prev_i [0:NUM_RANGE_BINS-1];
-reg signed [DATA_WIDTH-1:0] prev_q [0:NUM_RANGE_BINS-1];
+(* ram_style = "block" *) reg signed [DATA_WIDTH-1:0] prev_i [0:NUM_RANGE_BINS-1];
+(* ram_style = "block" *) reg signed [DATA_WIDTH-1:0] prev_q [0:NUM_RANGE_BINS-1];
+
+// ============================================================================
+// INPUT PIPELINE STAGE (1 cycle delay to match BRAM read latency)
+// ============================================================================
+// Declarations must precede the BRAM write block that references them.
+
+reg signed [DATA_WIDTH-1:0] range_i_d1, range_q_d1;
+reg                         range_valid_d1;
+reg [`RP_RANGE_BIN_BITS-1:0] range_bin_d1;
+reg                         mti_enable_d1;
+
+always @(posedge clk or negedge reset_n) begin
+    if (!reset_n) begin
+        range_i_d1     <= {DATA_WIDTH{1'b0}};
+        range_q_d1     <= {DATA_WIDTH{1'b0}};
+        range_valid_d1 <= 1'b0;
+        range_bin_d1   <= {`RP_RANGE_BIN_BITS{1'b0}};
+        mti_enable_d1  <= 1'b0;
+    end else begin
+        range_i_d1     <= range_i_in;
+        range_q_d1     <= range_q_in;
+        range_valid_d1 <= range_valid_in;
+        range_bin_d1   <= range_bin_in;
+        mti_enable_d1  <= mti_enable;
+    end
+end
+
+// ============================================================================
+// BRAM WRITE PORT (sync only — NO async reset for BRAM inference)
+// ============================================================================
+// Writes the current chirp sample into prev_i/prev_q for next chirp's
+// subtraction. Uses the delayed (d1) signals so the write happens 1 cycle
+// after the read address is presented, avoiding RAW hazards.
+
+always @(posedge clk) begin
+    if (range_valid_d1) begin
+        prev_i[range_bin_d1] <= range_i_d1;
+        prev_q[range_bin_d1] <= range_q_d1;
+    end
+end
+
+// ============================================================================
+// BRAM READ PORT (sync only — 1 cycle read latency)
+// ============================================================================
+// Address is always driven by range_bin_in (cycle 0). Read data appears
+// on prev_i_rd / prev_q_rd at cycle 1, aligned with the d1 pipeline stage.
+
+reg signed [DATA_WIDTH-1:0] prev_i_rd, prev_q_rd;
+
+always @(posedge clk) begin
+    prev_i_rd <= prev_i[range_bin_in];
+    prev_q_rd <= prev_q[range_bin_in];
+end
 
 // Track whether we have valid previous data
 reg has_previous;
 
 // ============================================================================
-// MTI PROCESSING
+// MTI PROCESSING (operates on d1 pipeline stage + BRAM read data)
 // ============================================================================
 
-// Read previous chirp data (combinational)
-wire signed [DATA_WIDTH-1:0] prev_i_rd = prev_i[range_bin_in];
-wire signed [DATA_WIDTH-1:0] prev_q_rd = prev_q[range_bin_in];
-
 // Compute difference with saturation
 // Subtraction can produce DATA_WIDTH+1 bits; saturate back to DATA_WIDTH.
-wire signed [DATA_WIDTH:0] diff_i_full = {range_i_in[DATA_WIDTH-1], range_i_in}
+wire signed [DATA_WIDTH:0] diff_i_full = {range_i_d1[DATA_WIDTH-1], range_i_d1}
                                         - {prev_i_rd[DATA_WIDTH-1], prev_i_rd};
-wire signed [DATA_WIDTH:0] diff_q_full = {range_q_in[DATA_WIDTH-1], range_q_in}
+wire signed [DATA_WIDTH:0] diff_q_full = {range_q_d1[DATA_WIDTH-1], range_q_d1}
                                         - {prev_q_rd[DATA_WIDTH-1], prev_q_rd};
 
 // Saturate to DATA_WIDTH bits
@@ -105,32 +162,28 @@ assign diff_q_sat = (diff_q_full > $signed({{2{1'b0}}, {(DATA_WIDTH-1){1'b1}}}))
                   : diff_q_full[DATA_WIDTH-1:0];
 
 // ============================================================================
-// MAIN LOGIC
+// MAIN OUTPUT LOGIC (operates on d1 pipeline stage)
 // ============================================================================
 always @(posedge clk or negedge reset_n) begin
     if (!reset_n) begin
         range_i_out     <= {DATA_WIDTH{1'b0}};
         range_q_out     <= {DATA_WIDTH{1'b0}};
         range_valid_out <= 1'b0;
-        range_bin_out   <= 6'd0;
+        range_bin_out   <= {`RP_RANGE_BIN_BITS{1'b0}};
         has_previous    <= 1'b0;
         mti_first_chirp <= 1'b1;
     end else begin
         // Default: no valid output
         range_valid_out <= 1'b0;
 
-        if (range_valid_in) begin
-            // Always store current sample as "previous" for next chirp
-            prev_i[range_bin_in] <= range_i_in;
-            prev_q[range_bin_in] <= range_q_in;
+        if (range_valid_d1) begin
+            // Output path — range_bin is from the delayed pipeline
+            range_bin_out <= range_bin_d1;
 
-            // Output path
-            range_bin_out <= range_bin_in;
-
-            if (!mti_enable) begin
+            if (!mti_enable_d1) begin
                 // Pass-through mode: no MTI processing
-                range_i_out     <= range_i_in;
-                range_q_out     <= range_q_in;
+                range_i_out     <= range_i_d1;
+                range_q_out     <= range_q_d1;
                 range_valid_out <= 1'b1;
                 // Reset first-chirp state when MTI is disabled
                 has_previous    <= 1'b0;
@@ -144,7 +197,7 @@ always @(posedge clk or negedge reset_n) begin
                 range_valid_out <= 1'b1;
 
                 // After last range bin of first chirp, mark previous as valid
-                if (range_bin_in == NUM_RANGE_BINS - 1) begin
+                if (range_bin_d1 == NUM_RANGE_BINS - 1) begin
                     has_previous    <= 1'b1;
                     mti_first_chirp <= 1'b0;
                 end

9_Firmware/9_2_FPGA/radar_mode_controller.v

@@ -1,5 +1,7 @@
 `timescale 1ns / 1ps
 
+`include "radar_params.vh"
+
 /**
  * radar_mode_controller.v
  *
@@ -18,12 +20,18 @@
  *   - 32 chirps per elevation
  *   - 31 elevations per azimuth
  *   - 50 azimuths per full scan
- *   - Each chirp: Long chirp → Listen → Guard → Short chirp → Listen
  *
- * Modes of operation:
+ * Chirp sequence depends on range_mode (host_range_mode, opcode 0x20):
+ *   range_mode 2'b00 (3 km):  All short chirps only. Long chirp blind zone
+ *     (4500 m) exceeds 3 km max range, so long chirps are useless.
+ *   range_mode 2'b01 (long-range): Dual chirp — Long chirp → Listen → Guard
+ *     → Short chirp → Listen. First half of chirps_per_elev are long, second
+ *     half are short (blind-zone fill).
+ *
+ * Modes of operation (host_radar_mode, opcode 0x01):
  *   mode[1:0]:
  *     2'b00 = STM32-driven (pass through stm32 toggle signals)
- *     2'b01 = Free-running auto-scan (internal timing)
+ *     2'b01 = Free-running auto-scan (internal timing, short chirps only)
  *     2'b10 = Single-chirp (fire one chirp per trigger, for debug)
  *     2'b11 = Reserved
  *
@@ -31,9 +39,9 @@
  */
 
 module radar_mode_controller #(
-    parameter CHIRPS_PER_ELEVATION = 32,
+    parameter CHIRPS_PER_ELEVATION  = `RP_DEF_CHIRPS_PER_ELEV,
     parameter ELEVATIONS_PER_AZIMUTH = 31,
-    parameter AZIMUTHS_PER_SCAN = 50,
+    parameter AZIMUTHS_PER_SCAN     = 50,
 
     // Timing in 100 MHz clock cycles
     // Long chirp: 30us = 3000 cycles at 100 MHz
@@ -41,18 +49,24 @@ module radar_mode_controller #(
     // Guard: 175.4us = 17540 cycles
     // Short chirp: 0.5us = 50 cycles
     // Short listen: 174.5us = 17450 cycles
-    parameter LONG_CHIRP_CYCLES   = 3000,
-    parameter LONG_LISTEN_CYCLES  = 13700,
-    parameter GUARD_CYCLES        = 17540,
-    parameter SHORT_CHIRP_CYCLES  = 50,
-    parameter SHORT_LISTEN_CYCLES = 17450
+    parameter LONG_CHIRP_CYCLES   = `RP_DEF_LONG_CHIRP_CYCLES,
+    parameter LONG_LISTEN_CYCLES  = `RP_DEF_LONG_LISTEN_CYCLES,
+    parameter GUARD_CYCLES        = `RP_DEF_GUARD_CYCLES,
+    parameter SHORT_CHIRP_CYCLES  = `RP_DEF_SHORT_CHIRP_CYCLES,
+    parameter SHORT_LISTEN_CYCLES = `RP_DEF_SHORT_LISTEN_CYCLES
 ) (
     input wire clk,
     input wire reset_n,
 
-    // Mode selection
+    // Mode selection (host_radar_mode, opcode 0x01)
     input wire [1:0] mode,          // 00=STM32, 01=auto, 10=single, 11=rsvd
 
+    // Range mode (host_range_mode, opcode 0x20)
+    // Determines chirp type selection in pass-through and auto-scan modes.
+    //   2'b00 = 3 km  (all short chirps — long blind zone > max range)
+    //   2'b01 = Long-range (dual chirp: first half long, second half short)
+    input wire [1:0] range_mode,
+
     // STM32 pass-through inputs (active in mode 00)
     input wire stm32_new_chirp,
     input wire stm32_new_elevation,
@@ -61,10 +75,8 @@ module radar_mode_controller #(
     // Single-chirp trigger (active in mode 10)
     input wire trigger,
 
-    // Gap 2: Runtime-configurable timing inputs from host USB commands.
+    // Runtime-configurable timing inputs from host USB commands.
     // When connected, these override the compile-time parameters.
-    // When left at default (tied to parameter values at instantiation),
-    // behavior is identical to pre-Gap-2.
     input wire [15:0] cfg_long_chirp_cycles,
     input wire [15:0] cfg_long_listen_cycles,
     input wire [15:0] cfg_guard_cycles,
@@ -156,7 +168,7 @@ always @(posedge clk or negedge reset_n) begin
     if (!reset_n) begin
         scan_state      <= S_IDLE;
         timer           <= 18'd0;
-        use_long_chirp  <= 1'b1;
+        use_long_chirp  <= 1'b0;  // Default short chirp (safe for 3 km mode)
         mc_new_chirp    <= 1'b0;
         mc_new_elevation <= 1'b0;
         mc_new_azimuth  <= 1'b0;
@@ -172,7 +184,12 @@ always @(posedge clk or negedge reset_n) begin
         // ================================================================
         // MODE 00: STM32-driven pass-through
         // The STM32 firmware controls timing; we just detect toggle edges
-        // and forward them to the receiver chain.
+        // and forward them to the receiver chain. Chirp type is determined
+        // by range_mode:
+        //   range_mode 00 (3 km):  ALL chirps are short (long blind zone
+        //     4500 m exceeds 3072 m max range, so long chirps are useless).
+        //   range_mode 01 (long-range): First half of chirps_per_elev are
+        //     long, second half are short (blind-zone fill).
         // ================================================================
         2'b00: begin
             // Reset auto-scan state
@@ -182,9 +199,29 @@ always @(posedge clk or negedge reset_n) begin
             // Pass through toggle signals
             if (stm32_chirp_toggle) begin
                 mc_new_chirp <= ~mc_new_chirp;  // Toggle output
-                use_long_chirp <= 1'b1;         // Default to long chirp
 
-                // Track chirp count (Gap 2: use runtime cfg_chirps_per_elev)
+                // Determine chirp type based on range_mode
+                case (range_mode)
+                `RP_RANGE_MODE_3KM: begin
+                    // 3 km mode: all short chirps
+                    use_long_chirp <= 1'b0;
+                end
+                `RP_RANGE_MODE_LONG: begin
+                    // Long-range: first half long, second half short.
+                    // chirps_per_elev is typically 32 (16 long + 16 short).
+                    // Use cfg_chirps_per_elev[5:1] as the halfway point.
+                    if (chirp_count < {1'b0, cfg_chirps_per_elev[5:1]})
+                        use_long_chirp <= 1'b1;
+                    else
+                        use_long_chirp <= 1'b0;
+                end
+                default: begin
+                    // Reserved modes: default to short chirp (safe)
+                    use_long_chirp <= 1'b0;
+                end
+                endcase
+
+                // Track chirp count
                 if (chirp_count < cfg_chirps_per_elev - 1)
                     chirp_count <= chirp_count + 1;
                 else
@@ -217,21 +254,33 @@ always @(posedge clk or negedge reset_n) begin
         // ================================================================
         // MODE 01: Free-running auto-scan
         // Internally generates chirp timing matching the transmitter.
+        // For 3 km mode (range_mode 00): short chirps only. The long chirp
+        // blind zone (4500 m) exceeds the 3072 m max range, making long
+        // chirps useless. State machine skips S_LONG_CHIRP/LISTEN/GUARD.
+        // For long-range mode (range_mode 01): full dual-chirp sequence.
+        // NOTE: Auto-scan is primarily for bench testing without STM32.
         // ================================================================
         2'b01: begin
             case (scan_state)
             S_IDLE: begin
                 // Start first chirp immediately
-                scan_state     <= S_LONG_CHIRP;
-                timer          <= 18'd0;
-                use_long_chirp <= 1'b1;
-                mc_new_chirp   <= ~mc_new_chirp;  // Toggle to start chirp
-                chirp_count    <= 6'd0;
+                timer           <= 18'd0;
+                chirp_count     <= 6'd0;
                 elevation_count <= 6'd0;
-                azimuth_count  <= 6'd0;
+                azimuth_count   <= 6'd0;
+                mc_new_chirp    <= ~mc_new_chirp;  // Toggle to start chirp
+
+                // For 3 km mode, skip directly to short chirp
+                if (range_mode == `RP_RANGE_MODE_3KM) begin
+                    scan_state     <= S_SHORT_CHIRP;
+                    use_long_chirp <= 1'b0;
+                end else begin
+                    scan_state     <= S_LONG_CHIRP;
+                    use_long_chirp <= 1'b1;
+                end
 
                 `ifdef SIMULATION
-                $display("[MODE_CTRL] Auto-scan starting");
+                $display("[MODE_CTRL] Auto-scan starting, range_mode=%0d", range_mode);
                 `endif
             end
 
@@ -285,13 +334,19 @@ always @(posedge clk or negedge reset_n) begin
 
             S_ADVANCE: begin
                 // Advance chirp/elevation/azimuth counters
-                // (Gap 2: use runtime cfg_chirps_per_elev)
                 if (chirp_count < cfg_chirps_per_elev - 1) begin
                     // Next chirp in current elevation
                     chirp_count  <= chirp_count + 1;
                     mc_new_chirp <= ~mc_new_chirp;
-                    scan_state   <= S_LONG_CHIRP;
-                    use_long_chirp <= 1'b1;
+
+                    // For 3 km mode: short chirps only, skip long phases
+                    if (range_mode == `RP_RANGE_MODE_3KM) begin
+                        scan_state     <= S_SHORT_CHIRP;
+                        use_long_chirp <= 1'b0;
+                    end else begin
+                        scan_state     <= S_LONG_CHIRP;
+                        use_long_chirp <= 1'b1;
+                    end
                 end else begin
                     chirp_count <= 6'd0;
 
@@ -300,8 +355,14 @@ always @(posedge clk or negedge reset_n) begin
                         elevation_count  <= elevation_count + 1;
                         mc_new_chirp     <= ~mc_new_chirp;
                         mc_new_elevation <= ~mc_new_elevation;
-                        scan_state       <= S_LONG_CHIRP;
-                        use_long_chirp   <= 1'b1;
+
+                        if (range_mode == `RP_RANGE_MODE_3KM) begin
+                            scan_state     <= S_SHORT_CHIRP;
+                            use_long_chirp <= 1'b0;
+                        end else begin
+                            scan_state     <= S_LONG_CHIRP;
+                            use_long_chirp <= 1'b1;
+                        end
                     end else begin
                         elevation_count <= 6'd0;
 
@@ -311,8 +372,14 @@ always @(posedge clk or negedge reset_n) begin
                             mc_new_chirp     <= ~mc_new_chirp;
                             mc_new_elevation <= ~mc_new_elevation;
                             mc_new_azimuth   <= ~mc_new_azimuth;
-                            scan_state       <= S_LONG_CHIRP;
-                            use_long_chirp   <= 1'b1;
+
+                            if (range_mode == `RP_RANGE_MODE_3KM) begin
+                                scan_state     <= S_SHORT_CHIRP;
+                                use_long_chirp <= 1'b0;
+                            end else begin
+                                scan_state     <= S_LONG_CHIRP;
+                                use_long_chirp <= 1'b1;
+                            end
                         end else begin
                             // Full scan complete — restart
                             azimuth_count   <= 6'd0;
@@ -320,8 +387,14 @@ always @(posedge clk or negedge reset_n) begin
                             mc_new_chirp    <= ~mc_new_chirp;
                             mc_new_elevation <= ~mc_new_elevation;
                             mc_new_azimuth  <= ~mc_new_azimuth;
-                            scan_state      <= S_LONG_CHIRP;
-                            use_long_chirp  <= 1'b1;
+
+                            if (range_mode == `RP_RANGE_MODE_3KM) begin
+                                scan_state     <= S_SHORT_CHIRP;
+                                use_long_chirp <= 1'b0;
+                            end else begin
+                                scan_state     <= S_LONG_CHIRP;
+                                use_long_chirp <= 1'b1;
+                            end
 
                             `ifdef SIMULATION
                             $display("[MODE_CTRL] Full scan complete, restarting");
@@ -337,16 +410,27 @@ always @(posedge clk or negedge reset_n) begin
 
         // ================================================================
         // MODE 10: Single-chirp (debug mode)
-        // Fire one long chirp per trigger pulse, no scanning.
+        // Fire one chirp per trigger pulse, no scanning.
+        // Chirp type depends on range_mode:
+        //   3 km:  short chirp only
+        //   Long-range: long chirp (for testing long-chirp path)
         // ================================================================
         2'b10: begin
             case (scan_state)
             S_IDLE: begin
                 if (trigger_pulse) begin
-                    scan_state     <= S_LONG_CHIRP;
-                    timer          <= 18'd0;
-                    use_long_chirp <= 1'b1;
-                    mc_new_chirp   <= ~mc_new_chirp;
+                    timer        <= 18'd0;
+                    mc_new_chirp <= ~mc_new_chirp;
+
+                    if (range_mode == `RP_RANGE_MODE_3KM) begin
+                        // 3 km: fire short chirp
+                        scan_state     <= S_SHORT_CHIRP;
+                        use_long_chirp <= 1'b0;
+                    end else begin
+                        // Long-range: fire long chirp
+                        scan_state     <= S_LONG_CHIRP;
+                        use_long_chirp <= 1'b1;
+                    end
                 end
             end
 
@@ -363,7 +447,27 @@ always @(posedge clk or negedge reset_n) begin
                 if (timer < cfg_long_listen_cycles - 1)
                     timer <= timer + 1;
                 else begin
-                    // Single chirp done, return to idle
+                    // Single long chirp done, return to idle
+                    timer      <= 18'd0;
+                    scan_state <= S_IDLE;
+                end
+            end
+
+            S_SHORT_CHIRP: begin
+                use_long_chirp <= 1'b0;
+                if (timer < cfg_short_chirp_cycles - 1)
+                    timer <= timer + 1;
+                else begin
+                    timer <= 18'd0;
+                    scan_state <= S_SHORT_LISTEN;
+                end
+            end
+
+            S_SHORT_LISTEN: begin
+                if (timer < cfg_short_listen_cycles - 1)
+                    timer <= timer + 1;
+                else begin
+                    // Single short chirp done, return to idle
                     timer      <= 18'd0;
                     scan_state <= S_IDLE;
                 end

9_Firmware/9_2_FPGA/radar_params.vh

@@ -0,0 +1,228 @@
+// ============================================================================
+// radar_params.vh — Single Source of Truth for AERIS-10 FPGA Parameters
+// ============================================================================
+//
+// ALL modules in the FPGA processing chain MUST `include this file instead of
+// hardcoding range bins, segment counts, chirp samples, or timing values.
+//
+// This file uses `define macros (not localparam) so it can be included at any
+// scope. Each consuming module should include this file inside its body and
+// optionally alias macros to localparams for readability.
+//
+// BOARD VARIANTS:
+//   SUPPORT_LONG_RANGE = 0  (50T, USB_MODE=1)  — 3 km mode only
+//   SUPPORT_LONG_RANGE = 1  (200T, USB_MODE=0) — 3 km + 20 km modes
+//
+// RADAR MODES (runtime, via host_radar_mode register, opcode 0x01):
+//   2'b00 = STM32 pass-through (production — STM32 controls chirp timing)
+//   2'b01 = Auto-scan 3 km     (FPGA-timed, short chirps only)
+//   2'b10 = Single-chirp debug (one long chirp per trigger)
+//   2'b11 = Reserved / idle
+//
+// RANGE MODES (runtime, via host_range_mode register, opcode 0x20):
+//   2'b00 = 3 km   (default — pass-through treats all chirps as short)
+//   2'b01 = Long-range (pass-through: first half long, second half short)
+//   2'b10 = Reserved
+//   2'b11 = Reserved
+//
+// USAGE:
+//   `include "radar_params.vh"
+//   Then reference `RP_FFT_SIZE, `RP_NUM_RANGE_BINS, etc.
+//
+// PHYSICAL CONSTANTS (derived from hardware):
+//   ADC clock:           400 MSPS
+//   CIC decimation:      4x
+//   Processing rate:     100 MSPS (post-DDC)
+//   Range per sample:    c / (2 * 100e6) = 1.5 m
+//   FFT size:            2048
+//   Decimation factor:   4  (2048 FFT bins -> 512 output range bins)
+//   Range per dec. bin:  1.5 m * 4 = 6.0 m
+//   Max range (3 km):    512 * 6.0 = 3072 m
+//   Carrier frequency:   10.5 GHz
+//   IF frequency:        120 MHz
+//
+// CHIRP BANDWIDTH (Phase 1 target — currently 20 MHz, planned 30 MHz):
+//   Range resolution:    c / (2 * BW)
+//     20 MHz -> 7.5 m
+//     30 MHz -> 5.0 m
+//   NOTE: Range resolution is independent of range-per-bin. Resolution
+//   determines the minimum separation between two targets; range-per-bin
+//   determines the spatial sampling grid.
+// ============================================================================
+
+`ifndef RADAR_PARAMS_VH
+`define RADAR_PARAMS_VH
+
+// ============================================================================
+// BOARD VARIANT — set at synthesis time, NOT runtime
+// ============================================================================
+// Default to 50T (conservative). Override in top-level or synthesis script:
+//   +define+SUPPORT_LONG_RANGE
+// or via Vivado: set_property verilog_define {SUPPORT_LONG_RANGE} [current_fileset]
+
+// Note: SUPPORT_LONG_RANGE is a flag define (ifdef/ifndef), not a value.
+// `ifndef SUPPORT_LONG_RANGE means 50T (no long range).
+// `ifdef SUPPORT_LONG_RANGE means 200T (long range supported).
+
+// ============================================================================
+// FFT AND PROCESSING CONSTANTS (fixed, both modes)
+// ============================================================================
+
+`define RP_FFT_SIZE             2048    // Range FFT points per segment
+`define RP_LOG2_FFT_SIZE        11      // log2(2048)
+`define RP_OVERLAP_SAMPLES      128     // Overlap between adjacent segments
+`define RP_SEGMENT_ADVANCE      1920    // FFT_SIZE - OVERLAP = 2048 - 128
+`define RP_DECIMATION_FACTOR    4       // Range bin decimation (2048 -> 512)
+`define RP_NUM_RANGE_BINS       512     // FFT_SIZE / DECIMATION_FACTOR
+`define RP_RANGE_BIN_BITS       9       // ceil(log2(512))
+`define RP_DOPPLER_FFT_SIZE     16      // Per sub-frame Doppler FFT
+`define RP_CHIRPS_PER_FRAME     32      // Total chirps (16 long + 16 short)
+`define RP_CHIRPS_PER_SUBFRAME  16      // Chirps per Doppler sub-frame
+`define RP_NUM_DOPPLER_BINS     32      // 2 sub-frames * 16 = 32
+`define RP_DATA_WIDTH           16      // ADC/processing data width
+
+// ============================================================================
+// 3 KM MODE PARAMETERS (both 50T and 200T)
+// ============================================================================
+
+`define RP_LONG_CHIRP_SAMPLES_3KM   3000    // 30 us at 100 MSPS
+`define RP_LONG_SEGMENTS_3KM        2       // ceil((3000-2048)/1920) + 1 = 2
+`define RP_SHORT_CHIRP_SAMPLES      50      // 0.5 us at 100 MSPS (same both modes)
+`define RP_SHORT_SEGMENTS           1       // Single segment for short chirp
+
+// Derived 3 km limits
+`define RP_MAX_RANGE_3KM            3072    // 512 bins * 6 m = 3072 m
+
+// ============================================================================
+// 20 KM MODE PARAMETERS (200T only — Phase 2)
+// ============================================================================
+
+`define RP_LONG_CHIRP_SAMPLES_20KM  13700   // 137 us at 100 MSPS (= listen window)
+`define RP_LONG_SEGMENTS_20KM       8       // 1 + ceil((13700-2048)/1920) = 1 + 7 = 8
+`define RP_OUTPUT_RANGE_BINS_20KM   4096    // 8 segments * 512 dec. bins each
+
+// Derived 20 km limits
+`define RP_MAX_RANGE_20KM           24576   // 4096 bins * 6 m = 24576 m
+
+// ============================================================================
+// MAX VALUES (for sizing buffers — compile-time, based on board variant)
+// ============================================================================
+
+`ifdef SUPPORT_LONG_RANGE
+  `define RP_MAX_SEGMENTS           8
+  `define RP_MAX_OUTPUT_BINS        4096
+  `define RP_MAX_CHIRP_SAMPLES      13700
+`else
+  `define RP_MAX_SEGMENTS           2
+  `define RP_MAX_OUTPUT_BINS        512
+  `define RP_MAX_CHIRP_SAMPLES      3000
+`endif
+
+// ============================================================================
+// BIT WIDTHS (derived from MAX values)
+// ============================================================================
+
+// Segment index: ceil(log2(MAX_SEGMENTS))
+//   50T:  log2(2) = 1 bit  (use 2 for safety)
+//   200T: log2(8) = 3 bits
+`ifdef SUPPORT_LONG_RANGE
+  `define RP_SEGMENT_IDX_WIDTH      3
+  `define RP_RANGE_BIN_WIDTH_MAX    12      // ceil(log2(4096))
+  `define RP_DOPPLER_MEM_ADDR_W     17      // ceil(log2(4096*32)) = 17
+  `define RP_CFAR_MAG_ADDR_W        17      // ceil(log2(4096*32)) = 17
+`else
+  `define RP_SEGMENT_IDX_WIDTH      2
+  `define RP_RANGE_BIN_WIDTH_MAX    9       // ceil(log2(512))
+  `define RP_DOPPLER_MEM_ADDR_W     14      // ceil(log2(512*32)) = 14
+  `define RP_CFAR_MAG_ADDR_W        14      // ceil(log2(512*32)) = 14
+`endif
+
+// Derived depths (for memory declarations)
+// Usage: reg [15:0] mem [0:`RP_DOPPLER_MEM_DEPTH-1];
+`define RP_DOPPLER_MEM_DEPTH    (`RP_MAX_OUTPUT_BINS * `RP_CHIRPS_PER_FRAME)
+`define RP_CFAR_MAG_DEPTH       (`RP_MAX_OUTPUT_BINS * `RP_NUM_DOPPLER_BINS)
+
+// ============================================================================
+// CHIRP TIMING DEFAULTS (100 MHz clock cycles)
+// ============================================================================
+// Reset defaults for host-configurable timing registers.
+// Match radar_mode_controller.v parameters and main.cpp STM32 defaults.
+
+`define RP_DEF_LONG_CHIRP_CYCLES    3000    // 30 us
+`define RP_DEF_LONG_LISTEN_CYCLES   13700   // 137 us
+`define RP_DEF_GUARD_CYCLES         17540   // 175.4 us
+`define RP_DEF_SHORT_CHIRP_CYCLES   50      // 0.5 us
+`define RP_DEF_SHORT_LISTEN_CYCLES  17450   // 174.5 us
+`define RP_DEF_CHIRPS_PER_ELEV      32
+
+// ============================================================================
+// BLIND ZONE CONSTANTS (informational, for comments and GUI)
+// ============================================================================
+// Long chirp blind zone:  c * 30 us / 2 = 4500 m
+// Short chirp blind zone: c * 0.5 us / 2 = 75 m
+
+`define RP_LONG_BLIND_ZONE_M        4500
+`define RP_SHORT_BLIND_ZONE_M       75
+
+// ============================================================================
+// PHYSICAL CONSTANTS (integer-scaled for Verilog — use in comments/assertions)
+// ============================================================================
+// Range per ADC sample:     1.5 m  (stored as 15 in units of 0.1 m)
+// Range per decimated bin:  6.0 m  (stored as 60 in units of 0.1 m)
+// Processing rate:         100 MSPS
+
+`define RP_RANGE_PER_SAMPLE_DM      15      // 1.5 m in decimeters
+`define RP_RANGE_PER_BIN_DM         60      // 6.0 m in decimeters
+`define RP_PROCESSING_RATE_MHZ      100
+
+// ============================================================================
+// AGC DEFAULTS
+// ============================================================================
+`define RP_DEF_AGC_TARGET           200
+`define RP_DEF_AGC_ATTACK           1
+`define RP_DEF_AGC_DECAY            1
+`define RP_DEF_AGC_HOLDOFF          4
+
+// ============================================================================
+// CFAR DEFAULTS
+// ============================================================================
+`define RP_DEF_CFAR_GUARD           2
+`define RP_DEF_CFAR_TRAIN           8
+`define RP_DEF_CFAR_ALPHA           8'h30   // 3.0 in Q4.4
+`define RP_DEF_CFAR_MODE            2'b00   // CA-CFAR
+
+// ============================================================================
+// DETECTION DEFAULTS
+// ============================================================================
+`define RP_DEF_DETECT_THRESHOLD     10000
+
+// ============================================================================
+// RADAR MODE ENCODING (host_radar_mode, opcode 0x01)
+// ============================================================================
+`define RP_MODE_STM32_PASSTHROUGH   2'b00
+`define RP_MODE_AUTO_3KM            2'b01
+`define RP_MODE_SINGLE_DEBUG        2'b10
+`define RP_MODE_RESERVED            2'b11
+
+// ============================================================================
+// RANGE MODE ENCODING (host_range_mode, opcode 0x20)
+// ============================================================================
+`define RP_RANGE_MODE_3KM           2'b00
+`define RP_RANGE_MODE_LONG          2'b01
+`define RP_RANGE_MODE_RSVD2         2'b10
+`define RP_RANGE_MODE_RSVD3         2'b11
+
+// ============================================================================
+// STREAM CONTROL (host_stream_control, opcode 0x04, 6-bit)
+// ============================================================================
+// Bits [2:0]: Stream enable mask
+//   Bit 0 = range profile stream
+//   Bit 1 = doppler map stream
+//   Bit 2 = cfar/detection stream
+// Bits [5:3]: Stream format control
+//   Bit 3 = mag_only    (0=I/Q pairs, 1=Manhattan magnitude only)
+//   Bit 4 = sparse_det  (0=dense detection flags, 1=sparse detection list)
+//   Bit 5 = reserved (was frame_decimate, not needed with mag-only fitting)
+`define RP_STREAM_CTRL_DEFAULT      6'b001_111  // all streams, mag-only mode
+
+`endif // RADAR_PARAMS_VH

9_Firmware/9_2_FPGA/radar_receiver_final.v

@@ -1,5 +1,7 @@
 `timescale 1ns / 1ps
 
+`include "radar_params.vh"
+
 module radar_receiver_final (
     input wire clk,           // 100MHz    
 	 input wire reset_n,
@@ -17,17 +19,22 @@ module radar_receiver_final (
     output wire [31:0] doppler_output,
     output wire doppler_valid,
     output wire [4:0] doppler_bin,
-    output wire [5:0] range_bin,
+    output wire [`RP_RANGE_BIN_BITS-1:0] range_bin,  // 9-bit
     
-    // Matched filter range profile output (for USB)
-    output wire signed [15:0] range_profile_i_out,
-    output wire signed [15:0] range_profile_q_out,
-    output wire range_profile_valid_out,
+    // Raw matched-filter output (debug/bring-up)
+    output wire signed [15:0] range_profile_i_out,
+    output wire signed [15:0] range_profile_q_out,
+    output wire range_profile_valid_out,
+
+    // Decimated 512-bin range profile (for USB bulk frames / downstream consumers)
+    output wire [15:0] decimated_range_mag_out,
+    output wire decimated_range_valid_out,
     
     // Host command inputs (Gap 4: USB Read Path, CDC-synchronized)
     // CDC-synchronized in radar_system_top.v before reaching here
     input wire [1:0] host_mode,      // Radar mode: 00=STM32, 01=auto-scan, 10=single-chirp
     input wire host_trigger,          // Single-chirp trigger pulse (1 clk cycle)
+    input wire [1:0] host_range_mode, // Range mode: 00=3km (short only), 01=long-range (dual chirp)
 
     // Gap 2: Host-configurable chirp timing (CDC-synchronized in radar_system_top.v)
     input wire [15:0] host_long_chirp_cycles,
@@ -102,9 +109,9 @@ wire [7:0] gc_saturation_count;  // Diagnostic: per-frame clipped sample counter
 wire [7:0] gc_peak_magnitude;    // Diagnostic: per-frame peak magnitude
 wire [3:0] gc_current_gain;      // Diagnostic: effective gain_shift
 
-// Reference signals for the processing chain
-wire [15:0] long_chirp_real, long_chirp_imag;
-wire [15:0] short_chirp_real, short_chirp_imag;
+// Reference signal for the processing chain (carries long OR short ref
+// depending on use_long_chirp — selected by chirp_memory_loader_param)
+wire [15:0] ref_chirp_real, ref_chirp_imag;
 
 // ========== DOPPLER PROCESSING SIGNALS ==========
 wire [31:0] range_data_32bit;
@@ -116,20 +123,36 @@ wire [31:0] doppler_spectrum;
 wire doppler_spectrum_valid;
 wire [4:0] doppler_bin_out;
 wire doppler_processing;
-wire doppler_frame_done;
+
+// frame_complete from doppler_processor is a LEVEL signal (high whenever
+// state == S_IDLE && !frame_buffer_full). Downstream consumers (USB FT2232H,
+// AGC, CFAR) expect a single-cycle PULSE. Convert here at the source so all
+// consumers are safe.
+wire doppler_frame_done_level;  // raw level from doppler_processor
+reg  doppler_frame_done_prev;
+wire doppler_frame_done;        // rising-edge pulse (1 clk cycle)
+
+always @(posedge clk or negedge reset_n) begin
+    if (!reset_n)
+        doppler_frame_done_prev <= 1'b0;
+    else
+        doppler_frame_done_prev <= doppler_frame_done_level;
+end
+
+assign doppler_frame_done = doppler_frame_done_level & ~doppler_frame_done_prev;
 assign doppler_frame_done_out = doppler_frame_done;
 
 // ========== RANGE BIN DECIMATOR SIGNALS ==========
 wire signed [15:0] decimated_range_i;
 wire signed [15:0] decimated_range_q;
 wire decimated_range_valid;
-wire [5:0] decimated_range_bin;
+wire [`RP_RANGE_BIN_BITS-1:0] decimated_range_bin;  // 9-bit
 
 // ========== MTI CANCELLER SIGNALS ==========
 wire signed [15:0] mti_range_i;
 wire signed [15:0] mti_range_q;
 wire mti_range_valid;
-wire [5:0] mti_range_bin;
+wire [`RP_RANGE_BIN_BITS-1:0] mti_range_bin;  // 9-bit
 wire mti_first_chirp;
 
 // ========== RADAR MODE CONTROLLER SIGNALS ==========
@@ -147,6 +170,7 @@ radar_mode_controller rmc (
     .clk(clk),
     .reset_n(reset_n),
     .mode(host_mode),                     // Controlled by host via USB (default: 2'b01 auto-scan)
+    .range_mode(host_range_mode),          // Range mode: 00=3km, 01=long-range (drives chirp type)
     .stm32_new_chirp(stm32_new_chirp_rx),
     .stm32_new_elevation(stm32_new_elevation_rx),
     .stm32_new_azimuth(stm32_new_azimuth_rx),
@@ -265,7 +289,7 @@ rx_gain_control gain_ctrl (
 );
 
 // 3. Dual Chirp Memory Loader
-wire [9:0] sample_addr_from_chain;
+wire [10:0] sample_addr_from_chain;
 
 chirp_memory_loader_param chirp_mem (
     .clk(clk),
@@ -279,20 +303,9 @@ chirp_memory_loader_param chirp_mem (
     .mem_ready(mem_ready)
 );
 
-// Sample address generator
-reg [9:0] sample_addr_reg;
-always @(posedge clk or negedge reset_n) begin
-    if (!reset_n) begin
-        sample_addr_reg <= 0;
-    end else if (mem_request) begin
-        sample_addr_reg <= sample_addr_reg + 1;
-        if (sample_addr_reg == 1023) sample_addr_reg <= 0;
-    end
-end
-// sample_addr_wire removed — was unused implicit wire (synthesis warning)
-
 // 4. CRITICAL: Reference Chirp Latency Buffer
-// This aligns reference data with FFT output (2159 cycle delay)
+// This aligns reference data with FFT output (3187 cycle delay)
+// TODO: verify empirically during hardware bring-up with correlation test
 wire [15:0] delayed_ref_i, delayed_ref_q;
 wire mem_ready_delayed;
 
@@ -308,11 +321,10 @@ latency_buffer #(
     .valid_out(mem_ready_delayed)
 );
 
-// Assign delayed reference signals
-assign long_chirp_real = delayed_ref_i;
-assign long_chirp_imag = delayed_ref_q;
-assign short_chirp_real = delayed_ref_i;
-assign short_chirp_imag = delayed_ref_q;
+// Assign delayed reference signals (single pair — chirp_memory_loader_param
+// selects long/short reference upstream via use_long_chirp)
+assign ref_chirp_real = delayed_ref_i;
+assign ref_chirp_imag = delayed_ref_q;
 
 // 5. Dual Chirp Matched Filter
 
@@ -321,9 +333,15 @@ wire signed [15:0] range_profile_q;
 wire range_valid;
 
 // Expose matched filter output to top level for USB range profile
-assign range_profile_i_out = range_profile_i;
-assign range_profile_q_out = range_profile_q;
-assign range_profile_valid_out = range_valid;
+assign range_profile_i_out = range_profile_i;
+assign range_profile_q_out = range_profile_q;
+assign range_profile_valid_out = range_valid;
+// Manhattan magnitude: |I| + |Q|, saturated to 16 bits
+wire [15:0] abs_mti_i = mti_range_i[15] ? (~mti_range_i + 16'd1) : mti_range_i;
+wire [15:0] abs_mti_q = mti_range_q[15] ? (~mti_range_q + 16'd1) : mti_range_q;
+wire [16:0] manhattan_sum = {1'b0, abs_mti_i} + {1'b0, abs_mti_q};
+assign decimated_range_mag_out = manhattan_sum[16] ? 16'hFFFF : manhattan_sum[15:0];
+assign decimated_range_valid_out = mti_range_valid;
 
 matched_filter_multi_segment mf_dual (
     .clk(clk),
@@ -336,10 +354,8 @@ matched_filter_multi_segment mf_dual (
     .mc_new_chirp(mc_new_chirp),
     .mc_new_elevation(mc_new_elevation),
     .mc_new_azimuth(mc_new_azimuth),
-	 .long_chirp_real(delayed_ref_i),      // From latency buffer
-    .long_chirp_imag(delayed_ref_q),
-    .short_chirp_real(delayed_ref_i),     // Same for short chirp
-    .short_chirp_imag(delayed_ref_q),
+	 .ref_chirp_real(delayed_ref_i),       // From latency buffer (long or short ref)
+    .ref_chirp_imag(delayed_ref_q),
     .segment_request(segment_request),
     .mem_request(mem_request),
 	 .sample_addr_out(sample_addr_from_chain),
@@ -350,11 +366,11 @@ matched_filter_multi_segment mf_dual (
 );
 
 // ========== CRITICAL: RANGE BIN DECIMATOR ==========
-// Convert 1024 range bins to 64 bins for Doppler
+// Convert 2048 range bins to 512 bins for Doppler
 range_bin_decimator #(
-    .INPUT_BINS(1024),
-    .OUTPUT_BINS(64),
-    .DECIMATION_FACTOR(16)
+    .INPUT_BINS(`RP_FFT_SIZE),              // 2048
+    .OUTPUT_BINS(`RP_NUM_RANGE_BINS),       // 512
+    .DECIMATION_FACTOR(`RP_DECIMATION_FACTOR)  // 4
 ) range_decim (
     .clk(clk),
     .reset_n(reset_n),
@@ -366,7 +382,7 @@ range_bin_decimator #(
     .range_valid_out(decimated_range_valid),
     .range_bin_index(decimated_range_bin),
     .decimation_mode(2'b01),           // Peak detection mode
-    .start_bin(10'd0),
+    .start_bin(11'd0),
     .watchdog_timeout()                // Diagnostic — unconnected (monitored via ILA if needed)
 );
 
@@ -375,8 +391,8 @@ range_bin_decimator #(
 // H(z) = 1 - z^{-1} → null at DC Doppler, removes stationary clutter.
 // When host_mti_enable=0: transparent pass-through.
 mti_canceller #(
-    .NUM_RANGE_BINS(64),
-    .DATA_WIDTH(16)
+    .NUM_RANGE_BINS(`RP_NUM_RANGE_BINS),    // 512
+    .DATA_WIDTH(`RP_DATA_WIDTH)             // 16
 ) mti_inst (
     .clk(clk),
     .reset_n(reset_n),
@@ -429,11 +445,11 @@ assign range_data_32bit = {mti_range_q, mti_range_i};
 assign range_data_valid = mti_range_valid;
 
 // ========== DOPPLER PROCESSOR ==========
-doppler_processor_optimized #(
-    .DOPPLER_FFT_SIZE(16),
-    .RANGE_BINS(64),
-    .CHIRPS_PER_FRAME(32),
-    .CHIRPS_PER_SUBFRAME(16)
+doppler_processor_optimized #(
+    .DOPPLER_FFT_SIZE(`RP_DOPPLER_FFT_SIZE),        // 16
+    .RANGE_BINS(`RP_NUM_RANGE_BINS),                // 512
+    .CHIRPS_PER_FRAME(`RP_CHIRPS_PER_FRAME),        // 32
+    .CHIRPS_PER_SUBFRAME(`RP_CHIRPS_PER_SUBFRAME)   // 16
 ) doppler_proc (
     .clk(clk),
     .reset_n(reset_n),
@@ -449,7 +465,7 @@ doppler_processor_optimized #(
     
     // Status
     .processing_active(doppler_processing),
-    .frame_complete(doppler_frame_done),
+    .frame_complete(doppler_frame_done_level),
     .status()
 );
 

9_Firmware/9_2_FPGA/radar_system_top.v

@@ -1,5 +1,7 @@
 `timescale 1ns / 1ps
 
+`include "radar_params.vh"
+
 /**
  * radar_system_top.v
  * 
@@ -122,7 +124,7 @@ module radar_system_top (
     output wire [31:0] dbg_doppler_data,
     output wire dbg_doppler_valid,
     output wire [4:0] dbg_doppler_bin,
-    output wire [5:0] dbg_range_bin,
+    output wire [`RP_RANGE_BIN_BITS-1:0] dbg_range_bin,
     
     // System status
     output wire [3:0] system_status,
@@ -176,11 +178,13 @@ wire tx_current_chirp_sync_valid;
 wire [31:0] rx_doppler_output;
 wire rx_doppler_valid;
 wire [4:0] rx_doppler_bin;
-wire [5:0] rx_range_bin;
-wire [31:0] rx_range_profile;
-wire rx_range_valid;
-wire [15:0] rx_doppler_real;
-wire [15:0] rx_doppler_imag;
+wire [`RP_RANGE_BIN_BITS-1:0] rx_range_bin;
+wire [31:0] rx_range_profile;
+wire rx_range_valid;
+wire [15:0] rx_range_profile_decimated;
+wire rx_range_profile_decimated_valid;
+wire [15:0] rx_doppler_real;
+wire [15:0] rx_doppler_imag;
 wire rx_doppler_data_valid;
 reg rx_detect_flag;       // Threshold detection result (was rx_cfar_detection)
 reg rx_detect_valid;      // Detection valid pulse (was rx_cfar_valid)
@@ -223,7 +227,7 @@ wire [15:0] usb_cmd_value;
 reg [1:0]  host_radar_mode;
 reg        host_trigger_pulse;
 reg [15:0] host_detect_threshold;  // (was host_cfar_threshold)
-reg [2:0]  host_stream_control;
+reg [5:0]  host_stream_control;
 
 // Fix 3: Digital gain control register
 // [3]=direction: 0=amplify, 1=attenuate. [2:0]=shift amount 0..7.
@@ -250,13 +254,12 @@ reg        host_status_request;       // Opcode 0xFF (self-clearing pulse)
 localparam DOPPLER_FRAME_CHIRPS = 32; // Total chirps per Doppler frame
 reg        chirps_mismatch_error;     // Set if host tried to set chirps != FFT size
 
-// Fix 7: Range-mode register (opcode 0x20)
-// Future-proofing for 3km/10km antenna switching.
-//   2'b00 = Auto (default — system selects based on scene)
-//   2'b01 = Short-range (3km)
-//   2'b10 = Long-range (10km)
+// Range-mode register (opcode 0x20)
+// Controls chirp type selection in the mode controller:
+//   2'b00 = 3 km mode (all short chirps — long blind zone > max range)
+//   2'b01 = Long-range (dual chirp: first half long, second half short)
+//   2'b10 = Reserved
 //   2'b11 = Reserved
-// Currently a configuration store only — antenna/timing switching TBD.
 reg [1:0]  host_range_mode;
 
 // CFAR configuration registers (host-configurable via USB)
@@ -519,14 +522,16 @@ radar_receiver_final rx_inst (
     .doppler_bin(rx_doppler_bin),
     .range_bin(rx_range_bin),
     
-    // Matched filter range profile (for USB)
-    .range_profile_i_out(rx_range_profile[15:0]),
-    .range_profile_q_out(rx_range_profile[31:16]),
-    .range_profile_valid_out(rx_range_valid),
+    // Range-profile outputs
+    .range_profile_i_out(rx_range_profile[15:0]),
+    .range_profile_q_out(rx_range_profile[31:16]),
+    .range_profile_valid_out(rx_range_valid),
+    .decimated_range_mag_out(rx_range_profile_decimated),
+    .decimated_range_valid_out(rx_range_profile_decimated_valid),
     
-    // Host command inputs (Gap 4: USB Read Path)
     .host_mode(host_radar_mode),
     .host_trigger(host_trigger_pulse),
+    .host_range_mode(host_range_mode),
     // Gap 2: Host-configurable chirp timing
     .host_long_chirp_cycles(host_long_chirp_cycles),
     .host_long_listen_cycles(host_long_listen_cycles),
@@ -596,7 +601,7 @@ assign dc_notch_active = (host_dc_notch_width != 3'd0) &&
 wire [31:0] notched_doppler_data  = dc_notch_active ? 32'd0 : rx_doppler_output;
 wire        notched_doppler_valid = rx_doppler_valid;
 wire [4:0]  notched_doppler_bin   = rx_doppler_bin;
-wire [5:0]  notched_range_bin     = rx_range_bin;
+wire [`RP_RANGE_BIN_BITS-1:0]  notched_range_bin     = rx_range_bin;
 
 // ============================================================================
 // CFAR DETECTOR (replaces simple threshold detector)
@@ -607,7 +612,7 @@ wire [5:0]  notched_range_bin     = rx_range_bin;
 
 wire cfar_detect_flag;
 wire cfar_detect_valid;
-wire [5:0]  cfar_detect_range;
+wire [`RP_RANGE_BIN_BITS-1:0]  cfar_detect_range;
 wire [4:0]  cfar_detect_doppler;
 wire [16:0] cfar_detect_magnitude;
 wire [16:0] cfar_detect_threshold;
@@ -698,9 +703,10 @@ end
 // DATA PACKING FOR USB
 // ============================================================================
 
-// Range profile from matched filter output (wired through radar_receiver_final)
-assign usb_range_profile = rx_range_profile;
-assign usb_range_valid = rx_range_valid;
+// USB range profile must match the advertised 512-bin frame payload, so source it
+// from the decimated range stream that feeds Doppler rather than raw MF samples.
+assign usb_range_profile = {16'd0, rx_range_profile_decimated};
+assign usb_range_valid = rx_range_profile_decimated_valid;
 
 assign usb_doppler_real = rx_doppler_real;
 assign usb_doppler_imag = rx_doppler_imag;
@@ -803,6 +809,11 @@ end else begin : gen_ft2232h
         .cfar_detection(usb_detect_flag),
         .cfar_valid(usb_detect_valid),
 
+        // Bulk frame protocol inputs
+        .range_bin_in(notched_range_bin),
+        .doppler_bin_in(notched_doppler_bin),
+        .frame_complete(rx_frame_complete),
+
         // FT2232H Interface
         .ft_data(ft_data),
         .ft_rxf_n(ft_rxf_n),
@@ -911,7 +922,7 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
         host_radar_mode    <= 2'b01;   // Default: auto-scan
         host_trigger_pulse <= 1'b0;
         host_detect_threshold <= 16'd10000; // Default threshold
-        host_stream_control <= 3'b111;    // Default: all streams enabled
+        host_stream_control <= `RP_STREAM_CTRL_DEFAULT; // Default: all streams, mag-only mode
         host_gain_shift     <= 4'd0;      // Default: pass-through (no gain change)
         // Gap 2: chirp timing defaults (match radar_mode_controller parameters)
         host_long_chirp_cycles  <= 16'd3000;
@@ -922,7 +933,7 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
         host_chirps_per_elev    <= 6'd32;
         host_status_request     <= 1'b0;
         chirps_mismatch_error   <= 1'b0;
-        host_range_mode         <= 2'b00;     // Default: auto
+        host_range_mode         <= 2'b00;     // Default: 3 km mode (all short chirps)
         // CFAR defaults (disabled by default — backward-compatible)
         host_cfar_guard         <= 4'd2;      // 2 guard cells each side
         host_cfar_train         <= 5'd8;      // 8 training cells each side
@@ -949,7 +960,7 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
                 8'h01: host_radar_mode     <= usb_cmd_value[1:0];
                 8'h02: host_trigger_pulse  <= 1'b1;
                 8'h03: host_detect_threshold <= usb_cmd_value;
-                8'h04: host_stream_control <= usb_cmd_value[2:0];
+                8'h04: host_stream_control <= usb_cmd_value[5:0];
                 // Gap 2: chirp timing configuration
                 8'h10: host_long_chirp_cycles  <= usb_cmd_value;
                 8'h11: host_long_listen_cycles <= usb_cmd_value;
@@ -972,7 +983,7 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
                     end
                 end
                 8'h16: host_gain_shift         <= usb_cmd_value[3:0];  // Fix 3: digital gain
-                8'h20: host_range_mode         <= usb_cmd_value[1:0];  // Fix 7: range mode
+                8'h20: host_range_mode         <= usb_cmd_value[1:0];  // Range mode
                 // CFAR configuration opcodes
                 8'h21: host_cfar_guard         <= usb_cmd_value[3:0];
                 8'h22: host_cfar_train         <= usb_cmd_value[4:0];

9_Firmware/9_2_FPGA/range_bin_decimator.v

@@ -3,7 +3,7 @@
 /**
  * range_bin_decimator.v
  *
- * Reduces 1024 range bins from the matched filter output down to 64 bins
+ * Reduces 2048 range bins from the matched filter output down to 512 bins
  * for the Doppler processor. Supports multiple decimation modes:
  *
  *   Mode 2'b00: Simple decimation (take every Nth sample)
@@ -11,29 +11,31 @@
  *   Mode 2'b10: Averaging (sum group and divide by N)
  *   Mode 2'b11: Reserved
  *
- * Interface contract (from radar_receiver_final.v line 229):
+ * Interface contract (from radar_receiver_final.v):
  *   .clk, .reset_n
- *   .range_i_in, .range_q_in, .range_valid_in   ← from matched_filter output
- *   .range_i_out, .range_q_out, .range_valid_out → to Doppler processor
- *   .range_bin_index                             → 6-bit output bin index
- *   .decimation_mode                             ← 2-bit mode select
- *   .start_bin                                   ← 10-bit start offset
+ *   .range_i_in, .range_q_in, .range_valid_in   <- from matched_filter output
+ *   .range_i_out, .range_q_out, .range_valid_out -> to Doppler processor
+ *   .range_bin_index                             -> 9-bit output bin index
+ *   .decimation_mode                             <- 2-bit mode select
+ *   .start_bin                                   <- 11-bit start offset
  *
  * start_bin usage:
  *   When start_bin > 0, the decimator skips the first 'start_bin' valid
  *   input samples before beginning decimation. This allows selecting a
- *   region of interest within the 1024 range bins (e.g., to focus on
+ *   region of interest within the 2048 range bins (e.g., to focus on
  *   near-range or far-range targets). When start_bin = 0 (default),
- *   all 1024 bins are processed starting from bin 0.
+ *   all 2048 bins are processed starting from bin 0.
  *
  * Clock domain: clk (100 MHz)
- * Decimation: 1024 → 64 (factor of 16)
+ * Decimation: 2048 -> 512 (factor of 4)
  */
 
+`include "radar_params.vh"
+
 module range_bin_decimator #(
-    parameter INPUT_BINS        = 1024,
-    parameter OUTPUT_BINS       = 64,
-    parameter DECIMATION_FACTOR = 16
+    parameter INPUT_BINS        = `RP_FFT_SIZE,          // 2048
+    parameter OUTPUT_BINS       = `RP_NUM_RANGE_BINS,    // 512
+    parameter DECIMATION_FACTOR = `RP_DECIMATION_FACTOR  // 4
 ) (
     input wire clk,
     input wire reset_n,
@@ -47,11 +49,11 @@ module range_bin_decimator #(
     output reg signed [15:0] range_i_out,
     output reg signed [15:0] range_q_out,
     output reg range_valid_out,
-    output reg [5:0] range_bin_index,
+    output reg [`RP_RANGE_BIN_BITS-1:0] range_bin_index,  // 9-bit
 
     // Configuration
     input wire [1:0] decimation_mode,  // 00=decimate, 01=peak, 10=average
-    input wire [9:0] start_bin,        // First input bin to process
+    input wire [10:0] start_bin,       // First input bin to process (11-bit for 2048)
 
     // Diagnostics
     output reg watchdog_timeout        // Pulses high for 1 cycle on watchdog reset
@@ -59,10 +61,10 @@ module range_bin_decimator #(
 `ifdef FORMAL
     ,
     output wire [2:0]  fv_state,
-    output wire [9:0]  fv_in_bin_count,
-    output wire [3:0]  fv_group_sample_count,
-    output wire [5:0]  fv_output_bin_count,
-    output wire [9:0]  fv_skip_count
+    output wire [10:0] fv_in_bin_count,
+    output wire [1:0]  fv_group_sample_count,
+    output wire [8:0]  fv_output_bin_count,
+    output wire [10:0] fv_skip_count
 `endif
 );
 
@@ -75,12 +77,12 @@ localparam WATCHDOG_LIMIT = 10'd256;
 // INTERNAL SIGNALS
 // ============================================================================
 
-// Input bin counter (0..1023)
-reg [9:0] in_bin_count;
+// Input bin counter (0..2047)
+reg [10:0] in_bin_count;
 
 // Group tracking
-reg [3:0] group_sample_count;  // 0..15 within current group of 16
-reg [5:0] output_bin_count;    // 0..63 output bin index
+reg [1:0] group_sample_count;   // 0..3 within current group of 4
+reg [8:0] output_bin_count;     // 0..511 output bin index
 
 // State machine
 reg [2:0] state;
@@ -91,7 +93,7 @@ localparam ST_EMIT    = 3'd3;
 localparam ST_DONE    = 3'd4;
 
 // Skip counter for start_bin
-reg [9:0] skip_count;
+reg [10:0] skip_count;
 
 // Watchdog counter — counts consecutive clocks with no range_valid_in
 reg [9:0] watchdog_count;
@@ -107,7 +109,7 @@ assign fv_skip_count         = skip_count;
 // ============================================================================
 // PEAK DETECTION (Mode 01)
 // ============================================================================
-// Track the sample with the largest magnitude in the current group of 16
+// Track the sample with the largest magnitude in the current group of 4
 reg signed [15:0] peak_i, peak_q;
 reg [16:0] peak_mag;  // |I| + |Q| approximation
 wire [16:0] cur_mag;
@@ -120,8 +122,8 @@ assign cur_mag = {1'b0, abs_i} + {1'b0, abs_q};
 // ============================================================================
 // AVERAGING (Mode 10)
 // ============================================================================
-// Accumulate I and Q separately, then divide by DECIMATION_FACTOR (>>4)
-reg signed [19:0] sum_i, sum_q;  // 16 + 4 guard bits for sum of 16 values
+// Accumulate I and Q separately, then divide by DECIMATION_FACTOR (>>2)
+reg signed [17:0] sum_i, sum_q;  // 16 + 2 guard bits for sum of 4 values
 
 // ============================================================================
 // SIMPLE DECIMATION (Mode 00)
@@ -135,21 +137,21 @@ reg signed [15:0] decim_i, decim_q;
 always @(posedge clk or negedge reset_n) begin
     if (!reset_n) begin
         state             <= ST_IDLE;
-        in_bin_count      <= 10'd0;
-        group_sample_count <= 4'd0;
-        output_bin_count  <= 6'd0;
-        skip_count        <= 10'd0;
+        in_bin_count      <= 11'd0;
+        group_sample_count <= 2'd0;
+        output_bin_count  <= 9'd0;
+        skip_count        <= 11'd0;
         watchdog_count    <= 10'd0;
         watchdog_timeout  <= 1'b0;
         range_valid_out   <= 1'b0;
         range_i_out       <= 16'd0;
         range_q_out       <= 16'd0;
-        range_bin_index   <= 6'd0;
+        range_bin_index   <= {`RP_RANGE_BIN_BITS{1'b0}};
         peak_i            <= 16'd0;
         peak_q            <= 16'd0;
         peak_mag          <= 17'd0;
-        sum_i             <= 20'd0;
-        sum_q             <= 20'd0;
+        sum_i             <= 18'd0;
+        sum_q             <= 18'd0;
         decim_i           <= 16'd0;
         decim_q           <= 16'd0;
     end else begin
@@ -162,33 +164,33 @@ always @(posedge clk or negedge reset_n) begin
         // IDLE: Wait for first valid input
         // ================================================================
         ST_IDLE: begin
-            in_bin_count       <= 10'd0;
-            group_sample_count <= 4'd0;
-            output_bin_count   <= 6'd0;
-            skip_count         <= 10'd0;
+            in_bin_count       <= 11'd0;
+            group_sample_count <= 2'd0;
+            output_bin_count   <= 9'd0;
+            skip_count         <= 11'd0;
             watchdog_count     <= 10'd0;
             peak_i             <= 16'd0;
             peak_q             <= 16'd0;
             peak_mag           <= 17'd0;
-            sum_i              <= 20'd0;
-            sum_q              <= 20'd0;
+            sum_i              <= 18'd0;
+            sum_q              <= 18'd0;
 
             if (range_valid_in) begin
-                in_bin_count <= 10'd1;
+                in_bin_count <= 11'd1;
 
-                if (start_bin > 10'd0) begin
+                if (start_bin > 11'd0) begin
                     // Need to skip 'start_bin' samples first
-                    skip_count <= 10'd1;
+                    skip_count <= 11'd1;
                     state      <= ST_SKIP;
                 end else begin
                     // No skip — process first sample immediately
                     state              <= ST_PROCESS;
-                    group_sample_count <= 4'd1;
+                    group_sample_count <= 2'd1;
 
                     // Mode-specific first sample handling
                     case (decimation_mode)
                     2'b00: begin  // Simple decimation — check if center sample
-                        if (4'd0 == (DECIMATION_FACTOR / 2)) begin
+                        if (2'd0 == (DECIMATION_FACTOR / 2)) begin
                             decim_i <= range_i_in;
                             decim_q <= range_q_in;
                         end
@@ -199,8 +201,8 @@ always @(posedge clk or negedge reset_n) begin
                         peak_mag <= cur_mag;
                     end
                     2'b10: begin  // Averaging
-                        sum_i <= {{4{range_i_in[15]}}, range_i_in};
-                        sum_q <= {{4{range_q_in[15]}}, range_q_in};
+                        sum_i <= {{2{range_i_in[15]}}, range_i_in};
+                        sum_q <= {{2{range_q_in[15]}}, range_q_in};
                     end
                     default: ;
                     endcase
@@ -219,11 +221,11 @@ always @(posedge clk or negedge reset_n) begin
                 if (skip_count >= start_bin) begin
                     // Done skipping — this sample is the first to process
                     state              <= ST_PROCESS;
-                    group_sample_count <= 4'd1;
+                    group_sample_count <= 2'd1;
 
                     case (decimation_mode)
                     2'b00: begin
-                        if (4'd0 == (DECIMATION_FACTOR / 2)) begin
+                        if (2'd0 == (DECIMATION_FACTOR / 2)) begin
                             decim_i <= range_i_in;
                             decim_q <= range_q_in;
                         end
@@ -234,8 +236,8 @@ always @(posedge clk or negedge reset_n) begin
                         peak_mag <= cur_mag;
                     end
                     2'b10: begin
-                        sum_i <= {{4{range_i_in[15]}}, range_i_in};
-                        sum_q <= {{4{range_q_in[15]}}, range_q_in};
+                        sum_i <= {{2{range_i_in[15]}}, range_i_in};
+                        sum_q <= {{2{range_q_in[15]}}, range_q_in};
                     end
                     default: ;
                     endcase
@@ -281,8 +283,8 @@ always @(posedge clk or negedge reset_n) begin
                     end
                 end
                 2'b10: begin  // Averaging
-                    sum_i <= sum_i + {{4{range_i_in[15]}}, range_i_in};
-                    sum_q <= sum_q + {{4{range_q_in[15]}}, range_q_in};
+                    sum_i <= sum_i + {{2{range_i_in[15]}}, range_i_in};
+                    sum_q <= sum_q + {{2{range_q_in[15]}}, range_q_in};
                 end
                 default: ;
                 endcase
@@ -291,7 +293,7 @@ always @(posedge clk or negedge reset_n) begin
                 if (group_sample_count == DECIMATION_FACTOR - 1) begin
                     // Group complete — emit output
                     state <= ST_EMIT;
-                    group_sample_count <= 4'd0;
+                    group_sample_count <= 2'd0;
                 end else if (in_bin_count >= INPUT_BINS - 1) begin
                     // Overflow guard: consumed all input bins but group
                     // is not yet complete. Stop to prevent corruption of
@@ -331,9 +333,9 @@ always @(posedge clk or negedge reset_n) begin
                 range_i_out <= peak_i;
                 range_q_out <= peak_q;
             end
-            2'b10: begin  // Averaging (sum >> 4 = divide by 16)
-                range_i_out <= sum_i[19:4];
-                range_q_out <= sum_q[19:4];
+            2'b10: begin  // Averaging (sum >> 2 = divide by 4)
+                range_i_out <= sum_i[17:2];
+                range_q_out <= sum_q[17:2];
             end
             default: begin
                 range_i_out <= 16'd0;
@@ -345,8 +347,8 @@ always @(posedge clk or negedge reset_n) begin
             peak_i   <= 16'd0;
             peak_q   <= 16'd0;
             peak_mag <= 17'd0;
-            sum_i    <= 20'd0;
-            sum_q    <= 20'd0;
+            sum_i    <= 18'd0;
+            sum_q    <= 18'd0;
 
             // Advance output bin
             output_bin_count <= output_bin_count + 1;
@@ -358,12 +360,12 @@ always @(posedge clk or negedge reset_n) begin
                 // If we already have valid input waiting, process it immediately
                 if (range_valid_in) begin
                     state              <= ST_PROCESS;
-                    group_sample_count <= 4'd1;
+                    group_sample_count <= 2'd1;
                     in_bin_count       <= in_bin_count + 1;
 
                     case (decimation_mode)
                     2'b00: begin
-                        if (4'd0 == (DECIMATION_FACTOR / 2)) begin
+                        if (2'd0 == (DECIMATION_FACTOR / 2)) begin
                             decim_i <= range_i_in;
                             decim_q <= range_q_in;
                         end
@@ -374,20 +376,20 @@ always @(posedge clk or negedge reset_n) begin
                         peak_mag <= cur_mag;
                     end
                     2'b10: begin
-                        sum_i <= {{4{range_i_in[15]}}, range_i_in};
-                        sum_q <= {{4{range_q_in[15]}}, range_q_in};
+                        sum_i <= {{2{range_i_in[15]}}, range_i_in};
+                        sum_q <= {{2{range_q_in[15]}}, range_q_in};
                     end
                     default: ;
                     endcase
                 end else begin
                     state <= ST_PROCESS;
-                    group_sample_count <= 4'd0;
+                    group_sample_count <= 2'd0;
                 end
             end
         end
 
         // ================================================================
-        // DONE: All 64 output bins emitted, return to idle
+        // DONE: All 512 output bins emitted, return to idle
         // ================================================================
         ST_DONE: begin
             state <= ST_IDLE;

9_Firmware/9_2_FPGA/run_regression.sh

@@ -253,11 +253,141 @@ run_lint_static() {
     fi
 }
 
+# ---------------------------------------------------------------------------
+# Helper: compile, run, and compare a matched-filter co-sim scenario
+#   run_mf_cosim <scenario_name> <define_flag>
+# ---------------------------------------------------------------------------
+run_mf_cosim() {
+    local name="$1"
+    local define="$2"
+    local vvp="tb/tb_mf_cosim_${name}.vvp"
+    local scenario_lower="$name"
+
+    printf "  %-45s " "MF Co-Sim ($name)"
+
+    # Compile — build command as string to handle optional define
+    local cmd="iverilog -g2001 -DSIMULATION"
+    if [[ -n "$define" ]]; then
+        cmd="$cmd $define"
+    fi
+    cmd="$cmd -o $vvp tb/tb_mf_cosim.v matched_filter_processing_chain.v fft_engine.v chirp_memory_loader_param.v"
+
+    if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
+        echo -e "${RED}COMPILE FAIL${NC}"
+        ERRORS="$ERRORS\n  MF Co-Sim ($name): compile error ($(head -1 /tmp/iverilog_err_$$))"
+        FAIL=$((FAIL + 1))
+        return
+    fi
+
+    # Run TB
+    local output
+    output=$(timeout 120 vvp "$vvp" 2>&1) || true
+    rm -f "$vvp"
+
+    # Check TB internal pass/fail
+    local tb_fail
+    tb_fail=$(echo "$output" | grep -Ec '^\[FAIL' || true)
+    if [[ "$tb_fail" -gt 0 ]]; then
+        echo -e "${RED}FAIL${NC} (TB internal failure)"
+        ERRORS="$ERRORS\n  MF Co-Sim ($name): TB internal failure"
+        FAIL=$((FAIL + 1))
+        return
+    fi
+
+    # Run Python compare
+    if command -v python3 >/dev/null 2>&1; then
+        local compare_out
+        local compare_rc=0
+        compare_out=$(python3 tb/cosim/compare_mf.py "$scenario_lower" 2>&1) || compare_rc=$?
+        if [[ "$compare_rc" -ne 0 ]]; then
+            echo -e "${RED}FAIL${NC} (compare_mf.py mismatch)"
+            ERRORS="$ERRORS\n  MF Co-Sim ($name): Python compare failed"
+            FAIL=$((FAIL + 1))
+            return
+        fi
+    else
+        echo -e "${YELLOW}SKIP${NC} (RTL passed, python3 not found — compare skipped)"
+        SKIP=$((SKIP + 1))
+        return
+    fi
+
+    echo -e "${GREEN}PASS${NC} (RTL + Python compare)"
+    PASS=$((PASS + 1))
+}
+
+# ---------------------------------------------------------------------------
+# Helper: compile, run, and compare a Doppler co-sim scenario
+#   run_doppler_cosim <scenario_name> <define_flag>
+# ---------------------------------------------------------------------------
+run_doppler_cosim() {
+    local name="$1"
+    local define="$2"
+    local vvp="tb/tb_doppler_cosim_${name}.vvp"
+
+    printf "  %-45s " "Doppler Co-Sim ($name)"
+
+    # Compile — build command as string to handle optional define
+    local cmd="iverilog -g2001 -DSIMULATION"
+    if [[ -n "$define" ]]; then
+        cmd="$cmd $define"
+    fi
+    cmd="$cmd -o $vvp tb/tb_doppler_cosim.v doppler_processor.v xfft_16.v fft_engine.v"
+
+    if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
+        echo -e "${RED}COMPILE FAIL${NC}"
+        ERRORS="$ERRORS\n  Doppler Co-Sim ($name): compile error ($(head -1 /tmp/iverilog_err_$$))"
+        FAIL=$((FAIL + 1))
+        return
+    fi
+
+    # Run TB
+    local output
+    output=$(timeout 120 vvp "$vvp" 2>&1) || true
+    rm -f "$vvp"
+
+    # Check TB internal pass/fail
+    local tb_fail
+    tb_fail=$(echo "$output" | grep -Ec '^\[FAIL' || true)
+    if [[ "$tb_fail" -gt 0 ]]; then
+        echo -e "${RED}FAIL${NC} (TB internal failure)"
+        ERRORS="$ERRORS\n  Doppler Co-Sim ($name): TB internal failure"
+        FAIL=$((FAIL + 1))
+        return
+    fi
+
+    # Run Python compare
+    if command -v python3 >/dev/null 2>&1; then
+        local compare_out
+        local compare_rc=0
+        compare_out=$(python3 tb/cosim/compare_doppler.py "$name" 2>&1) || compare_rc=$?
+        if [[ "$compare_rc" -ne 0 ]]; then
+            echo -e "${RED}FAIL${NC} (compare_doppler.py mismatch)"
+            ERRORS="$ERRORS\n  Doppler Co-Sim ($name): Python compare failed"
+            FAIL=$((FAIL + 1))
+            return
+        fi
+    else
+        echo -e "${YELLOW}SKIP${NC} (RTL passed, python3 not found — compare skipped)"
+        SKIP=$((SKIP + 1))
+        return
+    fi
+
+    echo -e "${GREEN}PASS${NC} (RTL + Python compare)"
+    PASS=$((PASS + 1))
+}
+
 # ---------------------------------------------------------------------------
 # Helper: compile and run a single testbench
 #   run_test <name> <vvp_path> <iverilog_args...>
 # ---------------------------------------------------------------------------
 run_test() {
+    # Optional: --timeout=N as first arg overrides default 120s
+    local timeout_secs=120
+    if [[ "$1" == --timeout=* ]]; then
+        timeout_secs="${1#--timeout=}"
+        shift
+    fi
+
     local name="$1"
     local vvp="$2"
     shift 2
@@ -275,7 +405,7 @@ run_test() {
 
     # Run
     local output
-    output=$(timeout 120 vvp "$vvp" 2>&1) || true
+    output=$(timeout "$timeout_secs" vvp "$vvp" 2>&1) || true
 
     # Count PASS/FAIL in output (testbenches use explicit [PASS]/[FAIL] markers)
     local test_pass test_fail
@@ -367,9 +497,9 @@ run_test "Chirp Contract" \
     tb/tb_chirp_ctr_reg.vvp \
     tb/tb_chirp_contract.v plfm_chirp_controller.v
 
-run_test "Doppler Processor (DSP48)" \
-    tb/tb_doppler_reg.vvp \
-    tb/tb_doppler_cosim.v doppler_processor.v xfft_16.v fft_engine.v
+run_doppler_cosim "stationary"   ""
+run_doppler_cosim "moving"       "-DSCENARIO_MOVING"
+run_doppler_cosim "two_targets"  "-DSCENARIO_TWO"
 
 run_test "Threshold Detector (detection bugs)" \
     tb/tb_threshold_detector.vvp \
@@ -416,30 +546,31 @@ run_test "Full-Chain Real-Data (decim→Doppler, exact match)" \
     doppler_processor.v xfft_16.v fft_engine.v
 
 if [[ "$QUICK" -eq 0 ]]; then
-    # Golden generate
-    run_test "Receiver (golden generate)" \
-        tb/tb_rx_golden_reg.vvp \
-        -DGOLDEN_GENERATE \
-        tb/tb_radar_receiver_final.v radar_receiver_final.v \
-        radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
-        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
-        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
-        chirp_memory_loader_param.v latency_buffer.v \
-        matched_filter_multi_segment.v matched_filter_processing_chain.v \
-        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
-        rx_gain_control.v mti_canceller.v
+    # NOTE: The "Receiver golden generate/compare" pair was REMOVED because
+    # it was self-blessing: both passes ran the same RTL with the same
+    # deterministic stimulus, so the test always passed regardless of bugs.
+    # Real co-sim coverage is provided by:
+    #   - tb_doppler_realdata.v  (committed Python golden hex, exact match)
+    #   - tb_fullchain_realdata.v (committed Python golden hex, exact match)
+    # A proper full-pipeline co-sim (DDC→MF→Decim→Doppler vs Python) is
+    # planned as a replacement (Phase C of CI test plan).
 
-    # Golden compare
-    run_test "Receiver (golden compare)" \
-        tb/tb_rx_compare_reg.vvp \
-        tb/tb_radar_receiver_final.v radar_receiver_final.v \
-        radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
+    # Receiver integration (structural + bounds + pulse assertions)
+    # Tests the full RX pipeline: ADC stub → DDC → MF → Decim → Doppler
+    # Verifies doppler_frame_done is a single-cycle pulse (catches
+    # level-vs-pulse wiring bugs at module boundaries).
+    run_test --timeout=600 "Receiver Integration (tb_radar_receiver_final)" \
+        tb/tb_rx_final_reg.vvp \
+        tb/tb_radar_receiver_final.v \
+        radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
         ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
         cdc_modules.v fir_lowpass.v ddc_input_interface.v \
+        rx_gain_control.v \
         chirp_memory_loader_param.v latency_buffer.v \
         matched_filter_multi_segment.v matched_filter_processing_chain.v \
-        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
-        rx_gain_control.v mti_canceller.v
+        range_bin_decimator.v mti_canceller.v \
+        doppler_processor.v xfft_16.v fft_engine.v \
+        radar_mode_controller.v
 
     # Full system top (monitoring-only, legacy)
     run_test "System Top (radar_system_tb)" \
@@ -469,12 +600,28 @@ if [[ "$QUICK" -eq 0 ]]; then
         usb_data_interface.v edge_detector.v radar_mode_controller.v \
         rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
 else
-    echo "  (skipped receiver golden + system top + E2E — use without --quick)"
-    SKIP=$((SKIP + 4))
+    echo "  (skipped system top + E2E — use without --quick)"
+    SKIP=$((SKIP + 2))
 fi
 
 echo ""
 
+# ===========================================================================
+# PHASE 2b: MATCHED FILTER CO-SIMULATION (RTL vs Python golden reference)
+# Runs tb_mf_cosim.v for 4 scenarios, then compare_mf.py validates output
+# against committed Python golden CSV files. In SIMULATION mode, thresholds
+# are generous (behavioral vs fixed-point twiddles differ) — validates
+# state machine mechanics, output count, and energy sanity.
+# ===========================================================================
+echo "--- PHASE 2b: Matched Filter Co-Sim ---"
+
+run_mf_cosim "chirp"   ""
+run_mf_cosim "dc"      "-DSCENARIO_DC"
+run_mf_cosim "impulse" "-DSCENARIO_IMPULSE"
+run_mf_cosim "tone5"   "-DSCENARIO_TONE5"
+
+echo ""
+
 # ===========================================================================
 # PHASE 3: UNIT TESTS — Signal Processing
 # ===========================================================================

9_Firmware/9_2_FPGA/rx_gain_control.v

@@ -54,7 +54,7 @@ module rx_gain_control (
     input  wire [3:0]  agc_decay,      // 0x2B: amplification step when weak (default 1)
     input  wire [3:0]  agc_holdoff,    // 0x2C: frames to wait before gain-up (default 4)
 
-    // Frame boundary pulse (1 clk cycle, from Doppler frame_complete)
+    // Frame boundary pulse (1 clk cycle, from edge detector in radar_receiver_final)
     input  wire        frame_boundary,
 
     // Data output (to matched filter)

9_Firmware/9_2_FPGA/tb/cosim/compare_doppler.py

@@ -34,8 +34,8 @@ sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
 # =============================================================================
 
 DOPPLER_FFT = 32
-RANGE_BINS = 64
-TOTAL_OUTPUTS = RANGE_BINS * DOPPLER_FFT  # 2048
+RANGE_BINS = 512
+TOTAL_OUTPUTS = RANGE_BINS * DOPPLER_FFT  # 16384
 SUBFRAME_SIZE = 16
 
 SCENARIOS = {
@@ -246,7 +246,7 @@ def compare_scenario(name, config, base_dir):
     # ---- Pass/Fail ----
     checks = []
 
-    checks.append(('RTL output count == 2048', count_ok))
+    checks.append(('RTL output count == 16384', count_ok))
 
     energy_ok = (ENERGY_RATIO_MIN < energy_ratio < ENERGY_RATIO_MAX)
     checks.append((f'Energy ratio in bounds '

9_Firmware/9_2_FPGA/tb/cosim/compare_mf.py

@@ -36,7 +36,7 @@ sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
 # Configuration
 # =============================================================================
 
-FFT_SIZE = 1024
+FFT_SIZE = 2048
 
 SCENARIOS = {
     'chirp': {
@@ -243,7 +243,7 @@ def compare_scenario(scenario_name, config, base_dir):
 
     # Check 2: RTL produced expected sample count
     correct_count = len(rtl_i) == FFT_SIZE
-    checks.append(('Correct output count (1024)', correct_count))
+    checks.append(('Correct output count (2048)', correct_count))
 
     # Check 3: Energy ratio within generous bounds
     # Allow very wide range since twiddle differences cause large gain variation

9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py

@@ -709,15 +709,24 @@ class DDCInputInterface:
 # FFT Engine (1024-point radix-2 DIT, in-place, 32-bit internal)
 # =============================================================================
 
-def load_twiddle_rom(filepath=None):
+def load_twiddle_rom(filepath=None, n=2048):
     """
-    Load 256-entry quarter-wave cosine ROM from hex file.
-    Returns list of 256 signed 16-bit integers.
+    Load quarter-wave cosine ROM from hex file.
+    Returns list of N/4 signed 16-bit integers.
+
+    For N=2048: loads fft_twiddle_2048.mem (512 entries).
+    For N=1024: loads fft_twiddle_1024.mem (256 entries).
+    For N=16:   loads fft_twiddle_16.mem (4 entries).
     """
     if filepath is None:
         # Default path relative to this file
         base = os.path.dirname(os.path.abspath(__file__))
-        filepath = os.path.join(base, '..', '..', 'fft_twiddle_1024.mem')
+        if n == 2048:
+            filepath = os.path.join(base, '..', '..', 'fft_twiddle_2048.mem')
+        elif n == 16:
+            filepath = os.path.join(base, '..', '..', 'fft_twiddle_16.mem')
+        else:
+            filepath = os.path.join(base, '..', '..', 'fft_twiddle_1024.mem')
 
     values = []
     with open(filepath) as f:
@@ -759,17 +768,17 @@ class FFTEngine:
     """
     Bit-accurate model of fft_engine.v
 
-    1024-point radix-2 DIT FFT/IFFT.
+    2048-point radix-2 DIT FFT/IFFT.
     Internal: 32-bit signed working data.
     Twiddle: 16-bit Q15 from quarter-wave cosine ROM.
     Butterfly: multiply 32x16->49 bits, >>>15, add/subtract.
     Output: saturate 32->16 bits. IFFT also >>>LOG2N before saturate.
     """
 
-    def __init__(self, n=1024, twiddle_file=None):
+    def __init__(self, n=2048, twiddle_file=None):
         self.N = n
         self.LOG2N = n.bit_length() - 1
-        self.cos_rom = load_twiddle_rom(twiddle_file)
+        self.cos_rom = load_twiddle_rom(twiddle_file, n=n)
         # Working memory (32-bit signed I/Q pairs)
         self.mem_re = [0] * n
         self.mem_im = [0] * n
@@ -942,21 +951,21 @@ class MatchedFilterChain:
     Uses a single FFTEngine instance (as in RTL, engine is reused).
     """
 
-    def __init__(self, fft_size=1024, twiddle_file=None):
+    def __init__(self, fft_size=2048, twiddle_file=None):
         self.fft_size = fft_size
         self.fft = FFTEngine(n=fft_size, twiddle_file=twiddle_file)
         self.conj_mult = FreqMatchedFilter()
 
     def process(self, sig_re, sig_im, ref_re, ref_im):
         """
-        Run matched filter on 1024-sample signal + reference.
+        Run matched filter on signal + reference.
 
         Args:
-            sig_re/im: signal I/Q (16-bit signed, 1024 samples)
-            ref_re/im: reference chirp I/Q (16-bit signed, 1024 samples)
+            sig_re/im: signal I/Q (16-bit signed, fft_size samples)
+            ref_re/im: reference chirp I/Q (16-bit signed, fft_size samples)
 
         Returns:
-            (range_profile_re, range_profile_im): 1024 x 16-bit signed
+            (range_profile_re, range_profile_im): fft_size x 16-bit signed
         """
         # Forward FFT of signal
         sig_fft_re, sig_fft_im = self.fft.compute(sig_re, sig_im, inverse=False)
@@ -984,27 +993,27 @@ class RangeBinDecimator:
     Bit-accurate model of range_bin_decimator.v
 
     Three modes:
-      00: Simple decimation (take center sample at index 8)
+      00: Simple decimation (take center sample at index 2)
       01: Peak detection (max |I|+|Q|)
-      10: Averaging (sum >> 4, truncation)
+      10: Averaging (sum >> 2, truncation)
       11: Reserved (output 0)
     """
 
-    DECIMATION_FACTOR = 16
-    OUTPUT_BINS = 64
+    DECIMATION_FACTOR = 4
+    OUTPUT_BINS = 512
 
     @staticmethod
     def decimate(range_re, range_im, mode=1, start_bin=0):
         """
-        Decimate 1024 range bins to 64.
+        Decimate 2048 range bins to 512.
 
         Args:
-            range_re/im: 1024 x signed 16-bit
+            range_re/im: 2048 x signed 16-bit
             mode: 0=center, 1=peak, 2=average, 3=zero
-            start_bin: first input bin to process (0-1023)
+            start_bin: first input bin to process (0-2047)
 
         Returns:
-            (out_re, out_im): 64 x signed 16-bit
+            (out_re, out_im): 512 x signed 16-bit
         """
         out_re = []
         out_im = []
@@ -1052,9 +1061,9 @@ class RangeBinDecimator:
                     if idx < len(range_re):
                         sum_re += sign_extend(range_re[idx] & 0xFFFF, 16)
                         sum_im += sign_extend(range_im[idx] & 0xFFFF, 16)
-                # Truncate (arithmetic right shift by 4), take 16 bits
-                out_re.append(sign_extend((sum_re >> 4) & 0xFFFF, 16))
-                out_im.append(sign_extend((sum_im >> 4) & 0xFFFF, 16))
+                # Truncate (arithmetic right shift by 2), take 16 bits
+                out_re.append(sign_extend((sum_re >> 2) & 0xFFFF, 16))
+                out_im.append(sign_extend((sum_im >> 2) & 0xFFFF, 16))
 
             else:
                 # Mode 3: reserved, output 0
@@ -1090,7 +1099,7 @@ class DopplerProcessor:
     """
 
     DOPPLER_FFT_SIZE = 16     # Per sub-frame
-    RANGE_BINS = 64
+    RANGE_BINS = 512
     CHIRPS_PER_FRAME = 32
     CHIRPS_PER_SUBFRAME = 16
 
@@ -1126,11 +1135,11 @@ class DopplerProcessor:
         Process one complete Doppler frame using dual 16-pt FFTs.
 
         Args:
-            chirp_data_i: 2D array [32 chirps][64 range bins] of signed 16-bit I
-            chirp_data_q: 2D array [32 chirps][64 range bins] of signed 16-bit Q
+            chirp_data_i: 2D array [32 chirps][512 range bins] of signed 16-bit I
+            chirp_data_q: 2D array [32 chirps][512 range bins] of signed 16-bit Q
 
         Returns:
-            (doppler_map_i, doppler_map_q): 2D arrays [64 range bins][32 doppler bins]
+            (doppler_map_i, doppler_map_q): 2D arrays [512 range bins][32 doppler bins]
                                             of signed 16-bit
                                             Bins 0-15 = sub-frame 0 (long PRI)
                                             Bins 16-31 = sub-frame 1 (short PRI)
@@ -1213,7 +1222,7 @@ class SignalChain:
     IF_FREQ = 120_000_000    # IF frequency
     FTW_120MHZ = 0x4CCCCCCD  # Phase increment for 120 MHz at 400 MSPS
 
-    def __init__(self, twiddle_file_1024=None, twiddle_file_16=None):
+    def __init__(self, twiddle_file_2048=None, twiddle_file_16=None):
         self.nco = NCO()
         self.mixer = Mixer()
         self.cic_i = CICDecimator()
@@ -1221,7 +1230,7 @@ class SignalChain:
         self.fir_i = FIRFilter()
         self.fir_q = FIRFilter()
         self.ddc_interface = DDCInputInterface()
-        self.matched_filter = MatchedFilterChain(fft_size=1024, twiddle_file=twiddle_file_1024)
+        self.matched_filter = MatchedFilterChain(fft_size=2048, twiddle_file=twiddle_file_2048)
         self.range_decimator = RangeBinDecimator()
         self.doppler = DopplerProcessor(twiddle_file_16=twiddle_file_16)
 

9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py

@@ -2,34 +2,22 @@
 """
 gen_chirp_mem.py — Generate all chirp .mem files for AERIS-10 FPGA.
 
-Generates the 10 chirp .mem files used by chirp_memory_loader_param.v:
-  - long_chirp_seg{0,1,2,3}_{i,q}.mem  (8 files, 1024 lines each)
-  - short_chirp_{i,q}.mem              (2 files, 50 lines each)
+Generates the 6 chirp .mem files used by chirp_memory_loader_param.v:
+  - long_chirp_seg{0,1}_{i,q}.mem  (4 files, 2048 lines each)
+  - short_chirp_{i,q}.mem          (2 files, 50 lines each)
 
 Long chirp:
   The 3000-sample baseband chirp (30 us at 100 MHz system clock) is
-  segmented into 4 blocks of 1024 samples.  Each segment covers a
+  segmented into 2 blocks of 2048 samples.  Each segment covers a
   different time window of the chirp:
-    seg0: samples   0 .. 1023
-    seg1: samples 1024 .. 2047
-    seg2: samples 2048 .. 3071  (only 952 valid chirp samples; 72 zeros)
-    seg3: all zeros (seg3 starts at sample 3072, past chirp end at 3000)
+    seg0: samples    0 .. 2047
+    seg1: samples 2048 .. 4095  (only 952 valid chirp samples; 1096 zeros)
 
-  Wait — actually the memory loader stores 4*1024 = 4096 contiguous
-  samples indexed by {segment_select[1:0], sample_addr[9:0]}.  The
-  long chirp has 3000 samples, so:
-    seg0: chirp[0..1023]
-    seg1: chirp[1024..2047]
-    seg2: chirp[2048..2999] + 24 zeros  (samples 2048..3071 but chirp
-          ends at 2999, so indices 3000..3071 relative to full chirp
-          => mem indices 952..1023 in seg2 file are zero)
-
-  Wait, let me re-count.  seg2 covers global indices 2048..3071.
-  The chirp has samples 0..2999 (3000 samples).  So seg2 has valid
-  data at global indices 2048..2999 = 952 valid samples (seg2 file
-  indices 0..951), then zeros at file indices 952..1023 (72 zeros).
-
-  seg3 covers global indices 3072..4095, all past chirp end => all zeros.
+  The memory loader stores 2*2048 = 4096 contiguous samples indexed
+  by {segment_select[0], sample_addr[10:0]}.  The long chirp has
+  3000 samples, so:
+    seg0: chirp[0..2047] — all valid data
+    seg1: chirp[2048..2999] + 1096 zeros (samples past chirp end)
 
 Short chirp:
   50 samples (0.5 us at 100 MHz), same chirp formula with
@@ -56,10 +44,10 @@ CHIRP_BW = 20e6           # 20 MHz sweep bandwidth
 FS_SYS = 100e6            # System clock (100 MHz, post-CIC)
 T_LONG_CHIRP = 30e-6      # 30 us long chirp duration
 T_SHORT_CHIRP = 0.5e-6    # 0.5 us short chirp duration
-FFT_SIZE = 1024
+FFT_SIZE = 2048
 LONG_CHIRP_SAMPLES = int(T_LONG_CHIRP * FS_SYS)   # 3000
 SHORT_CHIRP_SAMPLES = int(T_SHORT_CHIRP * FS_SYS)  # 50
-LONG_SEGMENTS = 4
+LONG_SEGMENTS = 2
 SCALE = 0.9               # Q15 scaling factor (matches radar_scene.py)
 Q15_MAX = 32767
 
@@ -187,13 +175,14 @@ def main():
     # Check magnitude envelope
     max(math.sqrt(i*i + q*q) for i, q in zip(long_i, long_q, strict=False))
 
-    # Check seg3 zero padding
-    seg3_i_path = os.path.join(MEM_DIR, 'long_chirp_seg3_i.mem')
-    with open(seg3_i_path) as f:
-        seg3_lines = [line.strip() for line in f if line.strip()]
-    nonzero_seg3 = sum(1 for line in seg3_lines if line != '0000')
+    # Check seg1 zero padding (samples 3000-4095 should be zero)
+    seg1_i_path = os.path.join(MEM_DIR, 'long_chirp_seg1_i.mem')
+    with open(seg1_i_path) as f:
+        seg1_lines = [line.strip() for line in f if line.strip()]
+    # Indices 952..2047 in seg1 (global 3000..4095) should be zero
+    nonzero_tail = sum(1 for line in seg1_lines[952:] if line != '0000')
 
-    if nonzero_seg3 == 0:
+    if nonzero_tail == 0:
         pass
     else:
         pass

9_Firmware/9_2_FPGA/tb/cosim/gen_doppler_golden.py

@@ -35,9 +35,9 @@ from radar_scene import Target, generate_doppler_frame
 
 DOPPLER_FFT_SIZE = 16     # Per sub-frame
 DOPPLER_TOTAL_BINS = 32   # Total output (2 sub-frames x 16)
-RANGE_BINS = 64
+RANGE_BINS = 512
 CHIRPS_PER_FRAME = 32
-TOTAL_SAMPLES = CHIRPS_PER_FRAME * RANGE_BINS  # 2048
+TOTAL_SAMPLES = CHIRPS_PER_FRAME * RANGE_BINS  # 16384
 
 
 # =============================================================================

9_Firmware/9_2_FPGA/tb/cosim/gen_mf_cosim_golden.py

@@ -30,7 +30,7 @@ from fpga_model import (
 )
 
 
-FFT_SIZE = 1024
+FFT_SIZE = 2048
 
 
 def load_hex_16bit(filepath):
@@ -143,9 +143,13 @@ def main():
         bb_q = load_hex_16bit(bb_q_path)
         ref_i = load_hex_16bit(ref_i_path)
         ref_q = load_hex_16bit(ref_q_path)
+        # Zero-pad to FFT_SIZE if shorter (legacy 1024-entry files → 2048)
+        for lst in [bb_i, bb_q, ref_i, ref_q]:
+            while len(lst) < FFT_SIZE:
+                lst.append(0)
         r = generate_case("chirp", bb_i, bb_q, ref_i, ref_q,
                           "Radar chirp: 2 targets (500m, 1500m) vs ref chirp",
-                          base_dir)
+                          base_dir, write_inputs=True)
         results.append(r)
     else:
         pass

9_Firmware/9_2_FPGA/tb/cosim/gen_multiseg_golden.py

@@ -5,8 +5,8 @@ gen_multiseg_golden.py
 Generate golden reference data for matched_filter_multi_segment co-simulation.
 
 Tests the overlap-save segmented convolution wrapper:
-  - Long chirp: 3072 samples (4 segments x 1024, with 128-sample overlap)
-  - Short chirp: 50 samples zero-padded to 1024 (1 segment)
+  - Long chirp: 3072 samples (2 segments x 2048, with overlap)
+  - Short chirp: 50 samples zero-padded to 2048 (1 segment)
 
 The matched_filter_processing_chain is already verified bit-perfect.
 This test validates that the multi_segment wrapper:
@@ -17,7 +17,7 @@ This test validates that the multi_segment wrapper:
 
 Strategy:
   - Generate known input data (identifiable per-segment patterns)
-  - Generate per-segment reference chirp data (1024 samples each)
+  - Generate per-segment reference chirp data (2048 samples each)
   - Run each segment through MatchedFilterChain independently in Python
   - Compare RTL multi-segment outputs against per-segment Python outputs
 
@@ -64,7 +64,7 @@ def generate_long_chirp_test():
       - buffer_write_ptr starts at 0 (from ST_IDLE reset)
       - Collects 896 samples into positions [0:895]
       - Positions [896:1023] remain zero (from initial block)
-      - Processes full 1024-sample buffer
+      - Processes full 2048-sample buffer
 
     For segment 1 (ST_NEXT_SEGMENT):
       - Copies input_buffer[SEGMENT_ADVANCE+i] to input_buffer[i] for i=0..127
@@ -89,7 +89,7 @@ def generate_long_chirp_test():
                           positions 0-895: input data
                           positions 896-1023: zeros from initial block
 
-    Processing chain sees: 1024 samples = [data[0:895], zeros[896:1023]]
+    Processing chain sees: 2048 samples = [data[0:1919], zeros[1920:2047]]
 
     OVERLAP-SAVE (ST_NEXT_SEGMENT):
       - Copies buffer[SEGMENT_ADVANCE+i] -> buffer[i] for i=0..OVERLAP-1
@@ -105,12 +105,12 @@ def generate_long_chirp_test():
         It was 896 after segment 0, then continues: 896+768 = 1664
 
     Actually I realize the overlap-save implementation in this RTL has an issue:
-    For segment 0, the buffer is only partially filled (896 out of 1024),
+    For segment 0, the buffer is only partially filled (1920 out of 2048),
     with zeros in positions 896-1023. The "overlap" that gets carried to
     segment 1 is those zeros, not actual signal data.
 
     A proper overlap-save would:
-    1. Fill the entire 1024-sample buffer for each segment
+    1. Fill the entire 2048-sample buffer for each segment
     2. The overlap region is the LAST 128 samples of the previous segment
 
     But this RTL only fills 896 samples per segment and relies on the
@@ -140,7 +140,7 @@ def generate_long_chirp_test():
     [768 new data samples at positions [128:895]] +
     [128 stale/zero samples at positions [896:1023]]
 
-    This is NOT standard overlap-save. It's a 1024-pt buffer but only
+    This is NOT standard overlap-save. It's a 2048-pt buffer but only
     896 positions are "active" for triggering, and positions 896-1023
     are never filled after init.
 
@@ -153,22 +153,16 @@ def generate_long_chirp_test():
     """
 
     # Parameters matching RTL
-    BUFFER_SIZE = 1024
+    BUFFER_SIZE = 2048
     OVERLAP_SAMPLES = 128
-    SEGMENT_ADVANCE = BUFFER_SIZE - OVERLAP_SAMPLES  # 896
-    LONG_SEGMENTS = 4
+    SEGMENT_ADVANCE = BUFFER_SIZE - OVERLAP_SAMPLES  # 1920
+    LONG_SEGMENTS = 2
 
-    # Total input samples needed:
-    # Segment 0: 896 samples (ptr goes from 0 to 896)
-    # Segment 1: 768 samples (ptr goes from 128 to 896)
-    # Segment 2: 768 samples (ptr goes from 128 to 896)
-    # Segment 3: 768 samples (ptr goes from 128 to 896)
-    # Total: 896 + 3*768 = 896 + 2304 = 3200
-    # But chirp_complete triggers at chirp_samples_collected >= LONG_CHIRP_SAMPLES-1 = 2999
-    # So the last segment may be truncated.
-    # Let's generate 3072 input samples (to be safe, more than 3000).
+    # Total input samples needed: seg0 needs 1920, seg1 needs 1792 (3712 total).
+    # chirp_complete triggers at chirp_samples_collected >= LONG_CHIRP_SAMPLES-1 (2999),
+    # so the last segment may be truncated. We generate 3800 samples to be safe.
 
-    TOTAL_SAMPLES = 3200  # More than enough for 4 segments
+    TOTAL_SAMPLES = 3800  # More than enough for 2 segments
 
     # Generate input signal: identifiable pattern per segment
     # Use a tone at different frequencies for each expected segment region
@@ -184,7 +178,7 @@ def generate_long_chirp_test():
         input_q.append(saturate(val_q, 16))
 
     # Generate per-segment reference chirps (just use known patterns)
-    # Each segment gets a different reference (1024 samples each)
+    # Each segment gets a different reference (2048 samples each)
     ref_segs_i = []
     ref_segs_q = []
     for seg in range(LONG_SEGMENTS):
@@ -202,7 +196,7 @@ def generate_long_chirp_test():
         ref_segs_q.append(ref_q)
 
     # Now simulate the RTL's overlap-save algorithm in Python
-    mf_chain = MatchedFilterChain(fft_size=1024)
+    mf_chain = MatchedFilterChain(fft_size=2048)
 
     # Simulate the buffer exactly as RTL does it
     input_buffer_i = [0] * BUFFER_SIZE
@@ -310,7 +304,7 @@ def generate_long_chirp_test():
         f.write('segment,bin,golden_i,golden_q\n')
         for seg in range(LONG_SEGMENTS):
             out_re, out_im = segment_results[seg]
-            for b in range(1024):
+            for b in range(2048):
                 f.write(f'{seg},{b},{out_re[b]},{out_im[b]}\n')
 
 
@@ -321,9 +315,9 @@ def generate_short_chirp_test():
     """
     Generate test data for single-segment short chirp.
 
-    Short chirp: 50 samples of data, zero-padded to 1024.
+    Short chirp: 50 samples of data, zero-padded to 2048.
     """
-    BUFFER_SIZE = 1024
+    BUFFER_SIZE = 2048
     SHORT_SAMPLES = 50
 
     # Generate 50-sample input
@@ -336,7 +330,7 @@ def generate_short_chirp_test():
         input_i.append(saturate(val_i, 16))
         input_q.append(saturate(val_q, 16))
 
-    # Zero-pad to 1024 (as RTL does in ST_ZERO_PAD)
+    # Zero-pad to 2048 (as RTL does in ST_ZERO_PAD)
     # Note: padding computed here for documentation; actual buffer uses buf_i/buf_q below
     _padded_i = list(input_i) + [0] * (BUFFER_SIZE - SHORT_SAMPLES)
     _padded_q = list(input_q) + [0] * (BUFFER_SIZE - SHORT_SAMPLES)
@@ -359,7 +353,7 @@ def generate_short_chirp_test():
             buf_i.append(0)
             buf_q.append(0)
 
-    # Reference chirp (1024 samples)
+    # Reference chirp (2048 samples)
     ref_i = []
     ref_q = []
     for n in range(BUFFER_SIZE):
@@ -370,7 +364,7 @@ def generate_short_chirp_test():
         ref_q.append(saturate(val_q, 16))
 
     # Process through MF chain
-    mf_chain = MatchedFilterChain(fft_size=1024)
+    mf_chain = MatchedFilterChain(fft_size=2048)
     out_re, out_im = mf_chain.process(buf_i, buf_q, ref_i, ref_q)
 
     # Write hex files
@@ -394,7 +388,7 @@ def generate_short_chirp_test():
     csv_path = os.path.join(out_dir, 'multiseg_short_golden.csv')
     with open(csv_path, 'w') as f:
         f.write('bin,golden_i,golden_q\n')
-        for b in range(1024):
+        for b in range(2048):
             f.write(f'{b},{out_re[b]},{out_im[b]}\n')
 
     return out_re, out_im
@@ -409,7 +403,7 @@ if __name__ == '__main__':
         # Find peak
         max_mag = 0
         peak_bin = 0
-        for b in range(1024):
+        for b in range(2048):
             mag = abs(out_re[b]) + abs(out_im[b])
             if mag > max_mag:
                 max_mag = mag
@@ -418,7 +412,7 @@ if __name__ == '__main__':
     short_re, short_im = generate_short_chirp_test()
     max_mag = 0
     peak_bin = 0
-    for b in range(1024):
+    for b in range(2048):
         mag = abs(short_re[b]) + abs(short_im[b])
         if mag > max_mag:
             max_mag = mag

9_Firmware/9_2_FPGA/tb/cosim/radar_scene.py

@@ -53,8 +53,8 @@ N_SAMPLES_LISTEN = int(T_LISTEN_LONG * FS_ADC)  # 54800 samples
 
 # Processing chain
 CIC_DECIMATION = 4
-FFT_SIZE = 1024
-RANGE_BINS = 64
+FFT_SIZE = 2048
+RANGE_BINS = 512
 DOPPLER_FFT_SIZE = 16      # Per sub-frame
 DOPPLER_TOTAL_BINS = 32    # Total output bins (2 sub-frames x 16)
 CHIRPS_PER_SUBFRAME = 16

9_Firmware/9_2_FPGA/tb/cosim/real_data/golden_reference.py

@@ -2,8 +2,8 @@
 """
 golden_reference.py — AERIS-10 FPGA bit-accurate golden reference model
 
-Uses ADI CN0566 Phaser radar data (10.525 GHz X-band FMCW) to validate
-the FPGA signal processing pipeline stage by stage:
+Uses ADI CN0566 Phaser radar data (10.525 GHz, used as test stimulus only) to
+validate the FPGA signal processing pipeline stage by stage:
 
     ADC → DDC (NCO+mixer+CIC+FIR) → Range FFT → Doppler FFT → Detection
 
@@ -69,7 +69,7 @@ FIR_COEFFS_HEX = [
 # DDC output interface
 DDC_OUT_BITS = 16                # 18 → 16 bit with rounding + saturation
 
-FFT_SIZE = 1024
+FFT_SIZE = 2048
 FFT_DATA_W = 16
 FFT_INTERNAL_W = 32
 FFT_TWIDDLE_W = 16
@@ -77,7 +77,7 @@ FFT_TWIDDLE_W = 16
 # Doppler — dual 16-pt FFT architecture
 DOPPLER_FFT_SIZE = 16            # per sub-frame
 DOPPLER_TOTAL_BINS = 32          # total output (2 sub-frames x 16)
-DOPPLER_RANGE_BINS = 64
+DOPPLER_RANGE_BINS = 512
 DOPPLER_CHIRPS = 32
 CHIRPS_PER_SUBFRAME = 16
 DOPPLER_WINDOW_TYPE = 0          # Hamming
@@ -90,7 +90,8 @@ HAMMING_Q15 = [
     0x3088, 0x1B6D, 0x0E5C, 0x0A3D,
 ]
 
-# ADI dataset parameters
+# ADI dataset parameters — used ONLY for loading/requantizing ADI Phaser test data.
+# These are NOT PLFM hardware parameters. See AERIS-10 constants below.
 ADI_SAMPLE_RATE = 4e6            # 4 MSPS
 ADI_IF_FREQ = 100e3             # 100 kHz IF
 ADI_RF_FREQ = 9.9e9             # 9.9 GHz
@@ -99,9 +100,17 @@ ADI_RAMP_TIME = 300e-6          # 300 us
 ADI_NUM_CHIRPS = 256
 ADI_SAMPLES_PER_CHIRP = 1079
 
-# AERIS-10 parameters
-AERIS_FS = 400e6                 # 400 MHz ADC clock
-AERIS_IF = 120e6                 # 120 MHz IF
+# AERIS-10 hardware parameters (from ADF4382/AD9523/main.cpp configuration)
+AERIS_FS = 400e6                 # 400 MHz ADC clock (AD9523 OUT4)
+AERIS_IF = 120e6                 # 120 MHz IF (TX 10.5 GHz - RX 10.38 GHz)
+AERIS_FS_PROCESSING = 100e6     # Post-DDC rate (400 MSPS / 4x CIC)
+AERIS_CARRIER_HZ = 10.5e9       # TX LO (ADF4382, verified)
+AERIS_RX_LO_HZ = 10.38e9        # RX LO (ADF4382)
+AERIS_CHIRP_BW = 20e6           # Chirp bandwidth (target: 30 MHz Phase 1)
+AERIS_LONG_CHIRP_S = 30e-6      # Long chirp duration
+AERIS_PRI_S = 167e-6            # Pulse repetition interval
+AERIS_DECIMATION = 4            # Range bin decimation (2048 → 512)
+AERIS_RANGE_PER_BIN = 6.0       # Meters per decimated bin
 
 
 # ===========================================================================
@@ -143,7 +152,7 @@ def load_and_quantize_adi_data(data_path, config_path, frame_idx=0):
     with a 120 MHz IF. We need to:
     1. Take one frame of 256 chirps x 1079 samples
     2. Use only 32 chirps (matching AERIS-10 CHIRPS_PER_FRAME)
-    3. Truncate to 1024 samples (matching FFT_SIZE)
+    3. Zero-pad to 2048 samples (matching FFT_SIZE)
     4. Upconvert to 120 MHz IF (add I*cos - Q*sin) to create real signal
     5. Quantize to 8-bit unsigned (matching AD9484)
     """
@@ -154,8 +163,10 @@ def load_and_quantize_adi_data(data_path, config_path, frame_idx=0):
     # Extract one frame
     frame = data[frame_idx]  # (256, 1079) complex
     
-    # Use first 32 chirps, first 1024 samples
-    iq_block = frame[:DOPPLER_CHIRPS, :FFT_SIZE]  # (32, 1024) complex
+    # Use first 32 chirps, zero-pad to FFT_SIZE samples
+    n_available = min(frame.shape[1], FFT_SIZE)
+    iq_block = np.zeros((DOPPLER_CHIRPS, FFT_SIZE), dtype=np.complex128)
+    iq_block[:, :n_available] = frame[:DOPPLER_CHIRPS, :n_available]
     
     # The ADI data is baseband complex IQ at 4 MSPS.
     # AERIS-10 sees a real signal at 400 MSPS with 120 MHz IF.
@@ -193,7 +204,10 @@ def load_and_quantize_adi_data(data_path, config_path, frame_idx=0):
     
     # Also create 8-bit ADC stimulus for DDC validation
     # Use just one chirp of real-valued data (I channel only, shifted to unsigned)
-    chirp0_real = np.real(frame[0, :FFT_SIZE])
+    # Zero-pad if needed (ADI has 1079 samples, FFT_SIZE may be larger)
+    chirp0_real = np.zeros(FFT_SIZE)
+    n_avail = min(frame.shape[1], FFT_SIZE)
+    chirp0_real[:n_avail] = np.real(frame[0, :n_avail])
     chirp0_norm = chirp0_real / np.max(np.abs(chirp0_real))
     adc_8bit = np.round(chirp0_norm * 127 + 128).astype(np.uint8)
     adc_8bit = np.clip(adc_8bit, 0, 255)
@@ -442,21 +456,21 @@ def fft_twiddle_lookup(k, N, cos_rom):
 
 def run_range_fft(iq_i, iq_q, twiddle_file=None):
     """
-    Bit-accurate 1024-point radix-2 DIT FFT matching fft_engine.v.
+    Bit-accurate radix-2 DIT FFT matching fft_engine.v.
     
-    Input: 16-bit signed I/Q arrays (1024 samples)
-    Output: 16-bit signed I/Q arrays (1024 bins, saturated from 32-bit internal)
+    Input: 16-bit signed I/Q arrays (N samples, N must be power of 2)
+    Output: 16-bit signed I/Q arrays (N bins, saturated from 32-bit internal)
     
     Matches RTL:
     - Bit-reversed input loading → sign-extended to 32-bit internal
-    - 10 stages of radix-2 butterflies
+    - LOG2(N) stages of radix-2 butterflies
     - Twiddle multiply: 32-bit * 16-bit = 48-bit, shift >>> 15
     - Add/subtract in 32-bit
     - Output: saturate 32-bit → 16-bit
     """
-    N = FFT_SIZE
+    N = len(iq_i)
     LOG2N = int(np.log2(N))
-    assert N == 1024 and LOG2N == 10
+    assert N == (1 << LOG2N), f"FFT size {N} is not a power of 2"
     
     # Load twiddle ROM
     if twiddle_file and os.path.exists(twiddle_file):
@@ -533,18 +547,18 @@ def run_range_fft(iq_i, iq_q, twiddle_file=None):
 # ===========================================================================
 def run_range_bin_decimator(range_fft_i, range_fft_q,
                             mode=1, start_bin=0,
-                            input_bins=1024, output_bins=64,
-                            decimation_factor=16):
+                            input_bins=2048, output_bins=512,
+                            decimation_factor=4):
     """
     Bit-accurate model of range_bin_decimator.v (peak detection mode).
 
-    Input:  range_fft_i/q — shape (N_chirps, 1024), 16-bit signed
-    Output: decimated_i/q — shape (N_chirps, 64), 16-bit signed
+    Input:  range_fft_i/q — shape (N_chirps, input_bins), 16-bit signed
+    Output: decimated_i/q — shape (N_chirps, output_bins), 16-bit signed
 
     Modes:
         0 = simple decimation (take center sample of each group)
-        1 = peak detection   (select max |I|+|Q| from each group of 16)
-        2 = averaging        (sum group >> 4)
+        1 = peak detection   (select max |I|+|Q| from each group)
+        2 = averaging        (sum group >> log2(decimation_factor))
 
     RTL detail: abs_i = I[15] ? (~I + 1) : I   (unsigned 16-bit)
                 cur_mag = {1'b0, abs_i} + {1'b0, abs_q}   (17-bit)
@@ -612,9 +626,10 @@ def run_range_bin_decimator(range_fft_i, range_fft_q,
                     sum_i += int(range_fft_i[c, in_idx])
                     sum_q += int(range_fft_q[c, in_idx])
                     in_idx += 1
-                # RTL: sum_i[19:4], truncation (not rounding)
-                decimated_i[c, obin] = int(sum_i) >> 4
-                decimated_q[c, obin] = int(sum_q) >> 4
+                # RTL: sum_i >> log2(decimation_factor), truncation (not rounding)
+                avg_shift = int(np.log2(decimation_factor))
+                decimated_i[c, obin] = int(sum_i) >> avg_shift
+                decimated_q[c, obin] = int(sum_q) >> avg_shift
 
 
     return decimated_i, decimated_q
@@ -627,7 +642,7 @@ def run_doppler_fft(range_data_i, range_data_q, twiddle_file_16=None):
     """
     Bit-accurate Doppler processor matching doppler_processor.v (dual 16-pt FFT).
 
-    Input: range_data_i/q shape (DOPPLER_CHIRPS, FFT_SIZE) — 16-bit signed
+    Input: range_data_i/q shape (DOPPLER_CHIRPS, N_range_bins) — 16-bit signed
            Only first DOPPLER_RANGE_BINS columns are processed.
     Output: doppler_map_i/q shape (DOPPLER_RANGE_BINS, DOPPLER_TOTAL_BINS) — 16-bit signed
 
@@ -1120,7 +1135,7 @@ def main():
         "amp_radar",
         "phaser_amp_4MSPS_500M_300u_256_m3dB_config.npy"
     )
-    twiddle_1024 = os.path.join(fpga_dir, "fft_twiddle_1024.mem")
+    twiddle_range = os.path.join(fpga_dir, "fft_twiddle_2048.mem")
     output_dir = os.path.join(script_dir, "hex")
     
     
@@ -1131,7 +1146,7 @@ def main():
         amp_data, amp_config, frame_idx=args.frame
     )
     
-    # iq_i, iq_q: (32, 1024) int64, 16-bit range — post-DDC equivalent
+    # iq_i, iq_q: (32, 2048) int64, 16-bit range — post-DDC equivalent (zero-padded)
     
     # -----------------------------------------------------------------------
     # Write stimulus files
@@ -1149,7 +1164,7 @@ def main():
     # -----------------------------------------------------------------------
     # Run range FFT on first chirp (bit-accurate)
     # -----------------------------------------------------------------------
-    range_fft_i, range_fft_q = run_range_fft(iq_i[0], iq_q[0], twiddle_1024)
+    range_fft_i, range_fft_q = run_range_fft(iq_i[0], iq_q[0], twiddle_range)
     write_hex_files(output_dir, range_fft_i, range_fft_q, "range_fft_chirp0")
     
     # Run range FFT on all 32 chirps
@@ -1157,7 +1172,7 @@ def main():
     all_range_q = np.zeros((DOPPLER_CHIRPS, FFT_SIZE), dtype=np.int64)
     
     for c in range(DOPPLER_CHIRPS):
-        ri, rq = run_range_fft(iq_i[c], iq_q[c], twiddle_1024)
+        ri, rq = run_range_fft(iq_i[c], iq_q[c], twiddle_range)
         all_range_i[c] = ri
         all_range_q[c] = rq
         if (c + 1) % 8 == 0:
@@ -1183,7 +1198,7 @@ def main():
         decimation_factor=FFT_SIZE // DOPPLER_RANGE_BINS
     )
     
-    # Write full-chain range FFT input: all 32 chirps x 1024 bins = 32768 samples
+    # Write full-chain range FFT input: all 32 chirps x 2048 bins = 65536 samples
     # This is the stimulus for the range_bin_decimator in the full-chain testbench.
     # Format: packed {Q[31:16], I[15:0]} per RTL range_data bus format
     fc_input_file = os.path.join(output_dir, "fullchain_range_input.hex")
@@ -1239,7 +1254,7 @@ def main():
     np.save(os.path.join(output_dir, "fullchain_mti_doppler_q.npy"), mti_doppler_q)
     
     # DC notch on MTI-Doppler data
-    DC_NOTCH_WIDTH = 2  # Default test value: zero bins {0, 1, 31}
+    DC_NOTCH_WIDTH = 2  # Default test value: zero bins {0, 1, 15, 16, 17, 31}
     notched_i, notched_q = run_dc_notch(mti_doppler_i, mti_doppler_q, width=DC_NOTCH_WIDTH)
     write_hex_files(output_dir, notched_i, notched_q, "fullchain_notched_ref")
     
@@ -1265,7 +1280,7 @@ def main():
     )
     
     # Write CFAR reference files
-    # 1. Magnitude map (17-bit unsigned, row-major: 64 range x 32 Doppler = 2048)
+    # 1. Magnitude map (17-bit unsigned, row-major: 512 range x 32 Doppler = 16384)
     cfar_mag_file = os.path.join(output_dir, "fullchain_cfar_mag.hex")
     with open(cfar_mag_file, 'w') as f:
         for rbin in range(DOPPLER_RANGE_BINS):