Merge remote-tracking branch 'origin/main' into fix/pre-bringup-audit-p0

Per-chirp T/R switching is owned by the FPGA plfm_chirp_controller
driving adar_tr_x pins (TR_SOURCE=1 in REG_SW_CONTROL, already set by
initializeSingleDevice). The MCU's SPI RMW path via fastTXMode/
fastRXMode/pulseTXMode/pulseRXMode/setADTR1107Control was:
  (a) architecturally redundant — raced the FPGA-driven TR line,
  (b) toggled the wrong bit (TR_SOURCE instead of TR_SPI),
  (c) in setFastSwitchMode(true) bundled a datasheet-violating
      PA+LNA-simultaneously-biased side effect.

Removed methods and their backing state (fast_switch_mode_,
switch_settling_time_us_). Call sites in executeChirpSequence /
runRadarPulseSequence updated to rely on the FPGA chirp FSM (GPIOD_8
new_chirp trigger unchanged).

Tests: adds CMSIS-Core DWT/CoreDebug/SystemCoreClock stubs to
stm32_hal_mock so F-4.7's DWT-based delayUs() compiles under the host
mock build. SystemCoreClock=0 makes the busy-wait exit immediately.

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp

@@ -10,15 +10,15 @@ extern SPI_HandleTypeDef hspi1;
 extern UART_HandleTypeDef huart3;
 
 // Chip Select GPIO definitions
-static const struct {
+static const struct {
-    GPIO_TypeDef* port;
+    GPIO_TypeDef* port;
-    uint16_t pin;
+    uint16_t pin;
-} CHIP_SELECTS[4] = {
+} CHIP_SELECTS[4] = {
-    {ADAR_1_CS_3V3_GPIO_Port, ADAR_1_CS_3V3_Pin}, // ADAR1000 #1
+    {ADAR_1_CS_3V3_GPIO_Port, ADAR_1_CS_3V3_Pin}, // ADAR1000 #1
-    {ADAR_2_CS_3V3_GPIO_Port, ADAR_2_CS_3V3_Pin}, // ADAR1000 #2
+    {ADAR_2_CS_3V3_GPIO_Port, ADAR_2_CS_3V3_Pin}, // ADAR1000 #2
-    {ADAR_3_CS_3V3_GPIO_Port, ADAR_3_CS_3V3_Pin}, // ADAR1000 #3
+    {ADAR_3_CS_3V3_GPIO_Port, ADAR_3_CS_3V3_Pin}, // ADAR1000 #3
-    {ADAR_4_CS_3V3_GPIO_Port, ADAR_4_CS_3V3_Pin}  // ADAR1000 #4
+    {ADAR_4_CS_3V3_GPIO_Port, ADAR_4_CS_3V3_Pin}  // ADAR1000 #4
-};
+};
 
 // ADAR1000 Vector Modulator lookup tables (128-state phase grid, 2.8125 deg step).
 //
@@ -163,8 +163,10 @@ void ADAR1000Manager::switchToTXMode() {
     DIAG("BF", "Step 3: PA bias ON");
     setPABias(true);
     delayUs(50);
-    DIAG("BF", "Step 4: ADTR1107 -> TX");
+    // Step 4 (former setADTR1107Control(true)) removed: TR pin is FPGA-owned.
-    setADTR1107Control(true);
+    // Chip follows adar_tr_x; TX path is asserted by the FPGA chirp FSM, not
+    // by SPI here. Write per-channel TX enables so the FPGA TR override has
+    // something to gate.
 
     for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
         adarWrite(dev, REG_RX_ENABLES, 0x00, BROADCAST_OFF);
@@ -185,8 +187,7 @@ void ADAR1000Manager::switchToRXMode() {
     DIAG("BF", "Step 2: Disable PA supplies");
     disablePASupplies();
     delayUs(10);
-    DIAG("BF", "Step 3: ADTR1107 -> RX");
+    // Step 3 (former setADTR1107Control(false)) removed: FPGA owns TR pin.
-    setADTR1107Control(false);
     DIAG("BF", "Step 4: Enable LNA supplies");
     enableLNASupplies();
     delayUs(50);
@@ -204,39 +205,11 @@ void ADAR1000Manager::switchToRXMode() {
     DIAG("BF", "switchToRXMode() complete");
 }
 
-void ADAR1000Manager::fastTXMode() {
+// fastTXMode, fastRXMode, pulseTXMode, pulseRXMode: REMOVED.
-    DIAG("BF", "fastTXMode(): ADTR1107 -> TX (no bias sequencing)");
+// The chirp hot path owns T/R switching via the FPGA adar_tr_x pins
-    setADTR1107Control(true);
+// (see 9_Firmware/9_2_FPGA/plfm_chirp_controller.v). The old SPI-RMW per
-    for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
+// chirp was architecturally redundant, raced the FPGA, and toggled the
-        adarWrite(dev, REG_RX_ENABLES, 0x00, BROADCAST_OFF);
+// wrong bit of REG_SW_CONTROL (TR_SOURCE instead of TR_SPI).
-        adarWrite(dev, REG_TX_ENABLES, 0x0F, BROADCAST_OFF);
-        devices_[dev]->current_mode = BeamDirection::TX;
-    }
-    current_mode_ = BeamDirection::TX;
-}
-
-void ADAR1000Manager::fastRXMode() {
-    DIAG("BF", "fastRXMode(): ADTR1107 -> RX (no bias sequencing)");
-    setADTR1107Control(false);
-    for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
-        adarWrite(dev, REG_TX_ENABLES, 0x00, BROADCAST_OFF);
-        adarWrite(dev, REG_RX_ENABLES, 0x0F, BROADCAST_OFF);
-        devices_[dev]->current_mode = BeamDirection::RX;
-    }
-    current_mode_ = BeamDirection::RX;
-}
-
-void ADAR1000Manager::pulseTXMode() {
-    DIAG("BF", "pulseTXMode(): TR switch only");
-    setADTR1107Control(true);
-    last_switch_time_us_ = HAL_GetTick() * 1000;
-}
-
-void ADAR1000Manager::pulseRXMode() {
-    DIAG("BF", "pulseRXMode(): TR switch only");
-    setADTR1107Control(false);
-    last_switch_time_us_ = HAL_GetTick() * 1000;
-}
 
 // Beam Steering
 bool ADAR1000Manager::setBeamAngle(float angle_degrees, BeamDirection direction) {
@@ -255,15 +228,15 @@ bool ADAR1000Manager::setBeamAngle(float angle_degrees, BeamDirection direction)
 
     for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
         for (uint8_t ch = 0; ch < 4; ++ch) {
-            if (direction == BeamDirection::TX) {
+            if (direction == BeamDirection::TX) {
-                adarSetTxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
+                adarSetTxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
-                adarSetTxVgaGain(dev, ch + 1, kDefaultTxVgaGain, BROADCAST_OFF);
+                adarSetTxVgaGain(dev, ch + 1, kDefaultTxVgaGain, BROADCAST_OFF);
-            } else {
+            } else {
-                adarSetRxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
+                adarSetRxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
-                adarSetRxVgaGain(dev, ch + 1, kDefaultRxVgaGain, BROADCAST_OFF);
+                adarSetRxVgaGain(dev, ch + 1, kDefaultRxVgaGain, BROADCAST_OFF);
-            }
+            }
-        }
+        }
-    }
+    }
     return true;
 }
 
@@ -368,25 +341,10 @@ void ADAR1000Manager::writeRegister(uint8_t deviceIndex, uint32_t address, uint8
 }
 
 // Configuration
-void ADAR1000Manager::setSwitchSettlingTime(uint32_t us) {
+// setSwitchSettlingTime, setFastSwitchMode: REMOVED.
-    switch_settling_time_us_ = us;
+// Their only reader was the deleted setADTR1107Control; setFastSwitchMode(true)
-}
+// also violated the ADTR1107 datasheet bias sequence (PA + LNA biased to
-
+// operational simultaneously). Per-chirp T/R is FPGA-owned now.
-void ADAR1000Manager::setFastSwitchMode(bool enable) {
-    DIAG("BF", "setFastSwitchMode(%s)", enable ? "ON" : "OFF");
-    fast_switch_mode_ = enable;
-    if (enable) {
-        switch_settling_time_us_ = 10;
-        DIAG("BF", "  settling time = 10 us, enabling PA+LNA supplies and bias simultaneously");
-        enablePASupplies();
-        enableLNASupplies();
-        setPABias(true);
-        setLNABias(true);
-    } else {
-        switch_settling_time_us_ = 50;
-        DIAG("BF", "  settling time = 50 us");
-    }
-}
 
 void ADAR1000Manager::setBeamDwellTime(uint32_t ms) {
     beam_dwell_time_ms_ = ms;
@@ -428,15 +386,30 @@ bool ADAR1000Manager::initializeSingleDevice(uint8_t deviceIndex) {
     DIAG("BF", "  dev[%u] set RAM bypass (bias+beam)", deviceIndex);
     adarSetRamBypass(deviceIndex, BROADCAST_OFF);
 
+    // Hand per-chirp T/R switching to the FPGA.
+    // Set TR_SOURCE (REG_SW_CONTROL bit 2) = 1 so the chip's internal
+    // RX_EN_OVERRIDE / TX_EN_OVERRIDE follow the external TR pin (driven by
+    // plfm_chirp_controller's adar_tr_x output). See ADAR1000 datasheet
+    // "Theory of Operation" -- SPI Control vs TR Pin Control.
+    // Without this write, the FPGA's TR pin is ignored and the chip stays
+    // in RX state (TR_SPI POR default).
+    DIAG("BF", "  dev[%u] SW_CONTROL: TR_SOURCE=1 (FPGA owns TR pin)", deviceIndex);
+    adarWrite(deviceIndex, REG_SW_CONTROL, (1 << 2), BROADCAST_OFF);
+
     // Initialize ADC
     DIAG("BF", "  dev[%u] enable ADC (2MHz clk)", deviceIndex);
     adarWrite(deviceIndex, REG_ADC_CONTROL, ADAR1000_ADC_2MHZ_CLK | ADAR1000_ADC_EN, BROADCAST_OFF);
 
     // Verify communication with scratchpad test
+    // Audit F-4.4: on SPI failure, previously marked the device initialized
+    // anyway, so downstream (e.g. PA enable) could drive PA gates out-of-spec
+    // on a dead bus. Now propagate the failure so initializeAllDevices aborts.
     DIAG("BF", "  dev[%u] verifying SPI communication...", deviceIndex);
     bool comms_ok = verifyDeviceCommunication(deviceIndex);
     if (!comms_ok) {
-        DIAG_WARN("BF", "  dev[%u] scratchpad verify FAILED but marking initialized anyway", deviceIndex);
+        DIAG_ERR("BF", "  dev[%u] scratchpad verify FAILED -- device NOT marked initialized", deviceIndex);
+        devices_[deviceIndex]->initialized = false;
+        return false;
     }
 
     devices_[deviceIndex]->initialized = true;
@@ -464,9 +437,11 @@ bool ADAR1000Manager::initializeADTR1107Sequence() {
     HAL_GPIO_WritePin(EN_P_3V3_SW_GPIO_Port, EN_P_3V3_SW_Pin, GPIO_PIN_SET);
     HAL_Delay(1);
 
-    // Step 4: Set CTRL_SW to RX mode initially via GPIO
+    // Step 4: CTRL_SW safe-default is RX.
-    DIAG("BF", "Step 4: CTRL_SW -> RX (initial safe mode)");
+    // FPGA-owned path: with TR_SOURCE=1 (set in initializeSingleDevice) the
-    setADTR1107Control(false); // RX mode
+    // chip follows adar_tr_x, which is 0 in the FPGA FSM's IDLE state = RX.
+    // No SPI write needed here.
+    DIAG("BF", "Step 4: CTRL_SW -> RX (FPGA adar_tr_x idle-low == RX)");
     HAL_Delay(1);
 
     // Step 5: Set VGG_LNA to 0
@@ -522,7 +497,7 @@ bool ADAR1000Manager::initializeADTR1107Sequence() {
     HAL_UART_Transmit(&huart3, success, sizeof(success) - 1, 1000);
 
     return true;
-}
+}
 
 bool ADAR1000Manager::setAllDevicesTXMode() {
     DIAG("BF", "setAllDevicesTXMode(): ADTR1107 -> TX, then configure ADAR1000s");
@@ -568,7 +543,7 @@ bool ADAR1000Manager::setAllDevicesRXMode() {
 void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
     if (direction == BeamDirection::TX) {
         DIAG_SECTION("ADTR1107 -> TX MODE");
-        setADTR1107Control(true); // TX mode
+        // setADTR1107Control(true) removed: TR pin is FPGA-driven.
 
         // Step 1: Disable LNA power first
         DIAG("BF", "  Disable LNA supplies");
@@ -598,10 +573,11 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
         }
         HAL_Delay(5);
 
-        // Step 5: Set TR switch to TX mode
+        // Step 5: TR switch state is FPGA-driven. TR_SOURCE=1 is set once in
-        DIAG("BF", "  TR switch -> TX (TR_SOURCE=1, BIAS_EN)");
+        // initializeSingleDevice, so the chip already follows adar_tr_x.
+        // Only BIAS_EN needs to be asserted here.
+        DIAG("BF", "  BIAS_EN (TR source still = FPGA adar_tr_x)");
         for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
-            adarSetBit(dev, REG_SW_CONTROL, 2, BROADCAST_OFF); // TR_SOURCE = 1 (TX)
             adarSetBit(dev, REG_MISC_ENABLES, 5, BROADCAST_OFF); // BIAS_EN
         }
         DIAG("BF", "  ADTR1107 TX mode complete");
@@ -609,7 +585,7 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
     } else {
         // RECEIVE MODE: Enable LNA, Disable PA
         DIAG_SECTION("ADTR1107 -> RX MODE");
-        setADTR1107Control(false); // RX mode
+        // setADTR1107Control(false) removed: TR pin is FPGA-driven.
 
         // Step 1: Disable PA power first
         DIAG("BF", "  Disable PA supplies");
@@ -640,34 +616,21 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
         }
         HAL_Delay(5);
 
-        // Step 5: Set TR switch to RX mode
+        // Step 5: TR switch state is FPGA-driven (TR_SOURCE left at 1).
-        DIAG("BF", "  TR switch -> RX (TR_SOURCE=0, LNA_BIAS_OUT_EN)");
+        // Only LNA_BIAS_OUT_EN needs to be asserted here.
+        DIAG("BF", "  LNA_BIAS_OUT_EN (TR source still = FPGA adar_tr_x)");
         for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
-            adarResetBit(dev, REG_SW_CONTROL, 2, BROADCAST_OFF); // TR_SOURCE = 0 (RX)
             adarSetBit(dev, REG_MISC_ENABLES, 4, BROADCAST_OFF); // LNA_BIAS_OUT_EN
         }
         DIAG("BF", "  ADTR1107 RX mode complete");
     }
-}
-
-void ADAR1000Manager::setADTR1107Control(bool tx_mode) {
-    DIAG("BF", "setADTR1107Control(%s): setting TR switch on all %u devices, settling %lu us",
-         tx_mode ? "TX" : "RX", (unsigned)devices_.size(), (unsigned long)switch_settling_time_us_);
-    for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
-        setTRSwitchPosition(dev, tx_mode);
-    }
-    delayUs(switch_settling_time_us_);
 }
 
-void ADAR1000Manager::setTRSwitchPosition(uint8_t deviceIndex, bool tx_mode) {
+// setADTR1107Control, setTRSwitchPosition: REMOVED.
-    if (tx_mode) {
+// The per-device SPI RMW of REG_SW_CONTROL bit 2 (TR_SOURCE) was both wrong
-        // TX mode: Set TR_SOURCE = 1
+// (it toggled the *control source*, not the TX/RX state -- TR_SPI is bit 1)
-        adarSetBit(deviceIndex, REG_SW_CONTROL, 2, BROADCAST_OFF);
+// and redundant with the FPGA's plfm_chirp_controller adar_tr_x output.
-    } else {
+// TR_SOURCE is now set to 1 exactly once in initializeSingleDevice.
-        // RX mode: Set TR_SOURCE = 0
-        adarResetBit(deviceIndex, REG_SW_CONTROL, 2, BROADCAST_OFF);
-    }
-}
 
 // Add the new public method
 bool ADAR1000Manager::setCustomBeamPattern16(const uint8_t phase_pattern[16], BeamDirection direction) {
@@ -727,13 +690,24 @@ void ADAR1000Manager::setLNABias(bool enable) {
     for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
         adarWrite(dev, REG_LNA_BIAS_ON, lna_bias, BROADCAST_OFF);
     }
-}
+}
 
 void ADAR1000Manager::delayUs(uint32_t microseconds) {
-    // Simple implementation - for F7 @ 216MHz, each loop ~7 cycles ≈ 0.032us
+    // Audit F-4.7: the prior implementation was a calibrated __NOP() busy-loop
-    volatile uint32_t cycles = microseconds * 10; // Adjust this multiplier for your clock
+    // that silently drifted with compiler optimization, cache state, and flash
-    while (cycles--) {
+    // wait-states. The ADAR1000 PLL/TX settling times require a real clock, so
-        __NOP();
+    // we poll the DWT cycle counter instead. One-time TRCENA/CYCCNTENA enable
+    // is idempotent; subsequent calls skip the init branch via DWT->CTRL read.
+    if ((DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk) == 0U) {
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+        DWT->CYCCNT       = 0U;
+        DWT->CTRL        |= DWT_CTRL_CYCCNTENA_Msk;
+    }
+    const uint32_t cycles_per_us = SystemCoreClock / 1000000U;
+    const uint32_t start         = DWT->CYCCNT;
+    const uint32_t target        = microseconds * cycles_per_us;
+    while ((DWT->CYCCNT - start) < target) {
+        /* CYCCNT wraps cleanly modulo 2^32 — subtraction stays correct. */
     }
 }
 
@@ -795,14 +769,25 @@ void ADAR1000Manager::setChipSelect(uint8_t deviceIndex, bool state) {
 }
 
 void ADAR1000Manager::adarWrite(uint8_t deviceIndex, uint32_t mem_addr, uint8_t data, uint8_t broadcast) {
-    uint8_t instruction[3];
+    // Audit F-4.1: the broadcast SPI opcode path (`instruction[0] = 0x08`)
-
+    // has never been exercised on silicon and is structurally questionable —
-    if (broadcast) {
+    // setChipSelect() only toggles ONE device's CS line, so even if a caller
-        instruction[0] = 0x08;
+    // opts into the broadcast opcode today, only the single selected chip
-    } else {
+    // actually sees the frame. Until a HIL test confirms multi-CS semantics,
-        instruction[0] = ((devices_[deviceIndex]->dev_addr & 0x03) << 5);
+    // route every broadcast write through a per-device unicast loop. This
+    // preserves caller intent (all four devices take the write) and makes
+    // the dead opcode-0x08 path unreachable at runtime.
+    if (broadcast == BROADCAST_ON) {
+        DIAG_WARN("BF", "adarWrite: broadcast=1 lowered to per-device unicast (addr=0x%03lX data=0x%02X)",
+                  (unsigned long)mem_addr, data);
+        for (uint8_t d = 0; d < devices_.size(); ++d) {
+            adarWrite(d, mem_addr, data, BROADCAST_OFF);
+        }
+        return;
     }
 
+    uint8_t instruction[3];
+    instruction[0] = ((devices_[deviceIndex]->dev_addr & 0x03) << 5);
     instruction[0] |= (0x1F00 & mem_addr) >> 8;
     instruction[1] = (0xFF & mem_addr);
     instruction[2] = data;
@@ -835,12 +820,26 @@ uint8_t ADAR1000Manager::adarRead(uint8_t deviceIndex, uint32_t mem_addr) {
 }
 
 void ADAR1000Manager::adarSetBit(uint8_t deviceIndex, uint32_t mem_addr, uint8_t bit, uint8_t broadcast) {
+    // Audit F-4.2: broadcast-RMW is unsafe. The read samples a single device
+    // but the write fans out to all four, overwriting the other three with
+    // deviceIndex's state. Reject and surface the mistake.
+    if (broadcast == BROADCAST_ON) {
+        DIAG_ERR("BF", "adarSetBit: broadcast RMW is unsafe, ignored (dev=%u addr=0x%03lX bit=%u)",
+                 deviceIndex, (unsigned long)mem_addr, bit);
+        return;
+    }
     uint8_t temp = adarRead(deviceIndex, mem_addr);
     uint8_t data = temp | (1 << bit);
     adarWrite(deviceIndex, mem_addr, data, broadcast);
 }
 
 void ADAR1000Manager::adarResetBit(uint8_t deviceIndex, uint32_t mem_addr, uint8_t bit, uint8_t broadcast) {
+    // Audit F-4.2: see adarSetBit.
+    if (broadcast == BROADCAST_ON) {
+        DIAG_ERR("BF", "adarResetBit: broadcast RMW is unsafe, ignored (dev=%u addr=0x%03lX bit=%u)",
+                 deviceIndex, (unsigned long)mem_addr, bit);
+        return;
+    }
     uint8_t temp = adarRead(deviceIndex, mem_addr);
     uint8_t data = temp & ~(1 << bit);
     adarWrite(deviceIndex, mem_addr, data, broadcast);
@@ -904,7 +903,7 @@ void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8
 
     adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
     adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
-    adarWrite(deviceIndex, REG_LOAD_WORKING, 0x1, broadcast);
+    adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
 }
 
 void ADAR1000Manager::adarSetRxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
@@ -929,11 +928,11 @@ void ADAR1000Manager::adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uin
     adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
 }
 
-void ADAR1000Manager::adarSetTxBias(uint8_t deviceIndex, uint8_t broadcast) {
+void ADAR1000Manager::adarSetTxBias(uint8_t deviceIndex, uint8_t broadcast) {
-    adarWrite(deviceIndex, REG_BIAS_CURRENT_TX, kTxBiasCurrent, broadcast);
+    adarWrite(deviceIndex, REG_BIAS_CURRENT_TX, kTxBiasCurrent, broadcast);
-    adarWrite(deviceIndex, REG_BIAS_CURRENT_TX_DRV, kTxDriverBiasCurrent, broadcast);
+    adarWrite(deviceIndex, REG_BIAS_CURRENT_TX_DRV, kTxDriverBiasCurrent, broadcast);
-    adarWrite(deviceIndex, REG_LOAD_WORKING, 0x2, broadcast);
+    adarWrite(deviceIndex, REG_LOAD_WORKING, 0x2, broadcast);
-}
+}
 
 uint8_t ADAR1000Manager::adarAdcRead(uint8_t deviceIndex, uint8_t broadcast) {
     adarWrite(deviceIndex, REG_ADC_CONTROL, ADAR1000_ADC_ST_CONV, broadcast);

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.h

@@ -48,10 +48,11 @@ public:
     // Mode Switching
     void switchToTXMode();
     void switchToRXMode();
-    void fastTXMode();
+    // fastTXMode/fastRXMode/pulseTXMode/pulseRXMode were removed: per-chirp T/R
-    void fastRXMode();
+    // switching is owned by the FPGA (plfm_chirp_controller -> adar_tr_x pins,
-    void pulseTXMode();
+    // requires TR_SOURCE=1 in REG_SW_CONTROL, set in initializeSingleDevice).
-    void pulseRXMode();
+    // The old SPI RMW path was architecturally redundant and also toggled the
+    // wrong bit (TR_SOURCE instead of TR_SPI). See PR for details.
 
     // Beam Steering
     bool setBeamAngle(float angle_degrees, BeamDirection direction);
@@ -69,7 +70,8 @@ public:
     bool setAllDevicesTXMode();
     bool setAllDevicesRXMode();
     void setADTR1107Mode(BeamDirection direction);
-    void setADTR1107Control(bool tx_mode);
+    // setADTR1107Control removed -- it only wrapped the now-deleted
+    // setTRSwitchPosition SPI path. FPGA drives the TR pin directly.
 
     // Monitoring and Diagnostics
     float readTemperature(uint8_t deviceIndex);
@@ -78,8 +80,11 @@ public:
     void writeRegister(uint8_t deviceIndex, uint32_t address, uint8_t value);
 
     // Configuration
-    void setSwitchSettlingTime(uint32_t us);
+    // setSwitchSettlingTime / setFastSwitchMode removed: their only reader was
-    void setFastSwitchMode(bool enable);
+    // the deleted setADTR1107Control SPI path, and setFastSwitchMode(true)
+    // also bundled a datasheet-violating PA+LNA-biased-simultaneously side
+    // effect. Per-chirp settling is now FPGA-owned. Callers that need a
+    // warm-up bias state should use switchToTXMode / switchToRXMode instead.
     void setBeamDwellTime(uint32_t ms);
 
     // Getters
@@ -100,8 +105,8 @@ public:
     };
 
     // Configuration
-    bool fast_switch_mode_ = false;
+    // fast_switch_mode_ / switch_settling_time_us_ removed: both had no
-    uint32_t switch_settling_time_us_ = 50;
+    // readers after the FPGA-owned TR refactor.
     uint32_t beam_dwell_time_ms_ = 100;
     uint32_t last_switch_time_us_ = 0;
 
@@ -121,22 +126,22 @@ public:
     // No VM_GAIN[] table exists: VM magnitude is bits [4:0] of the I/Q bytes
     // themselves; per-channel VGA gain uses a separate register.
     static const uint8_t VM_I[128];
-    static const uint8_t VM_Q[128];
+    static const uint8_t VM_Q[128];
-
+
-    // Named defaults for the ADTR1107 and ADAR1000 power sequence.
+    // Named defaults for the ADTR1107 and ADAR1000 power sequence.
-    static constexpr uint8_t kDefaultTxVgaGain = 0x7F;
+    static constexpr uint8_t kDefaultTxVgaGain = 0x7F;
-    static constexpr uint8_t kDefaultRxVgaGain = 30;
+    static constexpr uint8_t kDefaultRxVgaGain = 30;
-    static constexpr uint8_t kLnaBiasOff = 0x00;
+    static constexpr uint8_t kLnaBiasOff = 0x00;
-    static constexpr uint8_t kLnaBiasOperational = 0x30;
+    static constexpr uint8_t kLnaBiasOperational = 0x30;
-    static constexpr uint8_t kPaBiasTxSafe = 0x5D;
+    static constexpr uint8_t kPaBiasTxSafe = 0x5D;
-    static constexpr uint8_t kPaBiasIdqCalibration = 0x0D;
+    static constexpr uint8_t kPaBiasIdqCalibration = 0x0D;
-    static constexpr uint8_t kPaBiasOperational = 0x7F;
+    static constexpr uint8_t kPaBiasOperational = 0x7F;
-    static constexpr uint8_t kPaBiasRxSafe = 0x20;
+    static constexpr uint8_t kPaBiasRxSafe = 0x20;
-    static constexpr uint8_t kTxBiasCurrent = 0x2D;
+    static constexpr uint8_t kTxBiasCurrent = 0x2D;
-    static constexpr uint8_t kTxDriverBiasCurrent = 0x06;
+    static constexpr uint8_t kTxDriverBiasCurrent = 0x06;
-
+
-    // Private Methods
+    // Private Methods
-    bool initializeSingleDevice(uint8_t deviceIndex);
+    bool initializeSingleDevice(uint8_t deviceIndex);
     bool initializeADTR1107Sequence();
     void calculatePhaseSettings(float angle_degrees, uint8_t phase_settings[4]);
     void delayUs(uint32_t microseconds);
@@ -167,7 +172,7 @@ public:
     void adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast);
     void adarSetTxBias(uint8_t deviceIndex, uint8_t broadcast);
     uint8_t adarAdcRead(uint8_t deviceIndex, uint8_t broadcast);
-    void setTRSwitchPosition(uint8_t deviceIndex, bool tx_mode);
+    // setTRSwitchPosition removed -- FPGA owns TR pin. See PR.
 
 private:
 

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h

@@ -112,7 +112,7 @@ extern "C" {
  *   "BF"    -- ADAR1000 beamformer
  *   "PA"    -- Power amplifier bias/monitoring
  *   "FPGA"  -- FPGA communication and handshake
- *   "USB"   -- FT601 USB data path
+ *   "USB"   -- USB data path (FT2232H production / FT601 premium)
  *   "PWR"   -- Power sequencing and rail monitoring
  *   "IMU"   -- IMU/GPS/barometer sensors
  *   "MOT"   -- Stepper motor/scan mechanics

9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp

@@ -483,11 +483,14 @@ void executeChirpSequence(int num_chirps, float T1, float PRI1, float T2, float
     DIAG("SYS", "executeChirpSequence: num_chirps=%d T1=%.2f PRI1=%.2f T2=%.2f PRI2=%.2f",
          num_chirps, T1, PRI1, T2, PRI2);
     // First chirp sequence (microsecond timing)
+    // T/R switching is owned by the FPGA plfm_chirp_controller: its chirp
+    // FSM drives adar_tr_x high during LONG_CHIRP/SHORT_CHIRP and low during
+    // listen/guard. new_chirp (GPIOD_8) triggers the FSM out of IDLE.
+    // The MCU's old pulseTXMode/pulseRXMode SPI path was redundant and raced
+    // the FPGA -- removed.
     for(int i = 0; i < num_chirps; i++) {
         HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_8); // New chirp signal to FPGA
-        adarManager.pulseTXMode();
         delay_us((uint32_t)T1);
-        adarManager.pulseRXMode();
         delay_us((uint32_t)(PRI1 - T1));
     }
 
@@ -496,11 +499,8 @@ void executeChirpSequence(int num_chirps, float T1, float PRI1, float T2, float
     // Second chirp sequence (nanosecond timing)
     for(int i = 0; i < num_chirps; i++) {
     	HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_8); // New chirp signal to FPGA
-        adarManager.pulseTXMode();
         delay_ns((uint32_t)(T2 * 1000));
-        adarManager.pulseRXMode();
         delay_ns((uint32_t)((PRI2 - T2) * 1000));
-
     }
 }
 
@@ -513,9 +513,9 @@ void runRadarPulseSequence() {
     DIAG("SYS", "runRadarPulseSequence #%d: m_max=%d n_max=%d y_max=%d",
          sequence_count, m_max, n_max, y_max);
 
-    // Configure for fast switching
+    // Fast per-chirp switching is now FPGA-owned (plfm_chirp_controller
-    DIAG("BF", "Enabling fast-switch mode for beam sweep");
+    // adar_tr_x), not MCU-driven. setFastSwitchMode(true) call removed.
-    adarManager.setFastSwitchMode(true);
+    DIAG("BF", "Beam sweep start (FPGA owns per-chirp T/R switching)");
 
     int m = 1; // Chirp counter
     int n = 1; // Beam Elevation position counter
@@ -656,18 +656,18 @@ SystemError_t checkSystemHealth(void) {
 
     // 1. Check AD9523 Clock Generator
     static uint32_t last_clock_check = 0;
-    if (HAL_GetTick() - last_clock_check > 5000) {
+    if (HAL_GetTick() - last_clock_check > 5000) {
-        GPIO_PinState s0 = HAL_GPIO_ReadPin(AD9523_STATUS0_GPIO_Port, AD9523_STATUS0_Pin);
+        GPIO_PinState s0 = HAL_GPIO_ReadPin(AD9523_STATUS0_GPIO_Port, AD9523_STATUS0_Pin);
-        GPIO_PinState s1 = HAL_GPIO_ReadPin(AD9523_STATUS1_GPIO_Port, AD9523_STATUS1_Pin);
+        GPIO_PinState s1 = HAL_GPIO_ReadPin(AD9523_STATUS1_GPIO_Port, AD9523_STATUS1_Pin);
-        DIAG_GPIO("CLK", "AD9523 STATUS0", s0);
+        DIAG_GPIO("CLK", "AD9523 STATUS0", s0);
-        DIAG_GPIO("CLK", "AD9523 STATUS1", s1);
+        DIAG_GPIO("CLK", "AD9523 STATUS1", s1);
-        if (s0 == GPIO_PIN_RESET || s1 == GPIO_PIN_RESET) {
+        if (s0 == GPIO_PIN_RESET || s1 == GPIO_PIN_RESET) {
-            current_error = ERROR_AD9523_CLOCK;
+            current_error = ERROR_AD9523_CLOCK;
-            DIAG_ERR("CLK", "AD9523 clock health check FAILED (STATUS0=%d STATUS1=%d)", s0, s1);
+            DIAG_ERR("CLK", "AD9523 clock health check FAILED (STATUS0=%d STATUS1=%d)", s0, s1);
-            return current_error;
+            return current_error;
-        }
+        }
-        last_clock_check = HAL_GetTick();
+        last_clock_check = HAL_GetTick();
-    }
+    }
 
     // 2. Check ADF4382 Lock Status
     bool tx_locked, rx_locked;
@@ -702,34 +702,34 @@ SystemError_t checkSystemHealth(void) {
 
     // 4. Check IMU Communication
     static uint32_t last_imu_check = 0;
-    if (HAL_GetTick() - last_imu_check > 10000) {
+    if (HAL_GetTick() - last_imu_check > 10000) {
-        if (!GY85_Update(&imu)) {
+        if (!GY85_Update(&imu)) {
-            current_error = ERROR_IMU_COMM;
+            current_error = ERROR_IMU_COMM;
-            DIAG_ERR("IMU", "Health check: GY85_Update() FAILED");
+            DIAG_ERR("IMU", "Health check: GY85_Update() FAILED");
-            return current_error;
+            return current_error;
-        }
+        }
-        last_imu_check = HAL_GetTick();
+        last_imu_check = HAL_GetTick();
-    }
+    }
 
     // 5. Check BMP180 Communication
     static uint32_t last_bmp_check = 0;
-    if (HAL_GetTick() - last_bmp_check > 15000) {
+    if (HAL_GetTick() - last_bmp_check > 15000) {
-        double pressure = myBMP.getPressure();
+        double pressure = myBMP.getPressure();
-        if (pressure < 30000.0 || pressure > 110000.0 || isnan(pressure)) {
+        if (pressure < 30000.0 || pressure > 110000.0 || isnan(pressure)) {
-            current_error = ERROR_BMP180_COMM;
+            current_error = ERROR_BMP180_COMM;
-            DIAG_ERR("SYS", "Health check: BMP180 pressure out of range: %.0f", pressure);
+            DIAG_ERR("SYS", "Health check: BMP180 pressure out of range: %.0f", pressure);
-            return current_error;
+            return current_error;
-        }
+        }
-        last_bmp_check = HAL_GetTick();
+        last_bmp_check = HAL_GetTick();
-    }
+    }
 
-    // 6. Check GPS Communication (30s grace period from boot / last valid fix)
+    // 6. Check GPS Communication (30s grace period from boot / last valid fix)
-    uint32_t gps_fix_age = um982_position_age(&um982);
+    uint32_t gps_fix_age = um982_position_age(&um982);
-    if (gps_fix_age > 30000) {
+    if (gps_fix_age > 30000) {
-        current_error = ERROR_GPS_COMM;
+        current_error = ERROR_GPS_COMM;
-        DIAG_WARN("SYS", "Health check: GPS no fix for >30s (age=%lu ms)", (unsigned long)gps_fix_age);
+        DIAG_WARN("SYS", "Health check: GPS no fix for >30s (age=%lu ms)", (unsigned long)gps_fix_age);
-        return current_error;
+        return current_error;
-    }
+    }
 
     // 7. Check RF Power Amplifier Current
     if (PowerAmplifier) {
@@ -760,7 +760,7 @@ SystemError_t checkSystemHealth(void) {
         DIAG_ERR("SYS", "checkSystemHealth returning error code %d", current_error);
     }
     return current_error;
-}
+}
 
 // Error recovery function
 void attemptErrorRecovery(SystemError_t error) {
@@ -905,22 +905,22 @@ void handleSystemError(SystemError_t error) {
         HAL_Delay(200);
     }
 
-    // Critical errors trigger emergency shutdown.
+    // Critical errors trigger emergency shutdown.
-    //
+    //
-    // Safety-critical range: any fault that can damage the PAs or leave the
+    // Safety-critical range: any fault that can damage the PAs or leave the
-    // system in an undefined state must cut the RF rails via Emergency_Stop().
+    // system in an undefined state must cut the RF rails via Emergency_Stop().
-    // This covers:
+    // This covers:
-    //   ERROR_RF_PA_OVERCURRENT .. ERROR_POWER_SUPPLY (9..13) -- PA/supply faults
+    //   ERROR_RF_PA_OVERCURRENT .. ERROR_POWER_SUPPLY (9..13) -- PA/supply faults
-    //   ERROR_TEMPERATURE_HIGH  (14) -- >75 C on the PA thermal sensors;
+    //   ERROR_TEMPERATURE_HIGH  (14) -- >75 C on the PA thermal sensors;
-    //                                  without cutting bias + 5V/5V5/RFPA rails
+    //                                  without cutting bias + 5V/5V5/RFPA rails
-    //                                  the GaN QPA2962 stage can thermal-runaway.
+    //                                  the GaN QPA2962 stage can thermal-runaway.
-    //   ERROR_WATCHDOG_TIMEOUT  (16) -- health-check loop has stalled (>60 s);
+    //   ERROR_WATCHDOG_TIMEOUT  (16) -- health-check loop has stalled (>60 s);
-    //                                  transmitter state is unknown, safest to
+    //                                  transmitter state is unknown, safest to
-    //                                  latch Emergency_Stop rather than rely on
+    //                                  latch Emergency_Stop rather than rely on
-    //                                  IWDG reset (which re-energises the rails).
+    //                                  IWDG reset (which re-energises the rails).
-    if ((error >= ERROR_RF_PA_OVERCURRENT && error <= ERROR_POWER_SUPPLY) ||
+    if ((error >= ERROR_RF_PA_OVERCURRENT && error <= ERROR_POWER_SUPPLY) ||
-        error == ERROR_TEMPERATURE_HIGH ||
+        error == ERROR_TEMPERATURE_HIGH ||
-        error == ERROR_WATCHDOG_TIMEOUT) {
+        error == ERROR_WATCHDOG_TIMEOUT) {
         DIAG_ERR("SYS", "CRITICAL ERROR (code %d: %s) -- initiating Emergency_Stop()", error, err_name);
         snprintf(error_msg, sizeof(error_msg),
                  "CRITICAL ERROR! Initiating emergency shutdown.\r\n");
@@ -1483,8 +1483,8 @@ int main(void)
   HAL_GPIO_WritePin(EN_P_3V3_FPGA_GPIO_Port,EN_P_3V3_FPGA_Pin,GPIO_PIN_SET);
   HAL_Delay(100);
   DIAG("PWR", "FPGA power sequencing complete -- 1.0V -> 1.8V -> 3.3V");
-
+
-
+
 // Initialize module IMU
   DIAG_SECTION("IMU INIT (GY-85)");
   DIAG("IMU", "Initializing GY-85 IMU...");
@@ -1493,12 +1493,12 @@ int main(void)
       Error_Handler();
   }
   DIAG("IMU", "GY-85 initialized OK, running 10 calibration samples");
-  for(int i=0; i<10;i++){
+  for(int i=0; i<10;i++){
-  if (!GY85_Update(&imu)) {
+  if (!GY85_Update(&imu)) {
-      Error_Handler();
+      Error_Handler();
-  }
+  }
-
+
-  ax = imu.ax;
+  ax = imu.ax;
   ay = imu.ay;
   az = imu.az;
   gx = -imu.gx;
@@ -1793,20 +1793,20 @@ int main(void)
           HAL_Delay(10);
       }
   }
-  RADAR_Longitude = um982_get_longitude(&um982);
+  RADAR_Longitude = um982_get_longitude(&um982);
-  RADAR_Latitude = um982_get_latitude(&um982);
+  RADAR_Latitude = um982_get_latitude(&um982);
-  DIAG("GPS", "Initial position: lat=%.6f lon=%.6f fix=%d sats=%d",
+  DIAG("GPS", "Initial position: lat=%.6f lon=%.6f fix=%d sats=%d",
-       RADAR_Latitude, RADAR_Longitude,
+       RADAR_Latitude, RADAR_Longitude,
-       um982_get_fix_quality(&um982), um982_get_num_sats(&um982));
+       um982_get_fix_quality(&um982), um982_get_num_sats(&um982));
-
+
-  // Re-apply heading after GPS init so the north-alignment stepper move uses
+  // Re-apply heading after GPS init so the north-alignment stepper move uses
-  // UM982 dual-antenna heading when available.
+  // UM982 dual-antenna heading when available.
-  if (um982_is_heading_valid(&um982)) {
+  if (um982_is_heading_valid(&um982)) {
-      Yaw_Sensor = um982_get_heading(&um982);
+      Yaw_Sensor = um982_get_heading(&um982);
-  }
+  }
-
+
-  //move Stepper to position 1 = 0°
+  //move Stepper to position 1 = 0°
-  HAL_GPIO_WritePin(STEPPER_CW_P_GPIO_Port, STEPPER_CW_P_Pin, GPIO_PIN_RESET);//Set stepper motor spinning direction to CCW
+  HAL_GPIO_WritePin(STEPPER_CW_P_GPIO_Port, STEPPER_CW_P_Pin, GPIO_PIN_RESET);//Set stepper motor spinning direction to CCW
   //Point Stepper to North
   for(int i= 0;i<(int)(Yaw_Sensor*Stepper_steps/360);i++){
 	  HAL_GPIO_WritePin(STEPPER_CLK_P_GPIO_Port, STEPPER_CLK_P_Pin, GPIO_PIN_SET);
@@ -1819,14 +1819,14 @@ int main(void)
   /**********wait for GUI start flag and Send Lat/Long/alt********/
   /***************************************************************/
 
-  GPS_Data_t gps_data;
+  GPS_Data_t gps_data;
-  // Binary packet structure:
+  // Binary packet structure:
-  // [Header 4 bytes][Latitude 8 bytes][Longitude 8 bytes][Altitude 4 bytes][Pitch 4 bytes][CRC 2 bytes]
+  // [Header 4 bytes][Latitude 8 bytes][Longitude 8 bytes][Altitude 4 bytes][Pitch 4 bytes][CRC 2 bytes]
-  gps_data = {RADAR_Latitude, RADAR_Longitude, RADAR_Altitude, Pitch_Sensor, HAL_GetTick()};
+  gps_data = {RADAR_Latitude, RADAR_Longitude, RADAR_Altitude, Pitch_Sensor, HAL_GetTick()};
-  if (!GPS_SendBinaryToGUI(&gps_data)) {
+  if (!GPS_SendBinaryToGUI(&gps_data)) {
-      const uint8_t gps_send_error[] = "GPS binary send failed\r\n";
+      const uint8_t gps_send_error[] = "GPS binary send failed\r\n";
-      HAL_UART_Transmit(&huart3, (uint8_t*)gps_send_error, sizeof(gps_send_error) - 1, 1000);
+      HAL_UART_Transmit(&huart3, (uint8_t*)gps_send_error, sizeof(gps_send_error) - 1, 1000);
-  }
+  }
 
   /* [STM32-006 FIXED] Removed blocking do-while loop that waited for
    * usbHandler.isStartFlagReceived().  The production V7 PyQt GUI does not

9_Firmware/9_1_Microcontroller/tests/stm32_hal_mock.c

@@ -406,3 +406,11 @@ static int mock_spi_init_stub(void) { return 0; }
 const struct no_os_spi_platform_ops stm32_spi_ops = {
     .init = mock_spi_init_stub,
 };
+
+/* ========================= CMSIS-Core stub storage ======================= */
+/* See stm32_hal_mock.h for rationale. SystemCoreClock = 0 forces delayUs() to
+ * return immediately under host test builds. DWT->CTRL pre-enabled so the
+ * one-time-init branch is skipped deterministically. */
+struct _DWT_Mock_Type       _dwt_mock       = { .CTRL = DWT_CTRL_CYCCNTENA_Msk, .CYCCNT = 0 };
+struct _CoreDebug_Mock_Type _coredebug_mock = { .DEMCR = 0 };
+uint32_t                    SystemCoreClock = 0U;

9_Firmware/9_1_Microcontroller/tests/stm32_hal_mock.h

@@ -242,6 +242,26 @@ uint8_t ADS7830_Measure_SingleEnded(ADC_HandleTypeDef *hadc, uint8_t channel);
  * if desired via a global flag. */
 extern int mock_printf_enabled;
 
+/* ========================= CMSIS-Core stubs ======================= */
+/* Minimum surface to let F-4.7's DWT-based delayUs() in ADAR1000_Manager.cpp
+ * compile under the host mock build. SystemCoreClock is intentionally 0 so
+ * target = microseconds * (SystemCoreClock / 1000000) is also 0, making the
+ * busy-wait loop exit immediately regardless of argument. Pre-setting
+ * DWT->CTRL with CYCCNTENA also skips the one-time init branch.            */
+
+#define DWT_CTRL_CYCCNTENA_Msk     (1UL << 0)
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << 24)
+
+struct _DWT_Mock_Type       { uint32_t CTRL; uint32_t CYCCNT; };
+struct _CoreDebug_Mock_Type { uint32_t DEMCR; };
+
+extern struct _DWT_Mock_Type       _dwt_mock;
+extern struct _CoreDebug_Mock_Type _coredebug_mock;
+extern uint32_t                    SystemCoreClock;
+
+#define DWT       (&_dwt_mock)
+#define CoreDebug (&_coredebug_mock)
+
 #ifdef __cplusplus
 }
 #endif

9_Firmware/9_2_FPGA/ad9484_interface_400m.v

@@ -4,15 +4,23 @@ module ad9484_interface_400m (
     input wire [7:0] adc_d_n,        // ADC Data N
     input wire adc_dco_p,            // Data Clock Output P (400MHz)
     input wire adc_dco_n,            // Data Clock Output N (400MHz)
-    
+    // Audit F-0.1: AD9484 OR (overrange) LVDS pair, DDR like data.
+    // Routed on the 50T main board to bank 14 pins M6/N6. Asserts for any
+    // sample whose absolute value exceeds full-scale.
+    input wire adc_or_p,
+    input wire adc_or_n,
+
     // System Interface
     input wire sys_clk,              // 100MHz system clock (for control only)
     input wire reset_n,
-    
+
     // Output at 400MHz domain
     output wire [7:0] adc_data_400m, // ADC data at 400MHz
     output wire adc_data_valid_400m, // Valid at 400MHz
-    output wire adc_dco_bufg         // Buffered 400MHz DCO clock for downstream use
+    output wire adc_dco_bufg,        // Buffered 400MHz DCO clock for downstream use
+    // Audit F-0.1: OR flag, clk_400m domain. High on any sample in the
+    // current 400 MHz cycle where the ADC reports overrange.
+    output wire adc_overrange_400m
 );
 
 // LVDS to single-ended conversion
@@ -166,4 +174,54 @@ end
 assign adc_data_400m = adc_data_400m_reg;
 assign adc_data_valid_400m = adc_data_valid_400m_reg;
 
+// ============================================================================
+// Audit F-0.1: AD9484 OR (overrange) capture
+// OR is a DDR LVDS pair (same as data). Buffer it, capture both edges with an
+// IDDR in the BUFIO domain, then OR the two phases into a single clk_400m
+// flag. Register once for stability. No latching — downstream is expected to
+// stickify in its own domain.
+// ============================================================================
+wire adc_or_raw;
+IBUFDS #(
+    .DIFF_TERM("FALSE"),
+    .IOSTANDARD("DEFAULT")
+) ibufds_or (
+    .O(adc_or_raw),
+    .I(adc_or_p),
+    .IB(adc_or_n)
+);
+
+wire adc_or_rise;
+wire adc_or_fall;
+IDDR #(
+    .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
+    .INIT_Q1(1'b0),
+    .INIT_Q2(1'b0),
+    .SRTYPE("SYNC")
+) iddr_or (
+    .Q1(adc_or_rise),
+    .Q2(adc_or_fall),
+    .C(adc_dco_bufio),
+    .CE(1'b1),
+    .D(adc_or_raw),
+    .R(1'b0),
+    .S(1'b0)
+);
+
+reg adc_or_rise_bufg;
+reg adc_or_fall_bufg;
+always @(posedge adc_dco_buffered) begin
+    adc_or_rise_bufg <= adc_or_rise;
+    adc_or_fall_bufg <= adc_or_fall;
+end
+
+reg adc_overrange_r;
+always @(posedge adc_dco_buffered or negedge reset_n_400m) begin
+    if (!reset_n_400m)
+        adc_overrange_r <= 1'b0;
+    else
+        adc_overrange_r <= adc_or_rise_bufg | adc_or_fall_bufg;
+end
+assign adc_overrange_400m = adc_overrange_r;
+
 endmodule

9_Firmware/9_2_FPGA/cdc_modules.v

@@ -17,7 +17,12 @@ module cdc_adc_to_processing #(
     input wire [WIDTH-1:0] src_data,
     input wire src_valid,
     output wire [WIDTH-1:0] dst_data,
-    output wire dst_valid
+    output wire dst_valid,
+    // Audit F-1.2: overrun pulse in src_clk domain. Asserts for 1 src cycle
+    // whenever src_valid fires while the previous sample has not yet been
+    // acknowledged by the destination edge-detector (i.e., the transaction
+    // the CDC is silently dropping). Hold/count externally.
+    output wire overrun
 `ifdef FORMAL
     ,output wire [WIDTH-1:0] fv_src_data_reg,
     output wire [1:0]       fv_src_toggle
@@ -130,6 +135,36 @@ module cdc_adc_to_processing #(
     assign dst_data = dst_data_reg;
     assign dst_valid = dst_valid_reg;
 
+    // ------------------------------------------------------------------
+    // Audit F-1.2: overrun detection
+    //
+    // The src-side `src_toggle` counter flips on each latched src_valid.
+    // We feed back a 1-bit "ack" toggle from the dst domain (flipped each
+    // time dst_valid fires) through a STAGES-deep synchronizer into the
+    // src domain. If a new src_valid arrives while src_toggle[0] already
+    // differs from the acked value, the previous sample is still in flight
+    // and this new latch drops it. Emit a 1-cycle overrun pulse.
+    // ------------------------------------------------------------------
+    reg dst_ack_toggle;
+    always @(posedge dst_clk) begin
+        if (!dst_reset_n)      dst_ack_toggle <= 1'b0;
+        else if (dst_valid_reg) dst_ack_toggle <= ~dst_ack_toggle;
+    end
+
+    (* ASYNC_REG = "TRUE" *) reg [STAGES-1:0] ack_sync_chain;
+    always @(posedge src_clk) begin
+        if (!src_reset_n) ack_sync_chain <= {STAGES{1'b0}};
+        else              ack_sync_chain <= {ack_sync_chain[STAGES-2:0], dst_ack_toggle};
+    end
+    wire ack_in_src = ack_sync_chain[STAGES-1];
+
+    reg overrun_r;
+    always @(posedge src_clk) begin
+        if (!src_reset_n) overrun_r <= 1'b0;
+        else              overrun_r <= src_valid && (src_toggle[0] != ack_in_src);
+    end
+    assign overrun = overrun_r;
+
 `ifdef FORMAL
     assign fv_src_data_reg = src_data_reg;
     assign fv_src_toggle   = src_toggle;

9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v

@@ -32,11 +32,50 @@ localparam COMB_WIDTH = 28;
 // adjacent DSP48E1 tiles — zero fabric delay, guaranteed to meet 400+ MHz
 // on 7-series regardless of speed grade.
 //
-// Active-high reset derived from reset_n (inverted).
+// Active-high reset derived from reset_n (inverted and REGISTERED).
 // CEP (clock enable for P register) gated by data_valid.
-// ============================================================================
+//
-
+// ----------------------------------------------------------------------------
-wire reset_h = ~reset_n;  // active-high reset for DSP48E1 RSTP
+// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
+// ----------------------------------------------------------------------------
+// Previously this was a combinational wire (`wire reset_h = ~reset_n`). Vivado
+// collapsed all per-module inversions across the DDC hierarchy into a SINGLE
+// shared LUT1, whose output fanned out to 702 loads (DSP48E1 RSTP/RSTB/RSTC
+// plus FDRE R pins of all comb-stage DSP48E1s inferred via use_dsp="yes").
+// Route delay alone on that net was 2.019–2.268 ns — nearly one full 2.5 ns
+// period. Timing failed by 626 ps on the 400 MHz domain.
+//
+// Fix: convert reset_h to a REGISTERED signal with (* max_fanout = 50 *).
+// Vivado treats max_fanout on a REG (not a wire) as authoritative and
+// replicates the register into N copies, each placed near its ≈50 loads.
+// Invariants preserved:
+//   I1 (correctness):       reset_h is still active-high, equals ~reset_n
+//                           after one clk edge; CIC reset is a RECEIVER-side
+//                           synchronizer anyway (driven by reset_n_400m which
+//                           is already sync'd in the parent DDC), so adding
+//                           one more clk cycle of latency is safe.
+//   I2 (glitch-free):       Registered output => inherently glitch-free,
+//                           feeding DSP48E1 RST pins (which are synchronous
+//                           to CLK, so they capture on the same edge anyway).
+//   I3 (power-up safety):   reset_h is NOT async-reset itself. On power-up,
+//                           FDRE INIT=0 starts reset_h LOW. First clk edge
+//                           samples ~reset_n which is LOW on power-up (the
+//                           parent DDC holds reset_n_400m low until the 2-
+//                           stage synchronizer releases), so reset_h goes
+//                           HIGH on cycle 1 and all DSPs see reset during
+//                           the following cycles. System is held in reset
+//                           for enough cycles that any initial register
+//                           state garbage is overwritten. ✅
+//   I4 (reset de-assertion):reset_h goes LOW one cycle AFTER reset_n_400m
+//                           goes HIGH. Downstream DSPs come out of reset on
+//                           the next clk edge after that. Total latency
+//                           from system reset release to first valid sample:
+//                           2 (sync chain) + 1 (reset_h reg) + 1 (first
+//                           DSP output) = 4 cycles at 400 MHz = 10 ns.
+//                           Negligible vs system reset assertion duration.
+// ----------------------------------------------------------------------------
+(* max_fanout = 25 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
+always @(posedge clk) reset_h <= ~reset_n;
 
 // Sign-extended input for integrator_0 C port (48-bit)
 wire [ACC_WIDTH-1:0] data_in_c = {{(ACC_WIDTH-18){data_in[17]}}, data_in};
@@ -699,10 +738,11 @@ initial begin
 end
 
 // Decimation control + monitoring (integrators are now DSP48E1 instances)
-// Sync reset: enables FDRE inference for better timing at 400 MHz.
+// Sync reset via reset_h (registered, max_fanout=50) — eliminates the shared
-// Reset is already synchronous to clk via reset synchronizer in parent module.
+// LUT1 inverter that previously fanned out to all fabric FDRE R pins plus
+// DSP48E1 RST pins (702 loads total). See "RESET FAN-OUT INVARIANT" at top.
 always @(posedge clk) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         integrator_sampled <= 0;
         decimation_counter <= 0;
         data_valid_delayed <= 0;
@@ -755,9 +795,9 @@ always @(posedge clk) begin
 end
 
 // Pipeline the valid signal for comb section
-// Sync reset: matches decimation control block reset style.
+// Sync reset via reset_h — same replicated-register source as DSP48E1 RSTs.
 always @(posedge clk) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         data_valid_comb <= 0;
         data_valid_comb_pipe <= 0;
         data_valid_comb_0_out <= 0;
@@ -792,7 +832,7 @@ end
 //   - Each stage: comb[i] = comb[i-1] - comb_delay[i][last]
 
 always @(posedge clk) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         for (i = 0; i < STAGES; i = i + 1) begin
             comb[i] <= 0;
             for (j = 0; j < COMB_DELAY; j = j + 1) begin

9_Firmware/9_2_FPGA/constraints/README.md

@@ -32,8 +32,8 @@ the `USB_MODE` parameter in `radar_system_top.v`:
 
 | USB_MODE | Interface | Bus Width | Speed | Board Target |
 |----------|-----------|-----------|-------|--------------|
-| 0 (default) | FT601 (USB 3.0) | 32-bit | 100 MHz | 200T premium dev board |
+| 0 | FT601 (USB 3.0) | 32-bit | 100 MHz | 200T premium dev board |
-| 1 | FT2232H (USB 2.0) | 8-bit | 60 MHz | 50T production board |
+| 1 (default) | FT2232H (USB 2.0) | 8-bit | 60 MHz | 50T production board |
 
 ### How USB_MODE Works
 
@@ -72,7 +72,8 @@ The parameter is set via a **wrapper module** that overrides the default:
   ```
 
 - **200T dev board**: `radar_system_top` is used directly as the top module.
-  `USB_MODE` defaults to `0` (FT601). No wrapper needed.
+  `USB_MODE` defaults to `1` (FT2232H) since production is the primary target.
+  Override with `.USB_MODE(0)` for FT601 builds.
 
 ### RTL Files by USB Interface
 
@@ -158,7 +159,7 @@ The build scripts automatically select the correct top module and constraints:
 
 You do NOT need to set `USB_MODE` manually. The top module selection handles it:
 - `radar_system_top_50t` forces `USB_MODE=1` internally
-- `radar_system_top` defaults to `USB_MODE=0`
+- `radar_system_top` defaults to `USB_MODE=1` (FT2232H, production default)
 
 ## How to Select Constraints in Vivado
 
@@ -190,9 +191,9 @@ read_xdc constraints/te0713_te0701_minimal.xdc
 | Target | Top module | USB_MODE | USB Interface | Notes |
 |--------|------------|----------|---------------|-------|
 | 50T Production (FTG256) | `radar_system_top_50t` | 1 | FT2232H (8-bit) | Wrapper sets USB_MODE=1, ties off FT601 |
-| 200T Dev (FBG484) | `radar_system_top` | 0 (default) | FT601 (32-bit) | No wrapper needed |
+| 200T Dev (FBG484) | `radar_system_top` | 0 (override) | FT601 (32-bit) | Build script overrides default USB_MODE=1 |
-| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | 0 (default) | FT601 (32-bit) | Minimal bring-up wrapper |
+| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | 0 (override) | FT601 (32-bit) | Minimal bring-up wrapper |
-| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | 0 (default) | FT601 (32-bit) | Alternate SoM wrapper |
+| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | 0 (override) | FT601 (32-bit) | Alternate SoM wrapper |
 
 ## Trenz Split Status
 

9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc

@@ -33,10 +33,10 @@
 # (one period) to ensure the tools verify the transfer fits within one cycle
 # without over-constraining with full inter-clock setup/hold analysis.
 set_max_delay -datapath_only -from [get_clocks adc_dco_p] \
-    -to [get_clocks clk_mmcm_out0] 2.500
+    -to [get_clocks clk_mmcm_out0] 2.700
 
 set_max_delay -datapath_only -from [get_clocks clk_mmcm_out0] \
-    -to [get_clocks adc_dco_p] 2.500
+    -to [get_clocks adc_dco_p] 2.700
 
 # --------------------------------------------------------------------------
 # CDC: MMCM output domain ↔ other clock domains
@@ -47,8 +47,12 @@ set_max_delay -datapath_only -from [get_clocks clk_mmcm_out0] \
 set_false_path -from [get_clocks clk_100m] -to [get_clocks clk_mmcm_out0]
 set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks clk_100m]
 
-set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft601_clk_in]
+# Audit F-0.6: the USB-domain clock name differs per board
-set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_mmcm_out0]
+# (50T: ft_clkout, 200T: ft601_clk_in). XDC files only support a
+# restricted Tcl subset — `foreach`/`unset` trigger CRITICAL WARNING
+# [Designutils 20-1307]. The clk_mmcm_out0 ↔ USB-clock false paths
+# are declared in the per-board XDC (xc7a50t_ftg256.xdc and
+# xc7a200t_fbg484.xdc) where the USB clock name is already known.
 
 set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks clk_120m_dac]
 set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_mmcm_out0]
@@ -59,7 +63,10 @@ set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_mmcm_out0]
 # LOCKED is not a valid timing startpoint (it's a combinational output of the
 # MMCM primitive). Use -through instead of -from to waive all paths that pass
 # through the LOCKED net. This avoids the CRITICAL WARNING from Build 19/20.
-set_false_path -through [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED]
+# Audit F-0.7: the literal hierarchical path was missing the `u_core/`
+# prefix and silently matched no pins. Use a hierarchical wildcard to
+# catch the MMCM LOCKED pin regardless of wrapper hierarchy.
+set_false_path -through [get_pins -hierarchical -filter {REF_PIN_NAME == LOCKED}]
 
 # --------------------------------------------------------------------------
 # Hold waiver for source-synchronous ADC capture (BUFIO-clocked IDDR)
@@ -82,14 +89,19 @@ set_false_path -through [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED]
 #
 # Waiving hold on these 8 paths (adc_d_p[0..7] → IDDR) is standard practice
 # for source-synchronous LVDS ADC interfaces using BUFIO capture.
-set_false_path -hold -from [get_ports {adc_d_p[*]}] -to [get_clocks adc_dco_p]
+# adc_or_p (AD9484 overrange, audit F-0.1) shares the same IBUFDS→BUFIO
+# source-synchronous capture topology as adc_d_p[*] — same ~1.9 ns STA hold
+# violation for the same reason (BUFIO clock insertion ~4 ns vs data IBUFDS
+# ~0.9 ns), resolved by the same external-timing argument.
+set_false_path -hold -from [get_ports {adc_d_p[*] adc_or_p}] -to [get_clocks adc_dco_p]
 
 # --------------------------------------------------------------------------
 # Timing margin for 400 MHz critical paths
 # --------------------------------------------------------------------------
 # Extra setup uncertainty forces Vivado to leave margin for temperature/voltage/
-# aging variation. Reduced from 200 ps to 100 ps after NCO→mixer pipeline
+# aging variation. 150 ps absolute covers the built-in jitter-based value
-# register fix eliminated the dominant timing bottleneck (WNS went from +0.002ns
+# (~53 ps) plus ~100 ps temperature/voltage/aging guardband.
-# to comfortable margin). 100 ps still provides ~4% guardband on the 2.5ns period.
+# NOTE: Vivado's set_clock_uncertainty does NOT accept -add; prior use of
-# This is additive to the existing jitter-based uncertainty (~53 ps).
+# -add 0.100 was silently rejected as a CRITICAL WARNING, so no guardband
-set_clock_uncertainty -setup -add 0.100 [get_clocks clk_mmcm_out0]
+# was applied. Use an absolute value. (audit finding F-0.8)
+set_clock_uncertainty -setup 0.150 [get_clocks clk_mmcm_out0]

9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc

@@ -134,6 +134,22 @@ set_property IOSTANDARD LVDS_25 [get_ports {adc_d_p[*]}]
 set_property IOSTANDARD LVDS_25 [get_ports {adc_d_n[*]}]
 set_property DIFF_TERM TRUE [get_ports {adc_d_p[*]}]
 
+# --------------------------------------------------------------------------
+# Audit F-0.1: AD9484 OR (overrange) LVDS pair
+# The 50T main board schematic routes ADC_OR_P/N to bank-14 pins M6/N6 on
+# xc7a50t-ftg256. The 200T dev-board schematic has NOT been checked yet;
+# adc_or_p/n are declared as top-level ports so the 50T build anchors them
+# cleanly, but the 200T anchor below is a TODO placeholder — synth/impl will
+# error on unplaced IO until the 200T schematic is verified and the PACKAGE_PIN
+# values are set. IOSTANDARD/DIFF_TERM properties stay as-is (same class as
+# adc_d_p).
+# --------------------------------------------------------------------------
+set_property IOSTANDARD LVDS_25 [get_ports {adc_or_p}]
+set_property IOSTANDARD LVDS_25 [get_ports {adc_or_n}]
+set_property DIFF_TERM TRUE [get_ports {adc_or_p}]
+# TODO(F-0.1): set_property PACKAGE_PIN <?> [get_ports {adc_or_p}] after 200T schematic audit
+# TODO(F-0.1): set_property PACKAGE_PIN <?> [get_ports {adc_or_n}] after 200T schematic audit
+
 # ADC Power Down — single-ended, Bank 14 (LVCMOS25 matches bank VCCO)
 # Pin: P20 = IO_0_14
 set_property PACKAGE_PIN P20 [get_ports {adc_pwdn}]
@@ -621,6 +637,10 @@ set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_120m_dac]
 set_false_path -from [get_clocks adc_dco_p] -to [get_clocks ft601_clk_in]
 set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks adc_dco_p]
 
+# MMCM 400 MHz domain ↔ FT601 USB clock (see adc_clk_mmcm.xdc for rationale)
+set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft601_clk_in]
+set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_mmcm_out0]
+
 # Generated clock cross-domain paths:
 # dac_clk_fwd and ft601_clk_fwd are generated from their respective source
 # clocks. Vivado automatically inherits the source clock false paths for

9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc

@@ -70,9 +70,10 @@ set_input_jitter [get_clocks clk_100m] 0.1
 # NOTE: The physical DAC (U3, AD9708) receives its clock directly from the
 #       AD9523 via a separate net (DAC_CLOCK), NOT from the FPGA. The FPGA
 #       uses this clock input for internal DAC data timing only. The RTL port
-#       `dac_clk` is an output that assigns clk_120m directly — it has no
+#       `dac_clk` is an RTL output that assigns clk_120m directly. It has no
-#       separate physical pin on this board and should be removed from the
+#       physical pin on the 50T board and is left unconnected here. The port
-#       RTL or left unconnected.
+#       CANNOT be removed from the RTL because the 200T board uses it with
+#       ODDR clock forwarding (pin H17, see xc7a200t_fbg484.xdc).
 # FIX: Moved from C13 (IO_L12N = N-type) to D13 (IO_L12P = P-type MRCC).
 #      Clock inputs must use the P-type pin of an MRCC pair (PLIO-9 DRC).
 set_property PACKAGE_PIN D13 [get_ports {clk_120m_dac}]
@@ -106,8 +107,15 @@ set_property PACKAGE_PIN C4 [get_ports {ft_clkout}]
 set_property IOSTANDARD LVCMOS33 [get_ports {ft_clkout}]
 create_clock -name ft_clkout -period 16.667 [get_ports {ft_clkout}]
 set_input_jitter [get_clocks ft_clkout] 0.2
-# N-type MRCC pin requires dedicated route override (Place 30-876)
+# N-type MRCC pin requires dedicated route override (Place 30-876).
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {ft_clkout_IBUF}]
+# Audit F-0.4: the literal net name `ft_clkout_IBUF` exists post-synth but
+# the XDC scan happens before synthesis, when the IBUF net does not yet
+# exist — Vivado reported `No nets matched 'ft_clkout_IBUF'` + CRITICAL
+# WARNING. Use -hierarchical -filter + -quiet so the constraint matches
+# post-synth without warning during pre-synth XDC scan. The TCL duplicate
+# at scripts/50t/build_50t.tcl:119 remains as belt-and-suspenders.
+set_property -quiet CLOCK_DEDICATED_ROUTE FALSE \
+    [get_nets -quiet -hierarchical -filter {NAME =~ *ft_clkout_IBUF}]
 
 # ============================================================================
 # RESET (Active-Low)
@@ -282,6 +290,22 @@ set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_d_p[*]}]
 set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
 set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
 
+# --------------------------------------------------------------------------
+# Audit F-0.1: AD9484 OR (overrange) LVDS pair (Bank 14)
+# Schematic RADAR_Main_Board.sch: ADC_OR_P → U42 IO_L19P_T3_A10_D26_14 (M6)
+#                                  ADC_OR_N → U42 IO_L19N_T3_A09_D25_VREF_14 (N6)
+# DDR-sourced by adc_dco_p, same timing class as adc_d_p[*].
+# --------------------------------------------------------------------------
+set_property PACKAGE_PIN M6 [get_ports {adc_or_p}]
+set_property PACKAGE_PIN N6 [get_ports {adc_or_n}]
+set_property IOSTANDARD LVDS_25 [get_ports {adc_or_p}]
+set_property IOSTANDARD LVDS_25 [get_ports {adc_or_n}]
+set_property DIFF_TERM TRUE [get_ports {adc_or_p}]
+set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 [get_ports {adc_or_p}]
+set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_or_p}]
+set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_or_p}] -add_delay
+set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_or_p}] -add_delay
+
 # ============================================================================
 # FT2232H USB 2.0 INTERFACE (Bank 35, VCCO=3.3V)
 # ============================================================================
@@ -332,6 +356,50 @@ set_property DRIVE 8 [get_ports {ft_data[*]}]
 
 # ft_clkout constrained above in CLOCK CONSTRAINTS section (C4, 60 MHz)
 
+# --------------------------------------------------------------------------
+# FT2232H Source-Synchronous Timing Constraints
+# --------------------------------------------------------------------------
+# FT2232H 245 Synchronous FIFO mode timing (60 MHz, period = 16.667 ns).
+# Values per FTDI TN_167 "FT2232H Synchronous FIFO Bus Bridge" — verify
+# against the exact app-note revision before shipping.
+#
+# FPGA Read Path (FT2232H drives data/RXF#/TXE#, FPGA samples on CLKOUT↑):
+#   - t_co  (CLKOUT↑ → data valid)   max = 10.0 ns
+#   - t_coh (CLKOUT↑ → data hold)    min = 0.5 ns
+#   - set_input_delay -max = t_co,  -min = t_coh
+#
+# FPGA Write Path (FPGA drives data/WR#/RD#/OE#, FT2232H samples on CLKOUT↑):
+#   - t_su  (data setup before CLKOUT↑)  min = 3.5 ns  (NOT 5 ns — prior
+#           constraint used a synthetic period-based back-calculation)
+#   - t_h   (data hold after CLKOUT↑)    min = 1.0 ns  (NOT 0 — a 0 ns hold
+#           constraint produced no hold check at all)
+#   - set_output_delay -max = t_su, -min = -t_h (Vivado convention)
+#
+# Audit F-2026-04-20 Option B: the previous output_delay = 11.667 ns
+# (= period − 5) over-constrained launch by ~8 ns vs the actual datasheet
+# figure. Relaxing to 3.5 ns matches the chip's real setup requirement.
+# --------------------------------------------------------------------------
+
+# Input delays: FT2232H → FPGA (data bus and status signals)
+set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_data[*]}]
+set_input_delay -clock [get_clocks ft_clkout] -min 0.5  [get_ports {ft_data[*]}]
+set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_rxf_n}]
+set_input_delay -clock [get_clocks ft_clkout] -min 0.5  [get_ports {ft_rxf_n}]
+set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_txe_n}]
+set_input_delay -clock [get_clocks ft_clkout] -min 0.5  [get_ports {ft_txe_n}]
+
+# Output delays: FPGA → FT2232H (control strobes and data bus when writing)
+set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_data[*]}]
+set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_data[*]}]
+set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_rd_n}]
+set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_rd_n}]
+set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_wr_n}]
+set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_wr_n}]
+set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_oe_n}]
+set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_oe_n}]
+set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_siwu}]
+set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_siwu}]
+
 # ============================================================================
 # STATUS / DEBUG OUTPUTS — NO PHYSICAL CONNECTIONS
 # ============================================================================
@@ -369,7 +437,17 @@ set_false_path -from [get_ports {stm32_mixers_enable}]
 #   - Reset deassertion order is not functionally critical — all registers
 #     come out of reset within a few cycles of each other
 # --------------------------------------------------------------------------
-set_false_path -from [get_cells reset_sync_reg[*]] -to [get_pins -filter {REF_PIN_NAME == CLR} -of_objects [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ REGISTER.*.*}]]
+# Audit F-0.5: the literal cell name `reset_sync_reg[*]` does not match any
+# cell in the post-synth netlist. The actual sync regs are
+# `u_core/reset_sync_reg[0..1]`, `u_core/rx_inst/ddc/reset_sync_400m_reg[*]`,
+# `u_core/gen_ft2232h.usb_inst/ft_reset_sync_reg[*]`, and peers under
+# `u_core/reset_sync_120m_reg[*]`, `u_core/reset_sync_ft601_reg[*]`,
+# `u_core/rx_inst/adc/reset_sync_400m_reg[*]`. The waiver below covers all
+# of them by matching any register whose name contains `reset_sync`.
+# Without this, STA runs recovery/removal on the fanout of each sync-chain
+# output register (up to ~1000 loads pre-PR#113 replication).
+set_false_path -from [get_cells -hierarchical -filter {NAME =~ *reset_sync*_reg*}] \
+               -to   [get_pins  -hierarchical -filter {REF_PIN_NAME == CLR || REF_PIN_NAME == PRE}]
 
 # --------------------------------------------------------------------------
 # Clock Domain Crossing false paths
@@ -391,6 +469,10 @@ set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_100m]
 set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks ft_clkout]
 set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_120m_dac]
 
+# MMCM 400 MHz domain ↔ FT2232H USB clock (see adc_clk_mmcm.xdc for rationale)
+set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft_clkout]
+set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_mmcm_out0]
+
 # ============================================================================
 # PHYSICAL CONSTRAINTS
 # ============================================================================
@@ -418,10 +500,10 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
 # 4. JTAG: FPGA_TCK (L7), FPGA_TDI (N7), FPGA_TDO (N8), FPGA_TMS (M7).
 #    Dedicated pins — no XDC constraints needed.
 #
-# 5. dac_clk port: The RTL top module declares `dac_clk` as an output, but
+# 5. dac_clk port: Not connected on the 50T board (DAC clocked directly from
-#    the physical board wires the DAC clock (AD9708 CLOCK pin) directly from
+#    AD9523). The RTL port exists for 200T board compatibility, where the FPGA
-#    the AD9523, not from the FPGA. This port should be removed from the RTL
+#    forwards the DAC clock via ODDR to pin H17 with generated clock and
-#    or left unconnected. It currently just assigns clk_120m_dac passthrough.
+#    timing constraints (see xc7a200t_fbg484.xdc). Do NOT remove from RTL.
 #
 # ============================================================================
 # END OF CONSTRAINTS

9_Firmware/9_2_FPGA/ddc_400m.v

@@ -1,106 +1,69 @@
-`timescale 1ns / 1ps
+`timescale 1ns / 1ps
-
+
-module ddc_400m_enhanced (
+module ddc_400m_enhanced (
-    input wire clk_400m,           // 400MHz clock from ADC DCO
+    input wire clk_400m,           // 400MHz clock from ADC DCO
-    input wire clk_100m,           // 100MHz system clock
+    input wire clk_100m,           // 100MHz system clock
-    input wire reset_n,
+    input wire reset_n,
-    input wire mixers_enable,
+    input wire mixers_enable,
-    input wire [7:0] adc_data,     // ADC data at 400MHz
+    input wire [7:0] adc_data,     // ADC data at 400MHz
     input wire adc_data_valid_i,     // Valid at 400MHz
-	 input wire adc_data_valid_q,
+	 input wire adc_data_valid_q,
-    output wire signed [17:0] baseband_i,
+    output wire signed [17:0] baseband_i,
-    output wire signed [17:0] baseband_q,  
+    output wire signed [17:0] baseband_q,  
     output wire baseband_valid_i,
-	 output wire baseband_valid_q,
+	 output wire baseband_valid_q,
-
+
-    output wire [1:0] ddc_status,
+    output wire [1:0] ddc_status,
-    // Enhanced interfaces
+    // Enhanced interfaces
-    output wire [7:0] ddc_diagnostics,
+    output wire [7:0] ddc_diagnostics,
     output wire mixer_saturation,
     output wire filter_overflow,
 	 
-	 input wire [1:0] test_mode,
+	 input wire [1:0] test_mode,
-    input wire [15:0] test_phase_inc,
+    input wire [15:0] test_phase_inc,
-    input wire force_saturation,
+    input wire force_saturation,
-    input wire reset_monitors,
+    input wire reset_monitors,
-    output wire [31:0] debug_sample_count,
+    output wire [31:0] debug_sample_count,
-    output wire [17:0] debug_internal_i,
+    output wire [17:0] debug_internal_i,
-    output wire [17:0] debug_internal_q
+    output wire [17:0] debug_internal_q,
-);
+    // Audit F-1.2: sticky CIC→FIR CDC overrun flag (clk_400m domain). Goes
-
+    // high on the first dropped sample and stays high until reset_monitors.
-// Parameters for numerical precision
+    output wire cdc_cic_fir_overrun
-parameter ADC_WIDTH = 8;
+);
-parameter NCO_WIDTH = 16;
+
-parameter MIXER_WIDTH = 18;
+// Parameters for numerical precision
-parameter OUTPUT_WIDTH = 18;
+parameter ADC_WIDTH = 8;
-
+parameter NCO_WIDTH = 16;
-// IF frequency parameters
+parameter MIXER_WIDTH = 18;
-parameter IF_FREQ = 120000000;
+parameter OUTPUT_WIDTH = 18;
-parameter FS = 400000000;
+
-parameter PHASE_WIDTH = 32;
+// IF frequency parameters
-
+parameter IF_FREQ = 120000000;
-// Internal signals
+parameter FS = 400000000;
-wire signed [15:0] sin_out, cos_out;
+parameter PHASE_WIDTH = 32;
-wire nco_ready;
+
-wire cic_valid;
+// Internal signals
-wire fir_valid;
+wire signed [15:0] sin_out, cos_out;
-wire [17:0] cic_i_out, cic_q_out;
+wire nco_ready;
-wire signed [17:0] fir_i_out, fir_q_out;
+wire cic_valid;
-
+wire fir_valid;
-
+wire [17:0] cic_i_out, cic_q_out;
+wire signed [17:0] fir_i_out, fir_q_out;
+
+
 // Diagnostic registers
 reg [2:0] saturation_count;
 reg overflow_detected;
 reg [7:0] error_counter;
 
-// ============================================================================
-// 400 MHz Reset Synchronizer
-//
-// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
-// Using it directly as an async reset in the 400 MHz domain causes the reset
-// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
-// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
-// domain, requiring 18.243ns of routing (WNS = -18.081ns).
-//
-// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
-// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
-// path from reset_n to all 400 MHz registers). Reset deassertion is
-// synchronized to clk_400m rising edge, preventing metastability.
-//
-// All 400 MHz submodules (NCO, CIC, mixers, LFSR) use reset_n_400m.
-// All 100 MHz submodules (FIR, output stage) continue using reset_n directly
-// (already synchronized to 100 MHz at radar_system_top level).
-// ============================================================================
-(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
-(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
-
-// Active-high reset for DSP48E1 RST ports (avoids LUT1 inverter fan-out)
-(* max_fanout = 50 *) reg reset_400m;
-
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
-        reset_sync_400m <= 2'b00;
-        reset_400m      <= 1'b1;
-    end else begin
-        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
-        reset_400m      <= ~reset_sync_400m[1];
-    end
-end
-
-// CDC synchronization for control signals (2-stage synchronizers)
-(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
-(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
-wire mixers_enable_sync;
-wire force_saturation_sync;
-
 // Debug monitoring signals
 reg [31:0] sample_counter;
 wire signed [17:0] debug_mixed_i_trunc;
 wire signed [17:0] debug_mixed_q_trunc;
 
 // Real-time status monitoring
-reg [7:0] signal_power_i, signal_power_q;
+reg [7:0] signal_power_i, signal_power_q;
-
+
 // Internal mixing signals
 // Pipeline: NCO fabric reg (1) + DSP48E1 AREG/BREG (1) + MREG (1) + PREG (1) + retiming (1) = 5 cycles
 // The NCO fabric pipeline register was added to break the long NCO→DSP B-port route
@@ -118,61 +81,110 @@ reg [4:0] dsp_valid_pipe;
 // Post-DSP retiming registers — breaks DSP48E1 CLK→P to fabric timing path
 // This extra pipeline stage absorbs the 1.866ns DSP output prop delay + routing,
 // ensuring WNS > 0 at 400 MHz regardless of placement seed
-(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
+(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
-
+
-// Output stage registers
+// Output stage registers
-reg signed [17:0] baseband_i_reg, baseband_q_reg;
+reg signed [17:0] baseband_i_reg, baseband_q_reg;
-reg baseband_valid_reg;
+reg baseband_valid_reg;
-
+
-// ============================================================================
+// ============================================================================
 // Phase Dithering Signals
 // ============================================================================
 wire [7:0] phase_dither_bits;
-reg [31:0] phase_inc_dithered;
+reg [31:0] phase_inc_dithered;
-
+
-
-
-// ============================================================================
-// Debug Signal Assignments
-// ============================================================================
-assign debug_internal_i = mixed_i[25:8];
-assign debug_internal_q = mixed_q[25:8];
-assign debug_sample_count = sample_counter;
-assign debug_mixed_i_trunc = mixed_i[25:8];
-assign debug_mixed_q_trunc = mixed_q[25:8];
-
-// ============================================================================
-// Clock Domain Crossing for Control Signals (2-stage synchronizers)
 // ============================================================================
-assign mixers_enable_sync = mixers_enable_sync_chain[1];
+// Debug Signal Assignments
+// ============================================================================
+assign debug_internal_i = mixed_i[25:8];
+assign debug_internal_q = mixed_q[25:8];
+assign debug_sample_count = sample_counter;
+assign debug_mixed_i_trunc = mixed_i[25:8];
+assign debug_mixed_q_trunc = mixed_q[25:8];
+
+// ============================================================================
+// 400 MHz Reset Synchronizer
+//
+// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
+// Using it directly as an async reset in the 400 MHz domain causes the reset
+// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
+// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
+// domain, requiring 18.243ns of routing (WNS = -18.081ns).
+//
+// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
+// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
+// path from reset_n to all 400 MHz registers). Reset deassertion is
+//
+// reset_400m   : ACTIVE-HIGH registered reset with (* max_fanout = 50 *).
+//                This is THE signal fed to every synchronous 400 MHz FDRE
+//                and every DSP48E1 RST pin in this module and its children
+//                (NCO, CIC, LFSR). Vivado replicates the register (~14
+//                copies) so each replica drives ≈50 loads regionally,
+//                eliminating the single-LUT1 / 702-load net that caused
+//                WNS=-0.626 ns in Build N.
+//
+// System-level invariants preserved:
+//   I1  Reset assertion propagates to all 400 MHz regs within ≤3 clk edges
+//       (2 sync + 1 replicated-reg fanout).  At 400 MHz = 7.5 ns << any
+//       system-level reset assertion duration.
+//   I2  Reset de-assertion is always synchronous to clk_400m (via
+//       reset_sync_400m), never glitches.
+//   I3  DSP48E1 RST pins are all fed from Q of a register — glitch-free.
+//   I4  No new CDC introduced: reset_400m is entirely in clk_400m domain.
+//   I5  Power-up: reset_n is asserted externally and mmcm_locked is low;
+//       reset_sync_400m stays 2'b00, reset_400m stays 1'b1, downstream
+//       FDREs stay cleared. Safe.
+// ============================================================================
+(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m = 2'b00;
+(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
+
+// Active-high replicated reset for all synchronous 400 MHz consumers
+(* max_fanout = 50 *) reg reset_400m = 1'b1;
+
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
+        reset_sync_400m <= 2'b00;
+        reset_400m      <= 1'b1;
+    end else begin
+        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
+        reset_400m      <= ~reset_sync_400m[1];
+    end
+end
+
+// CDC synchronization for control signals (2-stage synchronizers).
+// Audit F-1.3: the mixers_enable synchronizer was dead — its _sync output
+// was never consumed (the NCO phase_valid uses the raw port), and the only
+// caller (radar_receiver_final.v) ties the port to 1'b1. Removed.
+(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
+wire force_saturation_sync;
 assign force_saturation_sync = force_saturation_sync_chain[1];
 
-always @(posedge clk_400m or negedge reset_n_400m) begin
+// Sync reset via reset_400m (replicated, max_fanout=50). Was async on
-    if (!reset_n_400m) begin
+// reset_n_400m — see "400 MHz RESET DISTRIBUTION" comment above.
-        mixers_enable_sync_chain <= 2'b00;
+always @(posedge clk_400m) begin
+    if (reset_400m) begin
         force_saturation_sync_chain <= 2'b00;
     end else begin
-        mixers_enable_sync_chain <= {mixers_enable_sync_chain[0], mixers_enable};
         force_saturation_sync_chain <= {force_saturation_sync_chain[0], force_saturation};
     end
-end
+end
-
+
-// ============================================================================
+// ============================================================================
-// Sample Counter and Debug Monitoring
+// Sample Counter and Debug Monitoring
-// ============================================================================
+// ============================================================================
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m || reset_monitors) begin
+    if (reset_400m || reset_monitors) begin
         sample_counter <= 0;
-        error_counter <= 0;
+        error_counter <= 0;
-    end else if (adc_data_valid_i && adc_data_valid_q ) begin
+    end else if (adc_data_valid_i && adc_data_valid_q ) begin
-        sample_counter <= sample_counter + 1;
+        sample_counter <= sample_counter + 1;
-    end
+    end
-end
+end
-
+
-
+
-// ============================================================================
+// ============================================================================
-// Enhanced Phase Dithering Instance
+// Enhanced Phase Dithering Instance
-// ============================================================================
+// ============================================================================
 lfsr_dither_enhanced #(
     .DITHER_WIDTH(8)
 ) phase_dither_gen (
@@ -180,36 +192,36 @@ lfsr_dither_enhanced #(
     .reset_n(reset_n_400m),
     .enable(nco_ready),
     .dither_out(phase_dither_bits)
-);
+);
-
+
-// ============================================================================
+// ============================================================================
-// Phase Increment Calculation with Dithering
+// Phase Increment Calculation with Dithering
-// ============================================================================
+// ============================================================================
-// Calculate phase increment for 120MHz IF at 400MHz sampling
+// Calculate phase increment for 120MHz IF at 400MHz sampling
-localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
+localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
-
+
 // Apply dithering to reduce spurious tones (registered for 400 MHz timing)
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m)
+    if (reset_400m)
         phase_inc_dithered <= PHASE_INC_120MHZ;
     else
         phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
-end
+end
-
+
-// ============================================================================
+// ============================================================================
-// Enhanced NCO with Diagnostics
+// Enhanced NCO with Diagnostics
-// ============================================================================
+// ============================================================================
 nco_400m_enhanced nco_core (
     .clk_400m(clk_400m),
-    .reset_n(reset_n_400m),
+    .reset_n(reset_n_400m),
-    .frequency_tuning_word(phase_inc_dithered),
+    .frequency_tuning_word(phase_inc_dithered),
-    .phase_valid(mixers_enable),
+    .phase_valid(mixers_enable),
-    .phase_offset(16'h0000),
+    .phase_offset(16'h0000),
-    .sin_out(sin_out),
+    .sin_out(sin_out),
-    .cos_out(cos_out),
+    .cos_out(cos_out),
-    .dds_ready(nco_ready)
+    .dds_ready(nco_ready)
-);
+);
-
+
 // ============================================================================
 // Enhanced Mixing Stage — DSP48E1 direct instantiation for 400 MHz timing
 //
@@ -229,8 +241,8 @@ assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
                       {1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
 
 // Valid pipeline: 5-stage shift register (1 NCO pipe + 3 DSP48E1 AREG+MREG+PREG + 1 retiming)
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
         dsp_valid_pipe <= 5'b00000;
     end else begin
         dsp_valid_pipe <= {dsp_valid_pipe[3:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
@@ -246,8 +258,8 @@ reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal;  // Mod
 reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg;            // Models PREG
 
 // Stage 0: NCO pipeline — breaks long NCO→DSP route (matches synthesis fabric registers)
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
         cos_nco_pipe <= 0;
         sin_nco_pipe <= 0;
     end else begin
@@ -257,8 +269,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
 end
 
 // Stage 1: AREG/BREG equivalent (uses pipelined NCO outputs)
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
         adc_signed_reg <= 0;
         cos_pipe_reg <= 0;
         sin_pipe_reg <= 0;
@@ -270,8 +282,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
 end
 
 // Stage 2: MREG equivalent
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
         mult_i_internal <= 0;
         mult_q_internal <= 0;
     end else begin
@@ -281,8 +293,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
 end
 
 // Stage 3: PREG equivalent
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
         mult_i_reg <= 0;
         mult_q_reg <= 0;
     end else begin
@@ -292,8 +304,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
 end
 
 // Stage 4: Post-DSP retiming register (matches synthesis path)
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
         mult_i_retimed <= 0;
         mult_q_retimed <= 0;
     end else begin
@@ -311,8 +323,8 @@ wire [47:0] dsp_p_i, dsp_p_q;
 // (1.505ns routing observed in Build 26). These fabric registers are placed
 // near the DSP by the placer, splitting the route into two shorter segments.
 // DONT_TOUCH on the reg declaration (above) prevents absorption/retiming.
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
         cos_nco_pipe <= 0;
         sin_nco_pipe <= 0;
     end else begin
@@ -329,11 +341,10 @@ DSP48E1 #(
     .USE_DPORT("FALSE"),
     .USE_MULT("MULTIPLY"),
     .USE_SIMD("ONE48"),
-    // Pipeline register attributes — all enabled for max timing
     .AREG(1),
     .BREG(1),
     .MREG(1),
-    .PREG(1),           // P register enabled — absorbs CLK→P delay for timing closure
+    .PREG(1),
     .ADREG(0),
     .ACASCREG(1),
     .BCASCREG(1),
@@ -344,7 +355,6 @@ DSP48E1 #(
     .DREG(0),
     .INMODEREG(0),
     .OPMODEREG(0),
-    // Pattern detector (unused)
     .AUTORESET_PATDET("NO_RESET"),
     .MASK(48'h3fffffffffff),
     .PATTERN(48'h000000000000),
@@ -496,8 +506,8 @@ wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WID
 // Stage 4: Post-DSP retiming register — breaks DSP48E1 CLK→P to fabric path
 // Without this, the DSP output prop delay (1.866ns) + routing (0.515ns) exceeds
 // the 2.500ns clock period at slow process corner
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
         mult_i_retimed <= 0;
         mult_q_retimed <= 0;
     end else begin
@@ -513,8 +523,8 @@ end
 // force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
 // polluting the critical input path with extra logic
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
         mixed_i <= 0;
         mixed_q <= 0;
         mixed_valid <= 0;
@@ -556,31 +566,31 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
         mixer_overflow_q <= 0;
         overflow_detected <= 1'b0;
     end
-end
+end
-
+
-// ============================================================================
+// ============================================================================
-// Enhanced CIC Decimators
+// Enhanced CIC Decimators
-// ============================================================================
+// ============================================================================
-wire cic_valid_i, cic_valid_q;
+wire cic_valid_i, cic_valid_q;
-
+
 cic_decimator_4x_enhanced cic_i_inst (
     .clk(clk_400m),
-    .reset_n(reset_n_400m),
+    .reset_n(reset_n_400m),
-    .data_in(mixed_i[33:16]),
+    .data_in(mixed_i[33:16]),
-    .data_valid(mixed_valid),
+    .data_valid(mixed_valid),
-    .data_out(cic_i_out),
+    .data_out(cic_i_out),
-    .data_out_valid(cic_valid_i)
+    .data_out_valid(cic_valid_i)
-);
+);
-
+
 cic_decimator_4x_enhanced cic_q_inst (
     .clk(clk_400m),
-    .reset_n(reset_n_400m),
+    .reset_n(reset_n_400m),
-    .data_in(mixed_q[33:16]),
+    .data_in(mixed_q[33:16]),
-    .data_valid(mixed_valid),
+    .data_valid(mixed_valid),
-    .data_out(cic_q_out),
+    .data_out(cic_q_out),
-    .data_out_valid(cic_valid_q)
+    .data_out_valid(cic_valid_q)
-);
+);
-
+
 assign cic_valid = cic_valid_i & cic_valid_q;
 
 // ============================================================================
@@ -591,98 +601,120 @@ assign cic_valid = cic_valid_i & cic_valid_q;
 wire fir_in_valid_i, fir_in_valid_q;
 wire fir_valid_i, fir_valid_q;
 wire fir_i_ready, fir_q_ready;
-wire [17:0] fir_d_in_i, fir_d_in_q; 
+wire [17:0] fir_d_in_i, fir_d_in_q;
+// Audit F-1.2: per-lane CIC→FIR CDC overrun pulses (clk_400m domain)
+wire cdc_fir_i_overrun;
+wire cdc_fir_q_overrun;
 
-cdc_adc_to_processing #(
+cdc_adc_to_processing #(
-    .WIDTH(18),
+    .WIDTH(18),
-    .STAGES(3)
+    .STAGES(3)
 )CDC_FIR_i(
     .src_clk(clk_400m),
     .dst_clk(clk_100m),
     .src_reset_n(reset_n_400m),
-    .dst_reset_n(reset_n),
+    .dst_reset_n(reset_n),
-    .src_data(cic_i_out),
+    .src_data(cic_i_out),
-    .src_valid(cic_valid_i),
+    .src_valid(cic_valid_i),
-    .dst_data(fir_d_in_i),
+    .dst_data(fir_d_in_i),
-    .dst_valid(fir_in_valid_i)
+    .dst_valid(fir_in_valid_i),
+    .overrun(cdc_fir_i_overrun)
 );
 
-cdc_adc_to_processing #(
+cdc_adc_to_processing #(
-    .WIDTH(18),
+    .WIDTH(18),
-    .STAGES(3)
+    .STAGES(3)
 )CDC_FIR_q(
     .src_clk(clk_400m),
     .dst_clk(clk_100m),
     .src_reset_n(reset_n_400m),
-    .dst_reset_n(reset_n),
+    .dst_reset_n(reset_n),
-    .src_data(cic_q_out),
+    .src_data(cic_q_out),
-    .src_valid(cic_valid_q),
+    .src_valid(cic_valid_q),
-    .dst_data(fir_d_in_q),
+    .dst_data(fir_d_in_q),
-    .dst_valid(fir_in_valid_q)
+    .dst_valid(fir_in_valid_q),
-);
+    .overrun(cdc_fir_q_overrun)
-
+);
+
+// Audit F-1.2: sticky-latch the two per-lane overrun pulses in the 400 MHz
+// domain and expose a single module-level flag. Cleared only by
+// reset_monitors (or reset_n via reset_400m), matching the other DDC
+// diagnostic latches (overflow/saturation).
+reg  cdc_cic_fir_overrun_sticky;
+always @(posedge clk_400m) begin
+    if (reset_400m || reset_monitors)                         cdc_cic_fir_overrun_sticky <= 1'b0;
+    else if (cdc_fir_i_overrun || cdc_fir_q_overrun)          cdc_cic_fir_overrun_sticky <= 1'b1;
+end
+assign cdc_cic_fir_overrun = cdc_cic_fir_overrun_sticky;
+
 // ============================================================================
 // FIR Filter Instances
 // ============================================================================
 
-// FIR I channel
+// FIR overflow flags (audit F-6.2 — previously dangling, now OR'd into
-fir_lowpass_parallel_enhanced fir_i_inst (
+// module-level filter_overflow so the receiver can see FIR arithmetic overflow)
-    .clk(clk_100m),
+wire fir_i_overflow;
-    .reset_n(reset_n),
+wire fir_q_overflow;
-    .data_in(fir_d_in_i),  // Use synchronized data
+
-    .data_valid(fir_in_valid_i),  // Use synchronized valid
+// FIR I channel
-    .data_out(fir_i_out),
+fir_lowpass_parallel_enhanced fir_i_inst (
-    .data_out_valid(fir_valid_i),
+    .clk(clk_100m),
-    .fir_ready(fir_i_ready),
+    .reset_n(reset_n),
-    .filter_overflow()
+    .data_in(fir_d_in_i),  // Use synchronized data
-);
+    .data_valid(fir_in_valid_i),  // Use synchronized valid
-
+    .data_out(fir_i_out),
-// FIR Q channel  
+    .data_out_valid(fir_valid_i),
-fir_lowpass_parallel_enhanced fir_q_inst (
+    .fir_ready(fir_i_ready),
-    .clk(clk_100m),
+    .filter_overflow(fir_i_overflow)
-    .reset_n(reset_n),
+);
-    .data_in(fir_d_in_q),  // Use synchronized data
+
-    .data_valid(fir_in_valid_q),  // Use synchronized valid
+// FIR Q channel
-    .data_out(fir_q_out),
+fir_lowpass_parallel_enhanced fir_q_inst (
-    .data_out_valid(fir_valid_q),
+    .clk(clk_100m),
-    .fir_ready(fir_q_ready),
+    .reset_n(reset_n),
-    .filter_overflow()
+    .data_in(fir_d_in_q),  // Use synchronized data
-);
+    .data_valid(fir_in_valid_q),  // Use synchronized valid
-
+    .data_out(fir_q_out),
-assign fir_valid = fir_valid_i & fir_valid_q;
+    .data_out_valid(fir_valid_q),
-
+    .fir_ready(fir_q_ready),
-// ============================================================================
+    .filter_overflow(fir_q_overflow)
-// Enhanced Output Stage
+);
-// ============================================================================
+
-always @(posedge clk_100m or negedge reset_n) begin
+assign fir_valid = fir_valid_i & fir_valid_q;
-    if (!reset_n) begin
+assign filter_overflow = fir_i_overflow | fir_q_overflow;
-        baseband_i_reg <= 0;
+
-        baseband_q_reg <= 0;
+// ============================================================================
-        baseband_valid_reg <= 0;
+// Enhanced Output Stage
-    end else if (fir_valid) begin
+// ============================================================================
-        baseband_i_reg <= fir_i_out;
+always @(posedge clk_100m or negedge reset_n) begin
-        baseband_q_reg <= fir_q_out;
+    if (!reset_n) begin
-        baseband_valid_reg <= 1;
+        baseband_i_reg <= 0;
-    end else begin
+        baseband_q_reg <= 0;
-        baseband_valid_reg <= 0;
+        baseband_valid_reg <= 0;
-    end
+    end else if (fir_valid) begin
-end
+        baseband_i_reg <= fir_i_out;
-
+        baseband_q_reg <= fir_q_out;
-
+        baseband_valid_reg <= 1;
-// ============================================================================
+    end else begin
-// Output Assignments
+        baseband_valid_reg <= 0;
-// ============================================================================
+    end
-assign baseband_i = baseband_i_reg;
+end
-assign baseband_q = baseband_q_reg;
+
+
+// ============================================================================
+// Output Assignments
+// ============================================================================
+assign baseband_i = baseband_i_reg;
+assign baseband_q = baseband_q_reg;
 assign baseband_valid_i = baseband_valid_reg;
-assign baseband_valid_q = baseband_valid_reg;
+assign baseband_valid_q = baseband_valid_reg;
-assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
+assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
-assign mixer_saturation = overflow_detected;
+assign mixer_saturation = overflow_detected;
-assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
+assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
-
+
-// ============================================================================
+// ============================================================================
-// Enhanced Debug and Monitoring
+// Enhanced Debug and Monitoring
-// ============================================================================
+// ============================================================================
 reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;
 
 `ifdef SIMULATION
@@ -699,10 +731,10 @@ always @(posedge clk_100m) begin
                  baseband_i, baseband_q, debug_bb_count);
     end
 end
-`endif
+`endif
-
+
-// In ddc_400m.v, add these debug signals:
+// In ddc_400m.v, add these debug signals:
-
+
 // Debug monitoring (simulation only)
 `ifdef SIMULATION
 reg [31:0] debug_adc_count = 0;
@@ -723,58 +755,67 @@ always @(posedge clk_100m) begin
                  baseband_i, baseband_q, debug_baseband_count, $time);
     end
 end
-`endif
+`endif
-
+
-
+
-endmodule
+endmodule
-
+
-// ============================================================================
+// ============================================================================
-// Enhanced Phase Dithering Module
+// Enhanced Phase Dithering Module
-// ============================================================================
+// ============================================================================
-`timescale 1ns / 1ps
+`timescale 1ns / 1ps
-
+
-module lfsr_dither_enhanced #(
+module lfsr_dither_enhanced #(
-    parameter DITHER_WIDTH = 8  // Increased for better dithering
+    parameter DITHER_WIDTH = 8  // Increased for better dithering
-)(
+)(
-    input wire clk,
+    input wire clk,
-    input wire reset_n,
+    input wire reset_n,
-    input wire enable,
+    input wire enable,
-    output wire [DITHER_WIDTH-1:0] dither_out
+    output wire [DITHER_WIDTH-1:0] dither_out
-);
+);
-
+
-reg [DITHER_WIDTH-1:0] lfsr_reg;
+reg [DITHER_WIDTH-1:0] lfsr_reg;
-reg [15:0] cycle_counter;
+reg [15:0] cycle_counter;
-reg lock_detected;
+reg lock_detected;
-
+
-// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
+// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
-wire feedback;
+wire feedback;
-
+
-generate
+generate
-    if (DITHER_WIDTH == 4) begin
+    if (DITHER_WIDTH == 4) begin
-        assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
+        assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
-    end else if (DITHER_WIDTH == 8) begin
+    end else if (DITHER_WIDTH == 8) begin
-        assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
+        assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
-    end else begin
+    end else begin
-        assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
+        assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
-    end
+    end
-endgenerate
+endgenerate
-
+
-always @(posedge clk or negedge reset_n) begin
+// ============================================================================
-    if (!reset_n) begin
+// RESET FAN-OUT INVARIANT: registered active-high reset with max_fanout=50.
-        lfsr_reg <= {DITHER_WIDTH{1'b1}};  // Non-zero initial state
+// See cic_decimator_4x_enhanced.v for full reasoning. reset_n here is driven
-        cycle_counter <= 0;
+// by the parent DDC's reset_n_400m (already synchronized to clk_400m), so
-        lock_detected <= 0;
+// sync reset on the LFSR is safe. INIT=1'b1 holds LFSR in reset on power-up.
-    end else if (enable) begin
+// ============================================================================
-        lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
+(* max_fanout = 50 *) reg reset_h = 1'b1;
-        cycle_counter <= cycle_counter + 1;
+always @(posedge clk) reset_h <= ~reset_n;
-        
+
-        // Detect LFSR lock after sufficient cycles
+always @(posedge clk) begin
-        if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
+    if (reset_h) begin
-            lock_detected <= 1'b1;
+        lfsr_reg <= {DITHER_WIDTH{1'b1}};  // Non-zero initial state
-        end
+        cycle_counter <= 0;
-    end
+        lock_detected <= 0;
-end
+    end else if (enable) begin
-
+        lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
-assign dither_out = lfsr_reg;
+        cycle_counter <= cycle_counter + 1;
-
+        
-endmodule
+        // Detect LFSR lock after sufficient cycles
+        if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
+            lock_detected <= 1'b1;
+        end
+    end
+end
+
+assign dither_out = lfsr_reg;
+
+endmodule

9_Firmware/9_2_FPGA/mti_canceller.v

@@ -58,7 +58,12 @@ module mti_canceller #(
     input wire mti_enable,   // 1=MTI active, 0=pass-through
 
     // ========== STATUS ==========
-    output reg mti_first_chirp  // 1 during first chirp (output muted)
+    output reg mti_first_chirp, // 1 during first chirp (output muted)
+
+    // Audit F-6.3: count of saturated samples since last reset. Saturation
+    // here produces spurious Doppler harmonics (phantom targets at ±fs/2)
+    // and was previously invisible to the MCU. Saturates at 0xFF.
+    output reg [7:0] mti_saturation_count
 );
 
 // ============================================================================
@@ -104,18 +109,30 @@ assign diff_q_sat = (diff_q_full > $signed({{2{1'b0}}, {(DATA_WIDTH-1){1'b1}}}))
                   ? $signed({1'b1, {(DATA_WIDTH-1){1'b0}}})
                   : diff_q_full[DATA_WIDTH-1:0];
 
+// Saturation detection (F-6.3): the top two bits of the DATA_WIDTH+1 signed
+// difference disagree iff the value exceeds the DATA_WIDTH signed range.
+wire diff_i_overflow = (diff_i_full[DATA_WIDTH] != diff_i_full[DATA_WIDTH-1]);
+wire diff_q_overflow = (diff_q_full[DATA_WIDTH] != diff_q_full[DATA_WIDTH-1]);
+
 // ============================================================================
 // MAIN LOGIC
 // ============================================================================
 always @(posedge clk or negedge reset_n) begin
     if (!reset_n) begin
-        range_i_out     <= {DATA_WIDTH{1'b0}};
+        range_i_out          <= {DATA_WIDTH{1'b0}};
-        range_q_out     <= {DATA_WIDTH{1'b0}};
+        range_q_out          <= {DATA_WIDTH{1'b0}};
-        range_valid_out <= 1'b0;
+        range_valid_out      <= 1'b0;
-        range_bin_out   <= 6'd0;
+        range_bin_out        <= 6'd0;
-        has_previous    <= 1'b0;
+        has_previous         <= 1'b0;
-        mti_first_chirp <= 1'b1;
+        mti_first_chirp      <= 1'b1;
+        mti_saturation_count <= 8'd0;
     end else begin
+        // Count saturated MTI-active samples (F-6.3). Clamp at 0xFF.
+        if (range_valid_in && mti_enable && has_previous
+            && (diff_i_overflow || diff_q_overflow)
+            && (mti_saturation_count != 8'hFF)) begin
+            mti_saturation_count <= mti_saturation_count + 8'd1;
+        end
         // Default: no valid output
         range_valid_out <= 1'b0;
 

9_Firmware/9_2_FPGA/nco_400m_enhanced.v

@@ -59,6 +59,25 @@ reg [1:0] quadrant_reg2;                 // Pass-through for Stage 5 MUX
 // Valid pipeline: tracks 6-stage latency
 reg [5:0] valid_pipe;
 
+// ============================================================================
+// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
+// ============================================================================
+// reset_h is an ACTIVE-HIGH, REGISTERED copy of ~reset_n with (* max_fanout=50 *).
+// Vivado replicates this register (14+ copies) so each copy drives ≈50 loads
+// regionally, avoiding the single-LUT1 / 702-load net that caused timing
+// failure in Build N. It feeds:
+//   - DSP48E1 RSTP/RSTC on the phase-accumulator DSP (below)
+//   - All pipeline-stage fabric FDREs (synchronous reset)
+// Invariants (see cic_decimator_4x_enhanced.v for full reasoning):
+//   I1 correctness:      reset_h == ~reset_n one cycle later
+//   I2 glitch-free:      registered output
+//   I3 power-up safe:    INIT=1'b1 holds all downstream in reset until first
+//                        valid clock edge; reset_n is low on power-up anyway
+//   I4 de-assert lat.:   +1 cycle vs. direct async; negligible at 400 MHz
+// ============================================================================
+(* max_fanout = 50 *) reg reset_h = 1'b1;
+always @(posedge clk_400m) reset_h <= ~reset_n;
+
 // Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
 wire [7:0] lut_address = phase_with_offset[31:24];
 
@@ -135,8 +154,8 @@ wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe_cos];
 // Stage 2: phase_with_offset adds phase offset
 reg [31:0] phase_accumulator;
 
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         phase_accumulator <= 32'h00000000;
         phase_accum_reg   <= 32'h00000000;
         phase_with_offset <= 32'h00000000;
@@ -190,8 +209,8 @@ DSP48E1 #(
     .RSTA(1'b0),
     .RSTB(1'b0),
     .RSTM(1'b0),
-    .RSTP(!reset_n),             // Reset P register (phase accumulator) on !reset_n
+    .RSTP(reset_h),              // Reset P register (phase accumulator) — registered, max_fanout=50
-    .RSTC(!reset_n),             // Reset C register (tuning word) on !reset_n
+    .RSTC(reset_h),              // Reset C register (tuning word)       — registered, max_fanout=50
     .RSTALLCARRYIN(1'b0),
     .RSTALUMODE(1'b0),
     .RSTCTRL(1'b0),
@@ -245,8 +264,8 @@ DSP48E1 #(
 // Stage 1: Capture DSP48E1 P output into fabric register
 // Stage 2: Add phase offset to captured value
 // Split into two registered stages to break DSP48E1.P→CARRY4 critical path
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         phase_accum_reg   <= 32'h00000000;
         phase_with_offset <= 32'h00000000;
     end else if (phase_valid) begin
@@ -264,8 +283,8 @@ end
 //           Only 2 registers driven (lut_index_pipe + quadrant_pipe)
 //           Minimal fanout → short routes → easy timing
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         lut_index_pipe_sin <= 6'b000000;
         lut_index_pipe_cos <= 6'b000000;
         quadrant_pipe      <= 2'b00;
@@ -281,8 +300,8 @@ end
 //           Registered address → combinational LUT6 read → register
 //           Only 1 logic level (LUT6), trivial timing
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         sin_abs_reg <= 16'h0000;
         cos_abs_reg <= 16'h7FFF;
         quadrant_reg <= 2'b00;
@@ -298,8 +317,8 @@ end
 //          CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
 //          Also pass through abs values and quadrant for Stage 5
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         sin_neg_reg <= 16'h0000;
         cos_neg_reg <= -16'h7FFF;
         sin_abs_reg2 <= 16'h0000;
@@ -318,8 +337,8 @@ end
 // Stage 5: Quadrant sign application → final sin/cos output
 //          Uses pre-computed negated values from Stage 4 — pure MUX, no arithmetic
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         sin_out <= 16'h0000;
         cos_out <= 16'h7FFF;
     end else if (valid_pipe[4]) begin
@@ -347,8 +366,8 @@ end
 // ============================================================================
 // Valid pipeline and dds_ready (6-stage latency)
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
         valid_pipe <= 6'b000000;
         dds_ready <= 1'b0;
     end else begin

9_Firmware/9_2_FPGA/radar_receiver_final.v

@@ -9,6 +9,9 @@ module radar_receiver_final (
     input wire [7:0] adc_d_n,        // ADC Data N (LVDS)
     input wire adc_dco_p,            // Data Clock Output P (400MHz LVDS)
     input wire adc_dco_n,            // Data Clock Output N (400MHz LVDS)
+    // Audit F-0.1: AD9484 OR (overrange) LVDS pair
+    input wire adc_or_p,
+    input wire adc_or_n,
 	 output wire adc_pwdn,
     
     // Chirp counter from transmitter (for matched filter indexing)
@@ -74,7 +77,28 @@ module radar_receiver_final (
     // AGC status outputs (for status readback / STM32 outer loop)
     output wire [7:0]  agc_saturation_count, // Per-frame clipped sample count
     output wire [7:0]  agc_peak_magnitude,   // Per-frame peak (upper 8 bits)
-    output wire [3:0]  agc_current_gain      // Effective gain_shift encoding
+    output wire [3:0]  agc_current_gain,     // Effective gain_shift encoding
+
+    // DDC overflow diagnostics (audit F-6.1 — previously deleted at boundary).
+    // Not yet plumbed into the USB status packet (protocol contract is frozen);
+    // exposed here for gpio aggregation and ILA mark_debug visibility.
+    output wire        ddc_overflow_any,
+    output wire [2:0]  ddc_saturation_count,
+
+    // MTI 2-pulse canceller saturation count (audit F-6.3).
+    output wire [7:0]  mti_saturation_count_out,
+
+    // Range-bin decimator watchdog (audit F-6.4 — previously tied off
+    // with an ILA-only note). A high pulse here means the decimator
+    // FSM has not seen the expected number of input samples within
+    // its timeout window, i.e. the upstream FIR/CDC has stalled.
+    output wire        range_decim_watchdog,
+
+    // Audit F-1.2: sticky CIC→FIR CDC overrun flag. Asserts on the first
+    // silent sample drop between the 400 MHz CIC output and the 100 MHz
+    // FIR input; stays high until the next reset. OR'd into the GPIO
+    // diagnostic bit at the top level.
+    output wire        ddc_cic_fir_overrun
 );
 
 // ========== INTERNAL SIGNALS ==========
@@ -185,18 +209,43 @@ wire adc_valid;            // Data valid signal
 // ADC power-down control (directly tie low = ADC always on)
 assign adc_pwdn = 1'b0;
 
+wire adc_overrange_400m;
 ad9484_interface_400m adc (
 	.adc_d_p(adc_d_p),
 	.adc_d_n(adc_d_n),
 	.adc_dco_p(adc_dco_p),
 	.adc_dco_n(adc_dco_n),
+	.adc_or_p(adc_or_p),
+	.adc_or_n(adc_or_n),
 	.sys_clk(clk),
 	.reset_n(reset_n),
 	.adc_data_400m(adc_data_cmos),
 	.adc_data_valid_400m(adc_valid),
-	.adc_dco_bufg(clk_400m)
+	.adc_dco_bufg(clk_400m),
+	.adc_overrange_400m(adc_overrange_400m)
 );
 
+// Audit F-0.1: stickify the 400 MHz OR pulse, then CDC to clk_100m via 2FF.
+// Same reasoning as ddc_cic_fir_overrun: single-bit, low→high-only once
+// latched, so a 2FF sync is sufficient for a GPIO-class diagnostic. Cleared
+// only by global reset_n.
+reg adc_overrange_sticky_400m;
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n)
+        adc_overrange_sticky_400m <= 1'b0;
+    else if (adc_overrange_400m)
+        adc_overrange_sticky_400m <= 1'b1;
+end
+
+(* ASYNC_REG = "TRUE" *) reg [1:0] adc_overrange_sync_100m;
+always @(posedge clk or negedge reset_n) begin
+    if (!reset_n)
+        adc_overrange_sync_100m <= 2'b00;
+    else
+        adc_overrange_sync_100m <= {adc_overrange_sync_100m[0], adc_overrange_sticky_400m};
+end
+wire adc_overrange_100m = adc_overrange_sync_100m[1];
+
 // NOTE: The cdc_adc_to_processing instance that was here used src_clk=dst_clk=clk_400m
 // (same clock domain — no crossing). Gray-code CDC on same-clock with fast-changing
 // ADC data corrupts samples because Gray coding only guarantees safe transfer of
@@ -211,6 +260,16 @@ wire signed [17:0] ddc_out_q;
 wire ddc_valid_i;
 wire ddc_valid_q;
 
+// DDC diagnostic signals (audit F-6.1 — all outputs previously unconnected)
+wire [1:0] ddc_status_w;
+wire [7:0] ddc_diagnostics_w;
+wire       ddc_mixer_saturation;
+wire       ddc_filter_overflow;
+
+(* mark_debug = "true" *) wire ddc_mixer_saturation_dbg = ddc_mixer_saturation;
+(* mark_debug = "true" *) wire ddc_filter_overflow_dbg  = ddc_filter_overflow;
+(* mark_debug = "true" *) wire [7:0] ddc_diagnostics_dbg = ddc_diagnostics_w;
+
 ddc_400m_enhanced ddc(
     .clk_400m(clk_400m),           // 400MHz clock from ADC DCO
     .clk_100m(clk),           // 100MHz system clock //used by the 2 FIR
@@ -219,12 +278,31 @@ ddc_400m_enhanced ddc(
     .adc_data_valid_i(adc_valid),     // Valid at 400MHz
     .adc_data_valid_q(adc_valid),     // Valid at 400MHz
     .baseband_i(ddc_out_i), // I output at 100MHz
-    .baseband_q(ddc_out_q), // Q output at 100MHz  
+    .baseband_q(ddc_out_q), // Q output at 100MHz
     .baseband_valid_i(ddc_valid_i),     // Valid at 100MHz
-	 .baseband_valid_q(ddc_valid_q),
+    .baseband_valid_q(ddc_valid_q),
- 	 .mixers_enable(1'b1)
+    .mixers_enable(1'b1),
+    // Diagnostics (audit F-6.1) — previously all unconnected
+    .ddc_status(ddc_status_w),
+    .ddc_diagnostics(ddc_diagnostics_w),
+    .mixer_saturation(ddc_mixer_saturation),
+    .filter_overflow(ddc_filter_overflow),
+    // Test/debug inputs — explicit tie-low (were floating)
+    .test_mode(2'b00),
+    .test_phase_inc(16'h0000),
+    .force_saturation(1'b0),
+    .reset_monitors(1'b0),
+    .debug_sample_count(),
+    .debug_internal_i(),
+    .debug_internal_q(),
+    .cdc_cic_fir_overrun(ddc_cic_fir_overrun)
 );
 
+// Audit F-0.1: AD9484 overrange aggregated here so a single gpio_dig bit
+// covers DDC-internal saturation, FIR overflow, AND raw ADC clipping.
+assign ddc_overflow_any     = ddc_mixer_saturation | ddc_filter_overflow | adc_overrange_100m;
+assign ddc_saturation_count = ddc_diagnostics_w[7:5];
+
 ddc_input_interface ddc_if (
     .clk(clk),
     .reset_n(reset_n),
@@ -369,7 +447,7 @@ range_bin_decimator #(
     .range_bin_index(decimated_range_bin),
     .decimation_mode(2'b01),           // Peak detection mode
     .start_bin(10'd0),
-    .watchdog_timeout()                // Diagnostic — unconnected (monitored via ILA if needed)
+    .watchdog_timeout(range_decim_watchdog)  // Audit F-6.4 — plumbed out
 );
 
 // ========== MTI CANCELLER (Ground Clutter Removal) ==========
@@ -391,7 +469,8 @@ mti_canceller #(
     .range_valid_out(mti_range_valid),
     .range_bin_out(mti_range_bin),
     .mti_enable(host_mti_enable),
-    .mti_first_chirp(mti_first_chirp)
+    .mti_first_chirp(mti_first_chirp),
+    .mti_saturation_count(mti_saturation_count_out)
 );
 
 // ========== FRAME SYNC FROM TRANSMITTER ==========
@@ -430,12 +509,12 @@ assign range_data_32bit = {mti_range_q, mti_range_i};
 assign range_data_valid = mti_range_valid;
 
 // ========== DOPPLER PROCESSOR ==========
-doppler_processor_optimized #(
+doppler_processor_optimized #(
-    .DOPPLER_FFT_SIZE(16),
+    .DOPPLER_FFT_SIZE(16),
-    .RANGE_BINS(64),
+    .RANGE_BINS(64),
-    .CHIRPS_PER_FRAME(32),
+    .CHIRPS_PER_FRAME(32),
-    .CHIRPS_PER_SUBFRAME(16)
+    .CHIRPS_PER_SUBFRAME(16)
-) doppler_proc (
+) doppler_proc (
     .clk(clk),
     .reset_n(reset_n),
     .range_data(range_data_32bit),
@@ -498,4 +577,4 @@ assign agc_saturation_count = gc_saturation_count;
 assign agc_peak_magnitude   = gc_peak_magnitude;
 assign agc_current_gain     = gc_current_gain;
 
-endmodule
+endmodule

9_Firmware/9_2_FPGA/radar_system_top.v

@@ -67,6 +67,9 @@ module radar_system_top (
     input wire [7:0] adc_d_n,            // ADC Data N (LVDS)
     input wire adc_dco_p,                 // Data Clock Output P (400MHz LVDS)
     input wire adc_dco_n,                 // Data Clock Output N (400MHz LVDS)
+    // Audit F-0.1: AD9484 OR (overrange) LVDS pair
+    input wire adc_or_p,
+    input wire adc_or_n,
     output wire adc_pwdn,                  // ADC Power Down
     
     // ========== STM32 CONTROL INTERFACES ==========
@@ -142,7 +145,7 @@ module radar_system_top (
 parameter USE_LONG_CHIRP = 1'b1;          // Default to long chirp
 parameter DOPPLER_ENABLE = 1'b1;           // Enable Doppler processing
 parameter USB_ENABLE = 1'b1;               // Enable USB data transfer
-parameter USB_MODE = 0;                    // 0=FT601 (32-bit, 200T), 1=FT2232H (8-bit, 50T)
+parameter USB_MODE = 1;                    // 0=FT601 (32-bit, 200T), 1=FT2232H (8-bit, 50T production default)
 
 // ============================================================================
 // INTERNAL SIGNALS
@@ -198,6 +201,19 @@ wire [7:0]  rx_agc_saturation_count;
 wire [7:0]  rx_agc_peak_magnitude;
 wire [3:0]  rx_agc_current_gain;
 
+// DDC overflow diagnostics (audit F-6.1) — plumbed out of receiver so the
+// DDC mixer_saturation / filter_overflow ports are no longer deleted at
+// the boundary. Aggregated into gpio_dig5 alongside AGC saturation.
+wire        rx_ddc_overflow_any;
+wire [2:0]  rx_ddc_saturation_count;
+// MTI saturation count (audit F-6.3). OR'd into gpio_dig5 for MCU visibility.
+wire [7:0]  rx_mti_saturation_count;
+// Range-bin decimator watchdog (audit F-6.4). High = decimator stalled.
+wire        rx_range_decim_watchdog;
+// CIC→FIR CDC overrun sticky (audit F-1.2). High = at least one baseband
+// sample has been silently dropped between the 400 MHz CIC and 100 MHz FIR.
+wire        rx_ddc_cic_fir_overrun;
+
 // Data packing for USB
 wire [31:0] usb_range_profile;
 wire usb_range_valid;
@@ -243,12 +259,12 @@ reg [5:0]  host_chirps_per_elev;      // Opcode 0x15 (default 32)
 reg        host_status_request;       // Opcode 0xFF (self-clearing pulse)
 
 // Fix 4: Doppler/chirps mismatch protection
-// DOPPLER_FRAME_CHIRPS is the fixed chirp count expected by the staggered-PRI
+// DOPPLER_FRAME_CHIRPS is the fixed chirp count expected by the staggered-PRI
-// Doppler path (16 long + 16 short). If host sets chirps_per_elev to a
+// Doppler path (16 long + 16 short). If host sets chirps_per_elev to a
-// different value, Doppler accumulation is corrupted. Clamp at command decode
+// different value, Doppler accumulation is corrupted. Clamp at command decode
-// and flag the mismatch so the host knows.
+// and flag the mismatch so the host knows.
-localparam DOPPLER_FRAME_CHIRPS = 32; // Total chirps per Doppler frame
+localparam DOPPLER_FRAME_CHIRPS = 32; // Total chirps per Doppler frame
-reg        chirps_mismatch_error;     // Set if host tried to set chirps != FFT size
+reg        chirps_mismatch_error;     // Set if host tried to set chirps != FFT size
 
 // Fix 7: Range-mode register (opcode 0x20)
 // Future-proofing for 3km/10km antenna switching.
@@ -513,6 +529,8 @@ radar_receiver_final rx_inst (
     .adc_d_n(adc_d_n),
     .adc_dco_p(adc_dco_p),
     .adc_dco_n(adc_dco_n),
+    .adc_or_p(adc_or_p),
+    .adc_or_n(adc_or_n),
     .adc_pwdn(adc_pwdn),
     
     // Doppler Outputs
@@ -562,7 +580,15 @@ radar_receiver_final rx_inst (
     // AGC status outputs
     .agc_saturation_count(rx_agc_saturation_count),
     .agc_peak_magnitude(rx_agc_peak_magnitude),
-    .agc_current_gain(rx_agc_current_gain)
+    .agc_current_gain(rx_agc_current_gain),
+    // DDC overflow diagnostics (audit F-6.1)
+    .ddc_overflow_any(rx_ddc_overflow_any),
+    .ddc_saturation_count(rx_ddc_saturation_count),
+    // MTI saturation count (audit F-6.3)
+    .mti_saturation_count_out(rx_mti_saturation_count),
+    // Range-bin decimator watchdog (audit F-6.4)
+    .range_decim_watchdog(rx_range_decim_watchdog),
+    .ddc_cic_fir_overrun(rx_ddc_cic_fir_overrun)
 );
 
 // ============================================================================
@@ -578,21 +604,21 @@ assign rx_doppler_data_valid = rx_doppler_valid;
 // ============================================================================
 // DC NOTCH FILTER (post-Doppler-FFT, pre-CFAR)
 // ============================================================================
-// Zeros out Doppler bins within ±host_dc_notch_width of DC for BOTH
+// Zeros out Doppler bins within ±host_dc_notch_width of DC for BOTH
-// sub-frames in the dual 16-pt FFT architecture.
+// sub-frames in the dual 16-pt FFT architecture.
-// doppler_bin[4:0] = {sub_frame, bin[3:0]}:
+// doppler_bin[4:0] = {sub_frame, bin[3:0]}:
-//   Sub-frame 0: bins 0-15,  DC = bin 0,  wrap = bin 15
+//   Sub-frame 0: bins 0-15,  DC = bin 0,  wrap = bin 15
-//   Sub-frame 1: bins 16-31, DC = bin 16, wrap = bin 31
+//   Sub-frame 1: bins 16-31, DC = bin 16, wrap = bin 31
-// notch_width=1 → zero bins {0,16}. notch_width=2 → zero bins
+// notch_width=1 → zero bins {0,16}. notch_width=2 → zero bins
-// {0,1,15,16,17,31}. etc.
+// {0,1,15,16,17,31}. etc.
-// When host_dc_notch_width=0: pass-through (no zeroing).
+// When host_dc_notch_width=0: pass-through (no zeroing).
-
+
-wire dc_notch_active;
+wire dc_notch_active;
-wire [4:0] dop_bin_unsigned = rx_doppler_bin;
+wire [4:0] dop_bin_unsigned = rx_doppler_bin;
-wire [3:0] bin_within_sf = dop_bin_unsigned[3:0];
+wire [3:0] bin_within_sf = dop_bin_unsigned[3:0];
-assign dc_notch_active = (host_dc_notch_width != 3'd0) &&
+assign dc_notch_active = (host_dc_notch_width != 3'd0) &&
-                          (bin_within_sf < {1'b0, host_dc_notch_width} ||
+                          (bin_within_sf < {1'b0, host_dc_notch_width} ||
-                           bin_within_sf > (4'd15 - {1'b0, host_dc_notch_width} + 4'd1));
+                           bin_within_sf > (4'd15 - {1'b0, host_dc_notch_width} + 4'd1));
 
 // Notched Doppler data: zero I/Q when in notch zone, pass through otherwise
 wire [31:0] notched_doppler_data  = dc_notch_active ? 32'd0 : rx_doppler_output;
@@ -871,6 +897,19 @@ endgenerate
 // we simply sample them in clk_100m when the CDC'd pulse arrives.
 
 // Step 1: Toggle on cmd_valid pulse (ft601_clk domain)
+//
+// CDC INVARIANT (audit F-1.1): usb_cmd_opcode / usb_cmd_addr / usb_cmd_value
+// / usb_cmd_data MUST be driven to their final values BEFORE usb_cmd_valid
+// asserts, and held stable for at least (STAGES + 1) clk_100m cycles after
+// (i.e., until cmd_valid_100m has pulsed in the destination domain). These
+// buses cross from ft601_clk to clk_100m as quasi-static data, NOT through
+// a synchronizer — only the toggle bit above is CDC'd. If a future edit
+// moves the cmd_* register write to the SAME cycle as the toggle flip, or
+// drops the stability hold, the clk_100m sampler at the command decoder
+// will latch metastable bits and dispatch on a garbage opcode.
+// The source-side FSM in usb_data_interface_ft2232h.v / usb_data_interface.v
+// currently satisfies this by assigning the cmd_* buses several cycles
+// before pulsing cmd_valid and leaving them stable until the next command.
 reg cmd_valid_toggle_ft601;
 always @(posedge ft601_clk_buf or negedge sys_reset_ft601_n) begin
     if (!sys_reset_ft601_n)
@@ -959,19 +998,19 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
                 8'h13: host_short_chirp_cycles <= usb_cmd_value;
                 8'h14: host_short_listen_cycles <= usb_cmd_value;
                 8'h15: begin
-                    // Fix 4: Clamp chirps_per_elev to the fixed Doppler frame size.
+                    // Fix 4: Clamp chirps_per_elev to the fixed Doppler frame size.
-                    // If host requests a different value, clamp and set error flag.
+                    // If host requests a different value, clamp and set error flag.
-                    if (usb_cmd_value[5:0] > DOPPLER_FRAME_CHIRPS[5:0]) begin
+                    if (usb_cmd_value[5:0] > DOPPLER_FRAME_CHIRPS[5:0]) begin
-                        host_chirps_per_elev  <= DOPPLER_FRAME_CHIRPS[5:0];
+                        host_chirps_per_elev  <= DOPPLER_FRAME_CHIRPS[5:0];
-                        chirps_mismatch_error <= 1'b1;
+                        chirps_mismatch_error <= 1'b1;
-                    end else if (usb_cmd_value[5:0] == 6'd0) begin
+                    end else if (usb_cmd_value[5:0] == 6'd0) begin
-                        host_chirps_per_elev  <= DOPPLER_FRAME_CHIRPS[5:0];
+                        host_chirps_per_elev  <= DOPPLER_FRAME_CHIRPS[5:0];
-                        chirps_mismatch_error <= 1'b1;
+                        chirps_mismatch_error <= 1'b1;
-                    end else begin
+                    end else begin
-                        host_chirps_per_elev  <= usb_cmd_value[5:0];
+                        host_chirps_per_elev  <= usb_cmd_value[5:0];
-                        // Clear error only if value matches FFT size exactly
+                        // Clear error only if value matches FFT size exactly
-                        chirps_mismatch_error <= (usb_cmd_value[5:0] != DOPPLER_FRAME_CHIRPS[5:0]);
+                        chirps_mismatch_error <= (usb_cmd_value[5:0] != DOPPLER_FRAME_CHIRPS[5:0]);
-                    end
+                    end
                 end
                 8'h16: host_gain_shift         <= usb_cmd_value[3:0];  // Fix 3: digital gain
                 8'h20: host_range_mode         <= usb_cmd_value[1:0];  // Fix 7: range mode
@@ -1040,7 +1079,15 @@ assign system_status = status_reg;
 // DIG_6: AGC enable flag — mirrors host_agc_enable so STM32 outer-loop AGC
 //        tracks the FPGA register as single source of truth.
 // DIG_7: Reserved (tied low for future use).
-assign gpio_dig5 = (rx_agc_saturation_count != 8'd0);
+// gpio_dig5: "signal-chain clipped" — asserts on AGC saturation, DDC mixer/FIR
+// overflow, or MTI 2-pulse saturation. Audit F-6.1/F-6.3: these were all
+// previously invisible to the MCU.
+assign gpio_dig5 = (rx_agc_saturation_count != 8'd0)
+                 | rx_ddc_overflow_any
+                 | (rx_ddc_saturation_count != 3'd0)
+                 | (rx_mti_saturation_count != 8'd0)
+                 | rx_range_decim_watchdog    // audit F-6.4
+                 | rx_ddc_cic_fir_overrun;    // audit F-1.2
 assign gpio_dig6 = host_agc_enable;
 assign gpio_dig7 = 1'b0;
 
@@ -1075,4 +1122,4 @@ always @(posedge clk_100m_buf) begin
 end
 `endif
 
-endmodule
+endmodule

9_Firmware/9_2_FPGA/radar_system_top_50t.v

@@ -60,6 +60,8 @@ module radar_system_top_50t (
     input wire [7:0] adc_d_n,
     input wire adc_dco_p,
     input wire adc_dco_n,
+    input wire adc_or_p,
+    input wire adc_or_n,
     output wire adc_pwdn,
 
     // ===== STM32 Control (Bank 15: 3.3V) =====
@@ -171,6 +173,8 @@ module radar_system_top_50t (
         .adc_d_n                (adc_d_n),
         .adc_dco_p              (adc_dco_p),
         .adc_dco_n              (adc_dco_n),
+        .adc_or_p               (adc_or_p),
+        .adc_or_n               (adc_or_n),
         .adc_pwdn               (adc_pwdn),
 
         // ----- STM32 Control -----

9_Firmware/9_2_FPGA/radar_system_top_te0713_umft601x_dev.v

@@ -138,7 +138,12 @@ usb_data_interface usb_inst (
     .status_range_mode(2'b01),
     .status_self_test_flags(5'b11111),
     .status_self_test_detail(8'hA5),
-    .status_self_test_busy(1'b0)
+    .status_self_test_busy(1'b0),
+    // AGC status: tie off with benign defaults (no AGC on dev board)
+    .status_agc_current_gain(4'd0),
+    .status_agc_peak_magnitude(8'd0),
+    .status_agc_saturation_count(8'd0),
+    .status_agc_enable(1'b0)
 );
 
 endmodule

9_Firmware/9_2_FPGA/run_regression.sh

@@ -70,6 +70,7 @@ PROD_RTL=(
     xfft_16.v
     fft_engine.v
     usb_data_interface.v
+    usb_data_interface_ft2232h.v
     edge_detector.v
     radar_mode_controller.v
     rx_gain_control.v
@@ -86,6 +87,33 @@ EXTRA_RTL=(
     frequency_matched_filter.v
 )
 
+# ---------------------------------------------------------------------------
+# Shared RTL file lists for integration / system tests
+# Centralised here so a new module only needs adding once.
+# ---------------------------------------------------------------------------
+
+# Receiver chain (used by golden generate/compare tests)
+RECEIVER_RTL=(
+    radar_receiver_final.v
+    radar_mode_controller.v
+    tb/ad9484_interface_400m_stub.v
+    ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v
+    cdc_modules.v fir_lowpass.v ddc_input_interface.v
+    chirp_memory_loader_param.v latency_buffer.v
+    matched_filter_multi_segment.v matched_filter_processing_chain.v
+    range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v
+    rx_gain_control.v mti_canceller.v
+)
+
+# Full system top (receiver chain + TX + USB + detection + self-test)
+SYSTEM_RTL=(
+    radar_system_top.v
+    radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v
+    "${RECEIVER_RTL[@]}"
+    usb_data_interface.v usb_data_interface_ft2232h.v edge_detector.v
+    cfar_ca.v fpga_self_test.v
+)
+
 # ---- Layer A: iverilog -Wall compilation ----
 run_lint_iverilog() {
     local label="$1"
@@ -219,26 +247,9 @@ run_lint_static() {
         fi
     done
 
-    # --- Single-line regex checks across all production RTL ---
+    # CHECK 5 ($readmemh in synth code) and CHECK 6 (unused includes)
-    for f in "$@"; do
+    # require multi-line ifdef tracking / cross-file analysis. Not feasible
-        [[ -f "$f" ]] || continue
+    # with line-by-line regex. Omitted — use Vivado lint instead.
-        case "$f" in tb/*) continue ;; esac
-
-        local linenum=0
-        while IFS= read -r line; do
-            linenum=$((linenum + 1))
-
-            # CHECK 5: $readmemh / $readmemb in synthesizable code
-            # (Only valid in simulation blocks — flag if outside `ifdef SIMULATION)
-            # This is hard to check line-by-line without tracking ifdefs.
-            # Skip for v1.
-
-            # CHECK 6: Unused `include files (informational only)
-            # Skip for v1.
-
-            :  # placeholder — prevents empty loop body
-        done < "$f"
-    done
 
     if [[ "$err_count" -gt 0 ]]; then
         echo -e "${RED}FAIL${NC} ($err_count errors, $warn_count warnings)"
@@ -420,57 +431,36 @@ if [[ "$QUICK" -eq 0 ]]; then
     run_test "Receiver (golden generate)" \
         tb/tb_rx_golden_reg.vvp \
         -DGOLDEN_GENERATE \
-        tb/tb_radar_receiver_final.v radar_receiver_final.v \
+        tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
-        radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
-        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
-        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
-        chirp_memory_loader_param.v latency_buffer.v \
-        matched_filter_multi_segment.v matched_filter_processing_chain.v \
-        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
-        rx_gain_control.v mti_canceller.v
 
     # Golden compare
     run_test "Receiver (golden compare)" \
         tb/tb_rx_compare_reg.vvp \
-        tb/tb_radar_receiver_final.v radar_receiver_final.v \
+        tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
-        radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
-        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
-        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
-        chirp_memory_loader_param.v latency_buffer.v \
-        matched_filter_multi_segment.v matched_filter_processing_chain.v \
-        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
-        rx_gain_control.v mti_canceller.v
 
     # Full system top (monitoring-only, legacy)
     run_test "System Top (radar_system_tb)" \
         tb/tb_system_reg.vvp \
-        tb/radar_system_tb.v radar_system_top.v \
+        tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
-        radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v \
-        radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
-        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
-        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
-        chirp_memory_loader_param.v latency_buffer.v \
-        matched_filter_multi_segment.v matched_filter_processing_chain.v \
-        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
-        usb_data_interface.v edge_detector.v radar_mode_controller.v \
-        rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
 
     # E2E integration (46 strict checks: TX, RX, USB R/W, CDC, safety, reset)
     run_test "System E2E (tb_system_e2e)" \
         tb/tb_system_e2e_reg.vvp \
-        tb/tb_system_e2e.v radar_system_top.v \
+        tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
-        radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v \
+
-        radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
+    # USB_MODE=1 (FT2232H production) variants of system tests
-        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
+    run_test "System Top USB_MODE=1 (FT2232H)" \
-        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
+        tb/tb_system_ft2232h_reg.vvp \
-        chirp_memory_loader_param.v latency_buffer.v \
+        -DUSB_MODE_1 \
-        matched_filter_multi_segment.v matched_filter_processing_chain.v \
+        tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
-        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
+
-        usb_data_interface.v edge_detector.v radar_mode_controller.v \
+    run_test "System E2E USB_MODE=1 (FT2232H)" \
-        rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
+        tb/tb_system_e2e_ft2232h_reg.vvp \
+        -DUSB_MODE_1 \
+        tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
 else
     echo "  (skipped receiver golden + system top + E2E — use without --quick)"
-    SKIP=$((SKIP + 4))
+    SKIP=$((SKIP + 6))
 fi
 
 echo ""

9_Firmware/9_2_FPGA/scripts/200t/build_200t.tcl

@@ -108,6 +108,9 @@ add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "
 
 set_property top $top_module [current_fileset]
 set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
+# Override USB_MODE to 0 (FT601) for 200T premium board.
+# The RTL default is USB_MODE=1 (FT2232H, production 50T).
+set_property generic {USB_MODE=0} [current_fileset]
 
 # ==============================================================================
 # 2. Synthesis

9_Firmware/9_2_FPGA/tb/ad9484_interface_400m_stub.v

@@ -19,6 +19,10 @@ module ad9484_interface_400m (
     input wire [7:0] adc_d_n,
     input wire adc_dco_p,
     input wire adc_dco_n,
+    // Audit F-0.1: AD9484 OR (overrange) LVDS pair — stub treats adc_or_p as
+    // the single-ended overrange flag, adc_or_n is ignored.
+    input wire adc_or_p,
+    input wire adc_or_n,
 
     // System Interface
     input wire sys_clk,
@@ -27,7 +31,8 @@ module ad9484_interface_400m (
     // Output at 400MHz domain
     output wire [7:0] adc_data_400m,
     output wire adc_data_valid_400m,
-    output wire adc_dco_bufg
+    output wire adc_dco_bufg,
+    output wire adc_overrange_400m
 );
 
 // Pass-through clock (no BUFG needed in simulation)
@@ -50,4 +55,15 @@ end
 assign adc_data_400m = adc_data_400m_reg;
 assign adc_data_valid_400m = adc_data_valid_400m_reg;
 
+// Audit F-0.1: 1-cycle pipeline of adc_or_p to match the real IDDR+register
+// capture path. TB drives adc_or_p directly with the overrange flag.
+reg adc_overrange_400m_reg;
+always @(posedge adc_dco_p or negedge reset_n) begin
+    if (!reset_n)
+        adc_overrange_400m_reg <= 1'b0;
+    else
+        adc_overrange_400m_reg <= adc_or_p;
+end
+assign adc_overrange_400m = adc_overrange_400m_reg;
+
 endmodule

9_Firmware/9_2_FPGA/tb/radar_system_tb.v

@@ -430,7 +430,13 @@ end
 // DUT INSTANTIATION
 // ============================================================================
 
-radar_system_top dut (
+radar_system_top #(
+`ifdef USB_MODE_1
+    .USB_MODE(1)  // FT2232H interface (production 50T board)
+`else
+    .USB_MODE(0)  // FT601 interface (200T dev board)
+`endif
+) dut (
     // System Clocks
     .clk_100m(clk_100m),
     .clk_120m_dac(clk_120m_dac),
@@ -481,6 +487,8 @@ radar_system_top dut (
     .adc_d_n(adc_d_n),
     .adc_dco_p(adc_dco_p),
     .adc_dco_n(adc_dco_n),
+    .adc_or_p(1'b0),
+    .adc_or_n(1'b1),
     .adc_pwdn(adc_pwdn),
     
     // STM32 Control
@@ -619,7 +627,11 @@ initial begin
     // Optional: dump specific signals for debugging
     $dumpvars(1, dut.tx_inst);
     $dumpvars(1, dut.rx_inst);
+    `ifdef USB_MODE_1
+    $dumpvars(1, dut.gen_ft2232h.usb_inst);
+    `else
     $dumpvars(1, dut.gen_ft601.usb_inst);
+    `endif
 end
 
 endmodule

9_Firmware/9_2_FPGA/tb/tb_ddc_cosim.v

@@ -64,9 +64,11 @@ module tb_ddc_cosim;
 
     // Scenario selector (set via +define)
     reg [255:0] scenario_name;
-    reg [1023:0] hex_file_path;
+    // Widened to 4 kbits (512 bytes) so fuzz-runner temp paths
-    reg [1023:0] csv_out_path;
+    // (e.g. /private/var/folders/.../pytest-of-...) fit without MSB truncation.
-    reg [1023:0] csv_cic_path;
+    reg [4095:0] hex_file_path;
+    reg [4095:0] csv_out_path;
+    reg [4095:0] csv_cic_path;
 
     // ── Clock generation ──────────────────────────────────────
     // 400 MHz clock
@@ -152,7 +154,16 @@ module tb_ddc_cosim;
         // ── Select scenario ───────────────────────────────────
         // Default to DC scenario for fastest validation
         // Override with: +define+SCENARIO_SINGLE, +define+SCENARIO_MULTI, etc.
-        `ifdef SCENARIO_SINGLE
+        `ifdef SCENARIO_FUZZ
+            // Audit F-3.2: fuzz runner provides +hex and +csv paths plus a
+            // scenario tag. Any missing plusarg falls back to the DC vector.
+            if (!$value$plusargs("hex=%s", hex_file_path))
+                hex_file_path = "tb/cosim/adc_dc.hex";
+            if (!$value$plusargs("csv=%s", csv_out_path))
+                csv_out_path  = "tb/cosim/rtl_bb_fuzz.csv";
+            if (!$value$plusargs("tag=%s", scenario_name))
+                scenario_name = "fuzz";
+        `elsif SCENARIO_SINGLE
             hex_file_path = "tb/cosim/adc_single_target.hex";
             csv_out_path  = "tb/cosim/rtl_bb_single_target.csv";
             scenario_name = "single_target";

9_Firmware/9_2_FPGA/tb/tb_radar_receiver_final.v

@@ -139,6 +139,8 @@ radar_receiver_final dut (
     // ADC "LVDS" -- stub treats adc_d_p as single-ended data
     .adc_d_p(adc_data),
     .adc_d_n(~adc_data),       // Complement (ignored by stub)
+    .adc_or_p(1'b0),           // F-0.1: no overrange stimulus in this TB
+    .adc_or_n(1'b1),
     .adc_dco_p(clk_400m),      // 400 MHz clock
     .adc_dco_n(~clk_400m),     // Complement (ignored by stub)
     .adc_pwdn(),

9_Firmware/9_2_FPGA/tb/tb_system_e2e.v

@@ -382,7 +382,13 @@ end
 // ============================================================================
 // DUT INSTANTIATION
 // ============================================================================
-radar_system_top dut (
+radar_system_top #(
+`ifdef USB_MODE_1
+    .USB_MODE(1)  // FT2232H interface (production 50T board)
+`else
+    .USB_MODE(0)  // FT601 interface (200T dev board)
+`endif
+) dut (
     .clk_100m(clk_100m),
     .clk_120m_dac(clk_120m_dac),
     .ft601_clk_in(ft601_clk_in),
@@ -421,6 +427,8 @@ radar_system_top dut (
     .adc_d_n(adc_d_n),
     .adc_dco_p(adc_dco_p),
     .adc_dco_n(adc_dco_n),
+    .adc_or_p(1'b0),
+    .adc_or_n(1'b1),
     .adc_pwdn(adc_pwdn),
 
     .stm32_new_chirp(stm32_new_chirp),
@@ -554,10 +562,10 @@ initial begin
     do_reset;
 
     // CRITICAL: Configure stream control to range-only BEFORE any chirps
-    // fire. The USB write FSM blocks on doppler_valid_ft if doppler stream
+    // fire. The USB write FSM gates on pending flags: if doppler stream is
-    // is enabled but no Doppler data arrives (needs 32 chirps/frame).
+    // enabled but no Doppler data arrives (needs 32 chirps/frame), the FSM
-    // Without this, the write FSM deadlocks and the read FSM can never
+    // stays in IDLE waiting for doppler_data_pending. With the write FSM
-    // activate (it requires write FSM == IDLE).
+    // not in IDLE, the read FSM cannot activate (bus arbitration rule).
     bfm_send_cmd(8'h04, 8'h00, 16'h0001);  // stream_control = range only
     // Wait for stream_control CDC to propagate (2-stage sync in ft601_clk)
     // Must be long enough that stream_ctrl_sync_1 is updated before any
@@ -778,7 +786,7 @@ initial begin
 
     // Restore defaults for subsequent tests
     bfm_send_cmd(8'h01, 8'h00, 16'h0001);  // mode = auto-scan
-    bfm_send_cmd(8'h04, 8'h00, 16'h0001);  // keep range-only (prevents write FSM deadlock)
+    bfm_send_cmd(8'h04, 8'h00, 16'h0001);  // keep range-only (TB lacks 32-chirp doppler data)
     bfm_send_cmd(8'h10, 8'h00, 16'd3000);  // restore long chirp cycles
 
     $display("");
@@ -913,7 +921,7 @@ initial begin
     // Need to re-send configuration since reset clears all registers
     stm32_mixers_enable = 1;
     ft601_txe = 0;
-    bfm_send_cmd(8'h04, 8'h00, 16'h0001);  // stream_control = range only (prevent deadlock)
+    bfm_send_cmd(8'h04, 8'h00, 16'h0001);  // stream_control = range only (TB lacks doppler data)
     #500;  // Wait for stream_control CDC
     bfm_send_cmd(8'h01, 8'h00, 16'h0001);  // auto-scan
     bfm_send_cmd(8'h10, 8'h00, 16'd100);   // short timing
@@ -932,6 +940,106 @@ initial begin
 
     $display("");
 
+    // ================================================================
+    // GROUP 9B: Adversarial reset sweep (audit F-2.2)
+    // ================================================================
+    // Drive the same auto-scan pipeline, then inject reset at four distinct
+    // offsets relative to a known-good start of operation. For each offset
+    // the system must:
+    //   (a) present system_status == 0 while held in reset
+    //   (b) produce at least one additional new_chirp_frame within the
+    //       observation window after reset release
+    //   (c) advance obs_range_valid_count (confirms full DDC+MF chain resumes)
+    // The four offsets are chosen to hit mid-chirp, mid-listen, and around
+    // the short/long chirp boundary, which covers the interesting FSM and
+    // CDC transitions in the pipeline.
+    $display("--- Group 9B: Adversarial reset sweep (F-2.2) ---");
+    begin : reset_sweep
+        integer sweep_i;
+        integer sweep_baseline_range;
+        integer sweep_baseline_chirp;
+        integer sweep_offsets [0:3];
+        integer sweep_holds   [0:3];
+        reg     sweep_ok;
+
+        // Reset injection offsets (ns) after the last auto-scan reconfigure.
+        // 3 us / 7 us / 12 us / 18 us — sprayed across a short-chirp burst.
+        sweep_offsets[0] = 3000;
+        sweep_offsets[1] = 7000;
+        sweep_offsets[2] = 12000;
+        sweep_offsets[3] = 18000;
+        // Reset-assert durations mix short (~20 clk_100m) and long (~120)
+        sweep_holds[0] = 200;
+        sweep_holds[1] = 1200;
+        sweep_holds[2] = 400;
+        sweep_holds[3] = 800;
+
+        for (sweep_i = 0; sweep_i < 4; sweep_i = sweep_i + 1) begin
+            // Re-seed auto-scan from a clean base each iteration
+            reset_n = 0;
+            bfm_rx_wr_ptr = 0;
+            bfm_rx_rd_ptr = 0;
+            #200;
+            reset_n = 1;
+            #500;
+            stm32_mixers_enable = 1;
+            ft601_txe = 0;
+            bfm_send_cmd(8'h04, 8'h00, 16'h0001);
+            #500;
+            bfm_send_cmd(8'h01, 8'h00, 16'h0001);
+            bfm_send_cmd(8'h10, 8'h00, 16'd100);
+            bfm_send_cmd(8'h11, 8'h00, 16'd200);
+            bfm_send_cmd(8'h12, 8'h00, 16'd100);
+            bfm_send_cmd(8'h13, 8'h00, 16'd20);
+            bfm_send_cmd(8'h14, 8'h00, 16'd100);
+            bfm_send_cmd(8'h15, 8'h00, 16'd4);
+
+            // Let the pipeline reach steady-state and capture a baseline
+            #30000;
+            sweep_baseline_range = obs_range_valid_count;
+            sweep_baseline_chirp = obs_chirp_frame_count;
+
+            // Wait out the configured offset, then assert reset asynchronously
+            #(sweep_offsets[sweep_i]);
+            reset_n = 0;
+            #(sweep_holds[sweep_i]);
+            sweep_ok = (system_status == 4'b0000);
+            check(sweep_ok,
+                  "G9B.a: system_status drops to 0 during injected reset");
+
+            // Release reset, re-configure (regs are cleared), allow recovery
+            reset_n = 1;
+            #500;
+            stm32_mixers_enable = 1;
+            ft601_txe = 0;
+            bfm_send_cmd(8'h04, 8'h00, 16'h0001);
+            #500;
+            bfm_send_cmd(8'h01, 8'h00, 16'h0001);
+            bfm_send_cmd(8'h10, 8'h00, 16'd100);
+            bfm_send_cmd(8'h11, 8'h00, 16'd200);
+            bfm_send_cmd(8'h12, 8'h00, 16'd100);
+            bfm_send_cmd(8'h13, 8'h00, 16'd20);
+            bfm_send_cmd(8'h14, 8'h00, 16'd100);
+            bfm_send_cmd(8'h15, 8'h00, 16'd4);
+
+            sweep_baseline_range = obs_range_valid_count;
+            sweep_baseline_chirp = obs_chirp_frame_count;
+            #60000;   // 60 us — two+ short-chirp frames
+
+            check(obs_chirp_frame_count > sweep_baseline_chirp,
+                  "G9B.b: new_chirp_frame resumes after injected reset");
+            check(obs_range_valid_count > sweep_baseline_range,
+                  "G9B.c: range pipeline resumes after injected reset");
+
+            $display("  [F-2.2] iter=%0d offset=%0dns hold=%0dns chirps=+%0d ranges=+%0d",
+                     sweep_i, sweep_offsets[sweep_i], sweep_holds[sweep_i],
+                     obs_chirp_frame_count - sweep_baseline_chirp,
+                     obs_range_valid_count - sweep_baseline_range);
+        end
+    end
+
+    $display("");
+
     // ================================================================
     // GROUP 10: STREAM CONTROL (Gap 2)
     // ================================================================
@@ -947,7 +1055,7 @@ initial begin
     check(dut.host_stream_control == 3'b000,
           "G10.2: All streams disabled (stream_control = 3'b000)");
 
-    // G10.3: Re-enable range only (keep range-only to prevent write FSM deadlock)
+    // G10.3: Re-enable range only (TB uses range-only — no doppler processing)
     bfm_send_cmd(8'h04, 8'h00, 16'h0001);  // stream_control = 3'b001
     check(dut.host_stream_control == 3'b001,
           "G10.3: Range stream re-enabled (stream_control = 3'b001)");

9_Firmware/9_2_FPGA/tb/tb_usb_data_interface.v

@@ -6,15 +6,11 @@ module tb_usb_data_interface;
     localparam CLK_PERIOD     = 10.0;  // 100 MHz main clock
     localparam FT_CLK_PERIOD  = 10.0;  // 100 MHz FT601 clock (asynchronous)
 
-    // State definitions (mirror the DUT)
+    // State definitions (mirror the DUT — 4-state packed-word FSM)
-    localparam [2:0] S_IDLE           = 3'd0,
+    localparam [3:0] S_IDLE           = 4'd0,
-                     S_SEND_HEADER    = 3'd1,
+                     S_SEND_DATA_WORD = 4'd1,
-                     S_SEND_RANGE     = 3'd2,
+                     S_SEND_STATUS    = 4'd2,
-                     S_SEND_DOPPLER   = 3'd3,
+                     S_WAIT_ACK       = 4'd3;
-                     S_SEND_DETECT    = 3'd4,
-                     S_SEND_FOOTER    = 3'd5,
-                     S_WAIT_ACK       = 3'd6,
-                     S_SEND_STATUS    = 3'd7;  // Gap 2: status readback
 
     // ── Signals ────────────────────────────────────────────────
     reg         clk;
@@ -219,9 +215,9 @@ module tb_usb_data_interface;
         end
     endtask
 
-    // ── Helper: wait for DUT to reach a specific state ─────────
+    // ── Helper: wait for DUT to reach a specific write FSM state ──
     task wait_for_state;
-        input [2:0] target;
+        input [3:0] target;
         input integer max_cyc;
         integer cnt;
         begin
@@ -280,7 +276,7 @@ module tb_usb_data_interface;
     // Set data_pending flags directly via hierarchical access.
     // This is the standard TB technique for internal state setup —
     // bypasses the CDC path for immediate, reliable flag setting.
-    // Call BEFORE assert_range_valid in tests that need SEND_DOPPLER/DETECT.
+    // Call BEFORE assert_range_valid in tests that need doppler/cfar data.
     task preload_pending_data;
         begin
             @(posedge ft601_clk_in);
@@ -354,24 +350,26 @@ module tb_usb_data_interface;
         end
     endtask
 
-    // Drive a complete packet through the FSM by sequentially providing
+    // Drive a complete data packet through the new 3-word packed FSM.
-    // range, doppler (4x), and cfar valid pulses.
+    // Pre-loads pending flags, triggers range_valid, and waits for IDLE.
+    // With the new FSM, all data is pre-packed in IDLE then sent as 3 words.
     task drive_full_packet;
         input [31:0] rng;
         input [15:0] dr;
         input [15:0] di;
         input        det;
         begin
-            // Pre-load pending flags so FSM enters doppler/cfar states
+            // Set doppler/cfar captured values via CDC inputs
+            @(posedge clk);
+            doppler_real   = dr;
+            doppler_imag   = di;
+            cfar_detection = det;
+            @(posedge clk);
+            // Pre-load pending flags so FSM includes doppler/cfar in packet
             preload_pending_data;
+            // Trigger the packet
             assert_range_valid(rng);
-            wait_for_state(S_SEND_DOPPLER, 100);
+            // Wait for complete packet cycle: IDLE → SEND_DATA_WORD(×3) → WAIT_ACK → IDLE
-            pulse_doppler_once(dr, di);
-            pulse_doppler_once(dr, di);
-            pulse_doppler_once(dr, di);
-            pulse_doppler_once(dr, di);
-            wait_for_state(S_SEND_DETECT, 100);
-            pulse_cfar_once(det);
             wait_for_state(S_IDLE, 100);
         end
     endtask
@@ -414,101 +412,138 @@ module tb_usb_data_interface;
               "ft601_siwu_n=1 after reset");
 
         // ════════════════════════════════════════════════════════
-        // TEST GROUP 2: Range data packet
+        // TEST GROUP 2: Data packet word packing
         //
-        // Use backpressure to freeze the FSM at specific states
+        // New FSM packs 11-byte data into 3 × 32-bit words:
-        // so we can reliably sample outputs.
+        //   Word 0: {HEADER, range[31:24], range[23:16], range[15:8]}
+        //   Word 1: {range[7:0], dop_re_hi, dop_re_lo, dop_im_hi}
+        //   Word 2: {dop_im_lo, detection, FOOTER, 0x00}  BE=1110
+        //
+        // The DUT uses range_data_ready (1-cycle delayed range_valid_ft)
+        // to trigger packing.  Doppler/CFAR _cap registers must be
+        // pre-loaded via hierarchical access because no valid pulse is
+        // given in this test (we only want to verify packing, not CDC).
         // ════════════════════════════════════════════════════════
-        $display("\n--- Test Group 2: Range Data Packet ---");
+        $display("\n--- Test Group 2: Data Packet Word Packing ---");
         apply_reset;
+        ft601_txe = 1;  // Stall so we can inspect packed words
 
-        // Stall at SEND_HEADER so we can verify first range word later
+        // Set known doppler/cfar values on clk-domain inputs
-        ft601_txe = 1;
+        @(posedge clk);
+        doppler_real   = 16'hABCD;
+        doppler_imag   = 16'hEF01;
+        cfar_detection = 1'b1;
+        @(posedge clk);
+
+        // Pre-load pending flags AND captured-data registers directly.
+        // No doppler/cfar valid pulses are given, so the CDC capture path
+        // never fires — we must set the _cap registers via hierarchical
+        // access for the word-packing checks to be meaningful.
         preload_pending_data;
+        @(posedge ft601_clk_in);
+        uut.doppler_real_cap   = 16'hABCD;
+        uut.doppler_imag_cap   = 16'hEF01;
+        uut.cfar_detection_cap = 1'b1;
+        @(posedge ft601_clk_in);
+
         assert_range_valid(32'hDEAD_BEEF);
-        wait_for_state(S_SEND_HEADER, 50);
-        repeat (2) @(posedge ft601_clk_in); #1;
-        check(uut.current_state === S_SEND_HEADER,
-              "Stalled in SEND_HEADER (backpressure)");
 
-        // Release: FSM drives header then moves to SEND_RANGE_DATA
+        // FSM should be in SEND_DATA_WORD, stalled on ft601_txe=1
+        wait_for_state(S_SEND_DATA_WORD, 50);
+        repeat (2) @(posedge ft601_clk_in); #1;
+
+        check(uut.current_state === S_SEND_DATA_WORD,
+              "Stalled in SEND_DATA_WORD (backpressure)");
+
+        // Verify pre-packed words
+        // range_profile = 0xDEAD_BEEF → range[31:24]=0xDE, [23:16]=0xAD, [15:8]=0xBE, [7:0]=0xEF
+        // Word 0: {0xAA, 0xDE, 0xAD, 0xBE}
+        check(uut.data_pkt_word0 === {8'hAA, 8'hDE, 8'hAD, 8'hBE},
+              "Word 0: {HEADER=AA, range[31:8]}");
+        // Word 1: {0xEF, 0xAB, 0xCD, 0xEF}
+        check(uut.data_pkt_word1 === {8'hEF, 8'hAB, 8'hCD, 8'hEF},
+              "Word 1: {range[7:0], dop_re, dop_im_hi}");
+        // Word 2: {0x01, detection_byte, 0x55, 0x00}
+        // detection_byte bit 7 = frame_start (sample_counter==0 → 1), bit 0 = cfar=1
+        // so detection_byte = 8'b1000_0001 = 8'h81
+        check(uut.data_pkt_word2 === {8'h01, 8'h81, 8'h55, 8'h00},
+              "Word 2: {dop_im_lo, det=81, FOOTER=55, pad=00}");
+        check(uut.data_pkt_be2 === 4'b1110,
+              "Word 2 BE=1110 (3 valid bytes + 1 pad)");
+
+        // Release backpressure and verify word 0 appears on bus.
+        // On the first posedge with !ft601_txe the FSM drives word 0 and
+        // advances data_word_idx 0→1 via NBA.  After #1 the NBA has
+        // resolved, so we see idx=1 and ft601_data_out=word0.
         ft601_txe = 0;
         @(posedge ft601_clk_in); #1;
-        // Now the FSM registered the header output and will transition
-        // At the NEXT posedge the state becomes SEND_RANGE_DATA
-        @(posedge ft601_clk_in); #1;
-
-        check(uut.current_state === S_SEND_RANGE,
-              "Entered SEND_RANGE_DATA after header");
-
-        // The first range word should be on the data bus (byte_counter=0 just
-        // drove range_profile_cap, byte_counter incremented to 1)
-        check(uut.ft601_data_out === 32'hDEAD_BEEF || uut.byte_counter <= 8'd1,
-              "Range data word 0 driven (range_profile_cap)");
 
+        check(uut.ft601_data_out === {8'hAA, 8'hDE, 8'hAD, 8'hBE},
+              "Word 0 driven on data bus after backpressure release");
         check(ft601_wr_n === 1'b0,
-              "Write strobe active during range data");
+              "Write strobe active during SEND_DATA_WORD");
-
         check(ft601_be === 4'b1111,
-              "Byte enable=1111 for range data");
+              "Byte enable=1111 for word 0");
+        check(uut.ft601_data_oe === 1'b1,
+              "Data bus output enabled during SEND_DATA_WORD");
 
-        // Wait for all 4 range words to complete
+        // Next posedge: FSM drives word 1, advances idx 1→2.
-        wait_for_state(S_SEND_DOPPLER, 50);
+        // After NBA: idx=2, ft601_data_out=word1.
-        #1;
+        @(posedge ft601_clk_in); #1;
-        check(uut.current_state === S_SEND_DOPPLER,
+        check(uut.data_word_idx === 2'd2,
-              "Advanced to SEND_DOPPLER_DATA after 4 range words");
+              "data_word_idx advanced past word 1 (now 2)");
+        check(uut.ft601_data_out === {8'hEF, 8'hAB, 8'hCD, 8'hEF},
+              "Word 1 driven on data bus");
+        check(ft601_be === 4'b1111,
+              "Byte enable=1111 for word 1");
+
+        // Next posedge: FSM drives word 2, idx resets 2→0,
+        // and current_state transitions to WAIT_ACK.
+        @(posedge ft601_clk_in); #1;
+        check(uut.current_state === S_WAIT_ACK,
+              "Transitioned to WAIT_ACK after 3 data words");
+        check(uut.ft601_data_out === {8'h01, 8'h81, 8'h55, 8'h00},
+              "Word 2 driven on data bus");
+        check(ft601_be === 4'b1110,
+              "Byte enable=1110 for word 2 (last byte is pad)");
+
+        // Then back to IDLE
+        @(posedge ft601_clk_in); #1;
+        check(uut.current_state === S_IDLE,
+              "Returned to IDLE after WAIT_ACK");
 
         // ════════════════════════════════════════════════════════
-        // TEST GROUP 3: Header verification (stall to observe)
+        // TEST GROUP 3: Header and footer verification
         // ════════════════════════════════════════════════════════
-        $display("\n--- Test Group 3: Header Verification ---");
+        $display("\n--- Test Group 3: Header and Footer Verification ---");
         apply_reset;
-        ft601_txe = 1;  // Stall at SEND_HEADER
+        ft601_txe = 1;  // Stall to inspect
 
         @(posedge clk);
-        range_profile = 32'hCAFE_BABE;
+        doppler_real   = 16'h0000;
-        range_valid   = 1;
+        doppler_imag   = 16'h0000;
-        repeat (4) @(posedge ft601_clk_in);
+        cfar_detection = 1'b0;
         @(posedge clk);
-        range_valid = 0;
+        preload_pending_data;
-        repeat (3) @(posedge ft601_clk_in);
+        assert_range_valid(32'hCAFE_BABE);
 
-        wait_for_state(S_SEND_HEADER, 50);
+        wait_for_state(S_SEND_DATA_WORD, 50);
         repeat (2) @(posedge ft601_clk_in); #1;
 
-        check(uut.current_state === S_SEND_HEADER,
+        // Header is in byte 3 (MSB) of word 0
-              "Stalled in SEND_HEADER with backpressure");
+        check(uut.data_pkt_word0[31:24] === 8'hAA,
-
+              "Header byte 0xAA in word 0 MSB");
-        // Release backpressure - header will be latched at next posedge
+        // Footer is in byte 1 (bits [15:8]) of word 2
-        ft601_txe = 0;
+        check(uut.data_pkt_word2[15:8] === 8'h55,
-        @(posedge ft601_clk_in); #1;
+              "Footer byte 0x55 in word 2");
-
-        check(uut.ft601_data_out[7:0] === 8'hAA,
-              "Header byte 0xAA on data bus");
-        check(ft601_be === 4'b0001,
-              "Byte enable=0001 for header (lower byte only)");
-        check(ft601_wr_n === 1'b0,
-              "Write strobe active during header");
-        check(uut.ft601_data_oe === 1'b1,
-              "Data bus output enabled during header");
 
         // ════════════════════════════════════════════════════════
-        // TEST GROUP 4: Doppler data verification
+        // TEST GROUP 4: Doppler data capture verification
         // ════════════════════════════════════════════════════════
-        $display("\n--- Test Group 4: Doppler Data Verification ---");
+        $display("\n--- Test Group 4: Doppler Data Capture ---");
         apply_reset;
         ft601_txe = 0;
 
-        // Preload only doppler pending (not cfar) so the FSM sends
-        // doppler data. After doppler, SEND_DETECT sees cfar_data_pending=0
-        // and skips to SEND_FOOTER, then WAIT_ACK, then IDLE.
-        preload_doppler_pending;
-        assert_range_valid(32'h0000_0001);
-        wait_for_state(S_SEND_DOPPLER, 100);
-        #1;
-        check(uut.current_state === S_SEND_DOPPLER,
-              "Reached SEND_DOPPLER_DATA");
-
         // Provide doppler data via valid pulse (updates captured values)
         @(posedge clk);
         doppler_real  = 16'hAAAA;
@@ -524,110 +559,70 @@ module tb_usb_data_interface;
         check(uut.doppler_imag_cap === 16'h5555,
               "doppler_imag captured correctly");
 
-        // The FSM has doppler_data_pending set and sends 4 bytes, then
+        // Drive a packet with pending doppler + cfar (both needed for gating
-        // transitions past SEND_DETECT (cfar_data_pending=0) to IDLE.
+        // since all streams are enabled after reset/apply_reset).
+        preload_pending_data;
+        assert_range_valid(32'h0000_0001);
         wait_for_state(S_IDLE, 100);
         #1;
         check(uut.current_state === S_IDLE,
-              "Doppler done, packet completed");
+              "Packet completed with doppler data");
+        check(uut.doppler_data_pending === 1'b0,
+              "doppler_data_pending cleared after packet");
 
         // ════════════════════════════════════════════════════════
         // TEST GROUP 5: CFAR detection data
         // ════════════════════════════════════════════════════════
         $display("\n--- Test Group 5: CFAR Detection Data ---");
-        // Start a new packet with both doppler and cfar pending to verify
-        // cfar data is properly sent in SEND_DETECTION_DATA.
         apply_reset;
         ft601_txe = 0;
         preload_pending_data;
         assert_range_valid(32'h0000_0002);
-        // FSM races through: HEADER -> RANGE -> DOPPLER -> DETECT -> FOOTER -> IDLE
-        // All pending flags consumed proves SEND_DETECT was entered.
         wait_for_state(S_IDLE, 200);
         #1;
         check(uut.cfar_data_pending === 1'b0,
-              "Starting in SEND_DETECTION_DATA");
+              "cfar_data_pending cleared after packet");
-
-        // Verify the full packet completed with cfar data consumed
         check(uut.current_state === S_IDLE &&
               uut.doppler_data_pending === 1'b0 &&
               uut.cfar_data_pending === 1'b0,
-              "CFAR detection sent, FSM advanced past SEND_DETECTION_DATA");
+              "CFAR detection sent, all pending flags cleared");
 
         // ════════════════════════════════════════════════════════
-        // TEST GROUP 6: Footer check
+        // TEST GROUP 6: Footer retained after packet
-        //
-        // Strategy: drive packet with ft601_txe=0 all the way through.
-        // The SEND_FOOTER state is only active for 1 cycle, but we can
-        // poll the state machine at each ft601_clk_in edge to observe
-        // it. We use a monitor-style approach: run the packet and
-        // capture what ft601_data_out contains when we see SEND_FOOTER.
         // ════════════════════════════════════════════════════════
-        $display("\n--- Test Group 6: Footer Check ---");
+        $display("\n--- Test Group 6: Footer Retention ---");
         apply_reset;
         ft601_txe = 0;
 
-        // Drive packet through range data
+        @(posedge clk);
+        cfar_detection = 1'b1;
+        @(posedge clk);
         preload_pending_data;
         assert_range_valid(32'hFACE_FEED);
-        wait_for_state(S_SEND_DOPPLER, 100);
-        // Feed doppler data (need 4 pulses)
-        pulse_doppler_once(16'h1111, 16'h2222);
-        pulse_doppler_once(16'h1111, 16'h2222);
-        pulse_doppler_once(16'h1111, 16'h2222);
-        pulse_doppler_once(16'h1111, 16'h2222);
-        wait_for_state(S_SEND_DETECT, 100);
-        // Feed cfar data, but keep ft601_txe=0 so it flows through
-        pulse_cfar_once(1'b1);
-
-        // Now the FSM should pass through SEND_FOOTER quickly.
-        // Use wait_for_state to reach SEND_FOOTER, or it may already
-        // be at WAIT_ACK/IDLE. Let's catch WAIT_ACK or IDLE.
-        // The footer values are latched into registers, so we can
-        // verify them even after the state transitions.
-        // Key verification: the FOOTER constant (0x55) must have been
-        // driven. We check this by looking at the constant definition.
-        // Since we can't easily freeze the FSM at SEND_FOOTER without
-        // also stalling SEND_DETECTION_DATA (both check ft601_txe),
-        // we verify the footer indirectly:
-        // 1. The packet completed (reached IDLE/WAIT_ACK)
-        // 2. ft601_data_out last held 0x55 during SEND_FOOTER
-
         wait_for_state(S_IDLE, 100);
         #1;
-        // If we reached IDLE, the full sequence ran including footer
         check(uut.current_state === S_IDLE,
               "Full packet incl. footer completed, back in IDLE");
 
-        // The registered ft601_data_out should still hold 0x55 from
+        // The last word driven was word 2 which contains footer 0x55.
-        // SEND_FOOTER (WAIT_ACK and IDLE don't overwrite ft601_data_out).
+        // WAIT_ACK and IDLE don't overwrite ft601_data_out, so it retains
-        // Actually, looking at the DUT: WAIT_ACK only sets wr_n=1 and
+        // the last driven value.
-        // data_oe=0, it doesn't change ft601_data_out. So it retains 0x55.
+        check(uut.ft601_data_out[15:8] === 8'h55,
-        check(uut.ft601_data_out[7:0] === 8'h55,
+              "ft601_data_out retains footer 0x55 in word 2 position");
-              "ft601_data_out retains footer 0x55 after packet");
 
-        // Verify WAIT_ACK behavior by doing another packet and catching it
+        // Verify WAIT_ACK → IDLE transition
         apply_reset;
         ft601_txe = 0;
         preload_pending_data;
         assert_range_valid(32'h1234_5678);
-        wait_for_state(S_SEND_DOPPLER, 100);
-        pulse_doppler_once(16'hABCD, 16'hEF01);
-        pulse_doppler_once(16'hABCD, 16'hEF01);
-        pulse_doppler_once(16'hABCD, 16'hEF01);
-        pulse_doppler_once(16'hABCD, 16'hEF01);
-        wait_for_state(S_SEND_DETECT, 100);
-        pulse_cfar_once(1'b0);
-        // WAIT_ACK lasts exactly 1 ft601_clk_in cycle then goes IDLE.
-        // Poll for IDLE (which means WAIT_ACK already happened).
         wait_for_state(S_IDLE, 100);
         #1;
         check(uut.current_state === S_IDLE,
               "Returned to IDLE after WAIT_ACK");
         check(ft601_wr_n === 1'b1,
-              "ft601_wr_n deasserted in IDLE (was deasserted in WAIT_ACK)");
+              "ft601_wr_n deasserted in IDLE");
         check(uut.ft601_data_oe === 1'b0,
-              "Data bus released in IDLE (was released in WAIT_ACK)");
+              "Data bus released in IDLE");
 
         // ════════════════════════════════════════════════════════
         // TEST GROUP 7: Full packet sequence (end-to-end)
@@ -646,23 +641,24 @@ module tb_usb_data_interface;
         // ════════════════════════════════════════════════════════
         $display("\n--- Test Group 8: FIFO Backpressure ---");
         apply_reset;
-        ft601_txe = 1;
+        ft601_txe = 1;  // FIFO full — stall
 
+        preload_pending_data;
         assert_range_valid(32'hBBBB_CCCC);
 
-        wait_for_state(S_SEND_HEADER, 50);
+        wait_for_state(S_SEND_DATA_WORD, 50);
         repeat (10) @(posedge ft601_clk_in); #1;
 
-        check(uut.current_state === S_SEND_HEADER,
+        check(uut.current_state === S_SEND_DATA_WORD,
-              "Stalled in SEND_HEADER when ft601_txe=1 (FIFO full)");
+              "Stalled in SEND_DATA_WORD when ft601_txe=1 (FIFO full)");
         check(ft601_wr_n === 1'b1,
               "ft601_wr_n not asserted during backpressure stall");
 
         ft601_txe = 0;
-        repeat (2) @(posedge ft601_clk_in); #1;
+        repeat (6) @(posedge ft601_clk_in); #1;
 
-        check(uut.current_state !== S_SEND_HEADER,
+        check(uut.current_state === S_IDLE || uut.current_state === S_WAIT_ACK,
-              "Resumed from SEND_HEADER after backpressure released");
+              "Resumed and completed after backpressure released");
 
         // ════════════════════════════════════════════════════════
         // TEST GROUP 9: Clock divider
@@ -705,13 +701,6 @@ module tb_usb_data_interface;
         ft601_txe = 0;
         preload_pending_data;
         assert_range_valid(32'h1111_2222);
-        wait_for_state(S_SEND_DOPPLER, 100);
-        pulse_doppler_once(16'h3333, 16'h4444);
-        pulse_doppler_once(16'h3333, 16'h4444);
-        pulse_doppler_once(16'h3333, 16'h4444);
-        pulse_doppler_once(16'h3333, 16'h4444);
-        wait_for_state(S_SEND_DETECT, 100);
-        pulse_cfar_once(1'b0);
         wait_for_state(S_WAIT_ACK, 50);
         #1;
 
@@ -805,7 +794,7 @@ module tb_usb_data_interface;
         // Start a write packet
         preload_pending_data;
         assert_range_valid(32'hFACE_FEED);
-        wait_for_state(S_SEND_HEADER, 50);
+        wait_for_state(S_SEND_DATA_WORD, 50);
         @(posedge ft601_clk_in); #1;
 
         // While write FSM is active, assert RXF=0 (host has data)
@@ -818,13 +807,6 @@ module tb_usb_data_interface;
 
         // Deassert RXF, complete the write packet
         ft601_rxf = 1;
-        wait_for_state(S_SEND_DOPPLER, 100);
-        pulse_doppler_once(16'hAAAA, 16'hBBBB);
-        pulse_doppler_once(16'hAAAA, 16'hBBBB);
-        pulse_doppler_once(16'hAAAA, 16'hBBBB);
-        pulse_doppler_once(16'hAAAA, 16'hBBBB);
-        wait_for_state(S_SEND_DETECT, 100);
-        pulse_cfar_once(1'b1);
         wait_for_state(S_IDLE, 100);
         @(posedge ft601_clk_in); #1;
 
@@ -841,32 +823,42 @@ module tb_usb_data_interface;
         // ════════════════════════════════════════════════════════
         // TEST GROUP 15: Stream Control Gating (Gap 2)
         // Verify that disabling individual streams causes the write
-        // FSM to skip those data phases.
+        // FSM to zero those fields in the packed words.
         // ════════════════════════════════════════════════════════
         $display("\n--- Test Group 15: Stream Control Gating (Gap 2) ---");
 
         // 15a: Disable doppler stream (stream_control = 3'b101 = range + cfar only)
         apply_reset;
-        ft601_txe = 0;
+        ft601_txe = 1;  // Stall to inspect packed words
         stream_control = 3'b101;  // range + cfar, no doppler
         // Wait for CDC propagation (2-stage sync)
         repeat (6) @(posedge ft601_clk_in);
 
-        // Preload cfar pending so the FSM enters the SEND_DETECT data path
+        @(posedge clk);
-        // (without it, SEND_DETECT skips immediately on !cfar_data_pending).
+        doppler_real   = 16'hAAAA;
-        preload_cfar_pending;
+        doppler_imag   = 16'hBBBB;
-        // Drive range valid — triggers write FSM
+        cfar_detection = 1'b1;
-        assert_range_valid(32'hAA11_BB22);
+        @(posedge clk);
-        // FSM: IDLE -> SEND_HEADER -> SEND_RANGE (doppler disabled) -> SEND_DETECT -> FOOTER
-        // The FSM races through SEND_DETECT in 1 cycle (cfar_data_pending is consumed).
-        // Verify the packet completed correctly (doppler was skipped).
-        wait_for_state(S_IDLE, 200);
-        #1;
-        // Reaching IDLE proves: HEADER -> RANGE -> (skip DOPPLER) -> DETECT -> FOOTER -> ACK -> IDLE.
-        // cfar_data_pending consumed confirms SEND_DETECT was entered.
-        check(uut.current_state === S_IDLE && uut.cfar_data_pending === 1'b0,
-              "Stream gate: reached SEND_DETECT (range sent, doppler skipped)");
 
+        preload_cfar_pending;
+        assert_range_valid(32'hAA11_BB22);
+
+        wait_for_state(S_SEND_DATA_WORD, 200);
+        repeat (2) @(posedge ft601_clk_in); #1;
+
+        // With doppler disabled, doppler fields in words 1 and 2 should be zero
+        // Word 1: {range[7:0], 0x00, 0x00, 0x00} (doppler zeroed)
+        check(uut.data_pkt_word1[23:0] === 24'h000000,
+              "Stream gate: doppler bytes zeroed in word 1 when disabled");
+
+        // Word 2 byte 3 (dop_im_lo) should also be zero
+        check(uut.data_pkt_word2[31:24] === 8'h00,
+              "Stream gate: dop_im_lo zeroed in word 2 when disabled");
+
+        // Let it complete
+        ft601_txe = 0;
+        wait_for_state(S_IDLE, 100);
+        #1;
         check(uut.current_state === S_IDLE,
               "Stream gate: packet completed without doppler");
 
@@ -951,28 +943,6 @@ module tb_usb_data_interface;
               "Status readback: returned to IDLE after 8-word response");
 
         // Verify the status snapshot was captured correctly.
-        // status_words[0] = {0xFF, 3'b000, mode[1:0], 5'b0, stream_ctrl[2:0], cfar_threshold[15:0]}
-        // = {8'hFF, 3'b000, 2'b01, 5'b00000, 3'b101, 16'hABCD}
-        // = 0xFF_09_05_ABCD... let's compute:
-        // Byte 3: 0xFF = 8'hFF
-        // Byte 2: {3'b000, 2'b01} = 5'b00001 + 3 high bits of next field...
-        // Actually the packing is: {8'hFF, 3'b000, status_radar_mode[1:0], 5'b00000, status_stream_ctrl[2:0], status_cfar_threshold[15:0]}
-        // = {8'hFF, 3'b000, 2'b01, 5'b00000, 3'b101, 16'hABCD}
-        // = 8'hFF, 5'b00001, 8'b00000101, 16'hABCD
-        // = FF_09_05_ABCD? Let me compute carefully:
-        // Bits [31:24] = 8'hFF = 0xFF
-        // Bits [23:21] = 3'b000
-        // Bits [20:19] = 2'b01 (mode)
-        // Bits [18:14] = 5'b00000
-        // Bits [13:11] = 3'b101 (stream_ctrl)
-        // Bits [10:0]  = ... wait, cfar_threshold is 16 bits → [15:0]
-        // Total bits = 8+3+2+5+3+16 = 37 bits — won't fit in 32!
-        // Re-reading the RTL: the packing at line 241 is:
-        //   {8'hFF, 3'b000, status_radar_mode, 5'b00000, status_stream_ctrl, status_cfar_threshold}
-        //   = 8 + 3 + 2 + 5 + 3 + 16 = 37 bits
-        // This would be truncated to 32 bits. Let me re-read the actual RTL to check.
-        // For now, just verify status_words[1] (word index 1 in the packet = idx 2 in FSM)
-        // status_words[1] = {status_long_chirp, status_long_listen} = {16'd3000, 16'd13700}
         check(uut.status_words[1] === {16'd3000, 16'd13700},
               "Status readback: word 1 = {long_chirp, long_listen}");
         check(uut.status_words[2] === {16'd17540, 16'd50},

9_Firmware/9_2_FPGA/usb_data_interface.v

@@ -1,3 +1,17 @@
+/**
+ * usb_data_interface.v
+ *
+ * FT601 USB 3.0 SuperSpeed FIFO Interface (32-bit bus, 100 MHz ft601_clk).
+ * Used on the 200T premium dev board. Production 50T board uses
+ * usb_data_interface_ft2232h.v (FT2232H, 8-bit, 60 MHz) instead.
+ *
+ * USB disconnect recovery:
+ *   A clock-activity watchdog in the clk domain detects when ft601_clk_in
+ *   stops (USB cable unplugged). After ~0.65 ms of silence (65536 system
+ *   clocks) it asserts ft601_clk_lost, which is OR'd into the FT-domain
+ *   reset so FSMs and FIFOs return to a clean state. When ft601_clk_in
+ *   resumes, a 2-stage reset synchronizer deasserts the reset cleanly.
+ */
 module usb_data_interface (
     input wire clk,              // Main clock (100MHz recommended)
     input wire reset_n,
@@ -15,13 +29,18 @@ module usb_data_interface (
     // FT601 Interface (Slave FIFO mode)
     // Data bus
     inout wire [31:0] ft601_data,    // 32-bit bidirectional data bus
-    output reg [3:0] ft601_be,       // Byte enable (4 lanes for 32-bit mode)
+    output reg [3:0] ft601_be,       // Byte enable (active-HIGH per DS_FT600Q-FT601Q Table 3.2)
     
     // Control signals
-    output reg ft601_txe_n,          // Transmit enable (active low)
+    // VESTIGIAL OUTPUTS — kept for 200T board port compatibility.
-    output reg ft601_rxf_n,          // Receive enable (active low)
+    // On the 200T, these are constrained to physical pins G21 (TXE) and
-    input wire ft601_txe,             // TXE: Transmit FIFO Not Full (high = space available to write)
+    // G22 (RXF) in xc7a200t_fbg484.xdc. Removing them from the RTL would
-    input wire ft601_rxf,             // RXF: Receive FIFO Not Empty (high = data available to read)
+    // break the 200T build. They are reset to 1 and never driven; the
+    // actual FT601 flow-control inputs are ft601_txe and ft601_rxf below.
+    output reg ft601_txe_n,          // VESTIGIAL: unused output, always 1
+    output reg ft601_rxf_n,          // VESTIGIAL: unused output, always 1
+    input wire ft601_txe,             // TXE: Transmit FIFO Not Full (active-low: 0 = space available)
+    input wire ft601_rxf,             // RXF: Receive FIFO Not Empty (active-low: 0 = data available)
     output reg ft601_wr_n,            // Write strobe (active low)
     output reg ft601_rd_n,            // Read strobe (active low)
     output reg ft601_oe_n,            // Output enable (active low)
@@ -97,21 +116,26 @@ localparam FT601_BURST_SIZE = 512;    // Max burst size in bytes
 // ============================================================================
 // WRITE FSM State definitions (Verilog-2001 compatible)
 // ============================================================================
-localparam [2:0] IDLE                = 3'd0,
+// Rewritten: data packet is now 3 x 32-bit writes (11 payload bytes + 1 pad).
-                 SEND_HEADER         = 3'd1,
+// Word 0: {HEADER, range[31:24], range[23:16], range[15:8]}  BE=1111
-                 SEND_RANGE_DATA     = 3'd2,
+// Word 1: {range[7:0], doppler_real[15:8], doppler_real[7:0], doppler_imag[15:8]} BE=1111
-                 SEND_DOPPLER_DATA   = 3'd3,
+// Word 2: {doppler_imag[7:0], detection, FOOTER, 8'h00}      BE=1110
-                 SEND_DETECTION_DATA = 3'd4,
+localparam [3:0] IDLE                = 4'd0,
-                 SEND_FOOTER         = 3'd5,
+                 SEND_DATA_WORD      = 4'd1,
-                 WAIT_ACK            = 3'd6,
+                 SEND_STATUS         = 4'd2,
-                 SEND_STATUS         = 3'd7;  // Gap 2: status readback
+                 WAIT_ACK            = 4'd3;
 
-reg [2:0] current_state;
+reg [3:0] current_state;
-reg [7:0] byte_counter;
+reg [1:0] data_word_idx;     // 0..2 for 3-word data packet
-reg [31:0] data_buffer;
 reg [31:0] ft601_data_out;
 reg ft601_data_oe;  // Output enable for bidirectional data bus
 
+// Pre-packed data words (registered snapshot of CDC'd data)
+reg [31:0] data_pkt_word0;
+reg [31:0] data_pkt_word1;
+reg [31:0] data_pkt_word2;
+reg [3:0]  data_pkt_be2;     // BE for last word (BE=1110 since byte 3 is pad)
+
 // ============================================================================
 // READ FSM State definitions (Gap 4: USB Read Path)
 // ============================================================================
@@ -184,6 +208,67 @@ always @(posedge clk or negedge reset_n) begin
     end
 end
 
+// ============================================================================
+// CLOCK-ACTIVITY WATCHDOG (clk domain)
+// ============================================================================
+// Detects when ft601_clk_in stops (USB cable unplugged). A toggle register
+// in the ft601_clk domain flips every edge. The clk domain synchronizes it
+// and checks for transitions. If no transition is seen for 2^16 = 65536
+// clk cycles (~0.65 ms at 100 MHz), ft601_clk_lost asserts.
+
+// Toggle register: flips every ft601_clk edge (ft601_clk domain)
+reg ft601_heartbeat;
+always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
+    if (!ft601_reset_n)
+        ft601_heartbeat <= 1'b0;
+    else
+        ft601_heartbeat <= ~ft601_heartbeat;
+end
+
+// Synchronize heartbeat into clk domain (2-stage)
+(* ASYNC_REG = "TRUE" *) reg [1:0] ft601_hb_sync;
+reg ft601_hb_prev;
+reg [15:0] ft601_clk_timeout;
+reg ft601_clk_lost;
+
+always @(posedge clk or negedge reset_n) begin
+    if (!reset_n) begin
+        ft601_hb_sync    <= 2'b00;
+        ft601_hb_prev    <= 1'b0;
+        ft601_clk_timeout <= 16'd0;
+        ft601_clk_lost   <= 1'b0;
+    end else begin
+        ft601_hb_sync <= {ft601_hb_sync[0], ft601_heartbeat};
+        ft601_hb_prev <= ft601_hb_sync[1];
+
+        if (ft601_hb_sync[1] != ft601_hb_prev) begin
+            // ft601_clk is alive — reset counter, clear lost flag
+            ft601_clk_timeout <= 16'd0;
+            ft601_clk_lost    <= 1'b0;
+        end else if (!ft601_clk_lost) begin
+            if (ft601_clk_timeout == 16'hFFFF)
+                ft601_clk_lost <= 1'b1;
+            else
+                ft601_clk_timeout <= ft601_clk_timeout + 16'd1;
+        end
+    end
+end
+
+// Effective FT601-domain reset: asserted by global reset OR clock loss.
+// Deassertion synchronized to ft601_clk via 2-stage sync to avoid
+// metastability on the recovery edge.
+(* ASYNC_REG = "TRUE" *) reg [1:0] ft601_reset_sync;
+wire ft601_reset_raw_n = ft601_reset_n & ~ft601_clk_lost;
+
+always @(posedge ft601_clk_in or negedge ft601_reset_raw_n) begin
+    if (!ft601_reset_raw_n)
+        ft601_reset_sync <= 2'b00;
+    else
+        ft601_reset_sync <= {ft601_reset_sync[0], 1'b1};
+end
+
+wire ft601_effective_reset_n = ft601_reset_sync[1];
+
 // FT601-domain captured data (sampled from holding regs on sync'd edge)
 reg [31:0] range_profile_cap;
 reg [15:0] doppler_real_cap;
@@ -197,6 +282,18 @@ reg cfar_detection_cap;
 reg doppler_data_pending;
 reg cfar_data_pending;
 
+// 1-cycle delayed range trigger.  range_valid_ft fires on the same clock
+// edge that range_profile_cap is captured (non-blocking).  If the FSM
+// reads range_profile_cap on that same edge it sees the STALE value.
+// Delaying the trigger by one cycle guarantees the capture register has
+// settled before the FSM packs the data words.
+reg range_data_ready;
+
+// Frame sync: sample counter (ft601_clk domain, wraps at NUM_CELLS)
+// Bit 7 of detection byte is set when sample_counter == 0 (frame start).
+localparam [11:0] NUM_CELLS = 12'd2048;  // 64 range x 32 doppler
+reg [11:0] sample_counter;
+
 // Gap 2: CDC for stream_control (clk_100m -> ft601_clk_in)
 // stream_control changes infrequently (only on host USB command), so
 // per-bit 2-stage synchronizers are sufficient. No Gray coding needed
@@ -228,8 +325,8 @@ wire range_valid_ft;
 wire doppler_valid_ft;
 wire cfar_valid_ft;
 
-always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
+always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
-    if (!ft601_reset_n) begin
+    if (!ft601_effective_reset_n) begin
         range_valid_sync   <= 2'b00;
         doppler_valid_sync <= 2'b00;
         cfar_valid_sync    <= 2'b00;
@@ -240,6 +337,7 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
         doppler_real_cap   <= 16'd0;
         doppler_imag_cap   <= 16'd0;
         cfar_detection_cap <= 1'b0;
+        range_data_ready   <= 1'b0;
         // Fix #5: Default to range-only on reset (prevents write FSM deadlock)
         stream_ctrl_sync_0 <= 3'b001;
         stream_ctrl_sync_1 <= 3'b001;
@@ -276,7 +374,7 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
             // Word 4: AGC metrics + range_mode
             status_words[4] <= {status_agc_current_gain,        // [31:28]
                                 status_agc_peak_magnitude,      // [27:20]
-                                status_agc_saturation_count,    // [19:12]
+                                status_agc_saturation_count,    // [19:12] 8-bit saturation count
                                 status_agc_enable,              // [11]
                                 9'd0,                           // [10:2] reserved
                                 status_range_mode};             // [1:0]
@@ -302,6 +400,10 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
         if (cfar_valid_sync[1] && !cfar_valid_sync_d) begin
             cfar_detection_cap <= cfar_detection_hold;
         end
+
+        // 1-cycle delayed trigger: ensures range_profile_cap has settled
+        // before the FSM reads it for word packing.
+        range_data_ready <= range_valid_ft;
     end
 end
 
@@ -314,11 +416,11 @@ assign cfar_valid_ft    = cfar_valid_sync[1]     && !cfar_valid_sync_d;
 // FT601 data bus direction control
 assign ft601_data = ft601_data_oe ? ft601_data_out : 32'hzzzz_zzzz;
 
-always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
+always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
-    if (!ft601_reset_n) begin
+    if (!ft601_effective_reset_n) begin
         current_state <= IDLE;
         read_state <= RD_IDLE;
-        byte_counter <= 0;
+        data_word_idx <= 2'd0;
         ft601_data_out <= 0;
         ft601_data_oe <= 0;
         ft601_be <= 4'b1111;  // All bytes enabled for 32-bit mode
@@ -336,6 +438,11 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
         cmd_value <= 16'd0;
         doppler_data_pending <= 1'b0;
         cfar_data_pending <= 1'b0;
+        data_pkt_word0 <= 32'd0;
+        data_pkt_word1 <= 32'd0;
+        data_pkt_word2 <= 32'd0;
+        data_pkt_be2   <= 4'b1110;
+        sample_counter <= 12'd0;
         // NOTE: ft601_clk_out is driven by the clk-domain always block below.
         // Do NOT assign it here (ft601_clk_in domain) — causes multi-driven net.
     end else begin
@@ -424,124 +531,66 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
                         current_state <= SEND_STATUS;
                         status_word_idx <= 3'd0;
                     end
-                    // Trigger write FSM on range_valid edge (primary data source).
+                    // Trigger on range_data_ready (1 cycle after range_valid_ft)
-                    // Doppler/cfar data_pending flags are checked inside
+                    // so that range_profile_cap has settled from the CDC block.
-                    // SEND_DOPPLER_DATA and SEND_DETECTION_DATA to skip or send.
+                    // Gate on pending flags: only send when all enabled
-                    // Do NOT trigger on pending flags alone — they're sticky and
+                    // streams have fresh data (avoids stale doppler/CFAR)
-                    // would cause repeated packet starts without new range data.
+                    else if (range_data_ready && stream_range_en
-                    else if (range_valid_ft && stream_range_en) begin
+                             && (!stream_doppler_en || doppler_data_pending)
+                             && (!stream_cfar_en    || cfar_data_pending)) begin
                         // Don't start write if a read is about to begin
                         if (ft601_rxf) begin  // rxf=1 means no host data pending
-                            current_state <= SEND_HEADER;
+                            // Pack 11-byte data packet into 3 x 32-bit words
-                            byte_counter <= 0;
+                            // Doppler fields zeroed when stream disabled
+                            // CFAR field zeroed when stream disabled
+                            data_pkt_word0 <= {HEADER,
+                                               range_profile_cap[31:24],
+                                               range_profile_cap[23:16],
+                                               range_profile_cap[15:8]};
+                            data_pkt_word1 <= {range_profile_cap[7:0],
+                                               stream_doppler_en ? doppler_real_cap[15:8] : 8'd0,
+                                               stream_doppler_en ? doppler_real_cap[7:0]  : 8'd0,
+                                               stream_doppler_en ? doppler_imag_cap[15:8] : 8'd0};
+                            data_pkt_word2 <= {stream_doppler_en ? doppler_imag_cap[7:0]  : 8'd0,
+                                               stream_cfar_en
+                                                    ? {(sample_counter == 12'd0), 6'b0, cfar_detection_cap}
+                                                    : {(sample_counter == 12'd0), 7'd0},
+                                               FOOTER,
+                                               8'h00};  // pad byte
+                            data_pkt_be2   <= 4'b1110;   // 3 valid bytes + 1 pad
+                            data_word_idx  <= 2'd0;
+                            current_state  <= SEND_DATA_WORD;
                         end
                     end
                 end
-                
+
-                SEND_HEADER: begin
+                SEND_DATA_WORD: begin
-                    if (!ft601_txe) begin  // FT601 TX FIFO not empty
-                        ft601_data_oe <= 1;
-                        ft601_data_out <= {24'b0, HEADER};
-                        ft601_be <= 4'b0001;  // Only lower byte valid
-                        ft601_wr_n <= 0;     // Assert write strobe
-                        // Gap 2: skip to first enabled stream
-                        if (stream_range_en)
-                            current_state <= SEND_RANGE_DATA;
-                        else if (stream_doppler_en)
-                            current_state <= SEND_DOPPLER_DATA;
-                        else if (stream_cfar_en)
-                            current_state <= SEND_DETECTION_DATA;
-                        else
-                            current_state <= SEND_FOOTER;  // No streams — send footer only
-                    end
-                end
-                
-                SEND_RANGE_DATA: begin
                     if (!ft601_txe) begin
                         ft601_data_oe <= 1;
-                        ft601_be <= 4'b1111;  // All bytes valid for 32-bit word
+                        ft601_wr_n <= 0;
-                        
+                        case (data_word_idx)
-                        case (byte_counter)
+                            2'd0: begin
-                            0: ft601_data_out <= range_profile_cap;
+                                ft601_data_out <= data_pkt_word0;
-                            1: ft601_data_out <= {range_profile_cap[23:0], 8'h00};
+                                ft601_be <= 4'b1111;
-                            2: ft601_data_out <= {range_profile_cap[15:0], 16'h0000};
+                            end
-                            3: ft601_data_out <= {range_profile_cap[7:0], 24'h000000};
+                            2'd1: begin
+                                ft601_data_out <= data_pkt_word1;
+                                ft601_be <= 4'b1111;
+                            end
+                            2'd2: begin
+                                ft601_data_out <= data_pkt_word2;
+                                ft601_be <= data_pkt_be2;
+                            end
+                            default: ;
                         endcase
-                        
+                        if (data_word_idx == 2'd2) begin
-                        ft601_wr_n <= 0;
+                            data_word_idx <= 2'd0;
-                        
+                            current_state <= WAIT_ACK;
-                        if (byte_counter == 3) begin
-                            byte_counter <= 0;
-                            // Gap 2: skip disabled streams
-                            if (stream_doppler_en)
-                                current_state <= SEND_DOPPLER_DATA;
-                            else if (stream_cfar_en)
-                                current_state <= SEND_DETECTION_DATA;
-                            else
-                                current_state <= SEND_FOOTER;
                         end else begin
-                            byte_counter <= byte_counter + 1;
+                            data_word_idx <= data_word_idx + 2'd1;
                         end
                     end
                 end
-                
-                SEND_DOPPLER_DATA: begin
-                    if (!ft601_txe && doppler_data_pending) begin
-                        ft601_data_oe <= 1;
-                        ft601_be <= 4'b1111;
-                        
-                        case (byte_counter)
-                            0: ft601_data_out <= {doppler_real_cap, doppler_imag_cap};
-                            1: ft601_data_out <= {doppler_imag_cap, doppler_real_cap[15:8], 8'h00};
-                            2: ft601_data_out <= {doppler_real_cap[7:0], doppler_imag_cap[15:8], 16'h0000};
-                            3: ft601_data_out <= {doppler_imag_cap[7:0], 24'h000000};
-                        endcase
-                        
-                        ft601_wr_n <= 0;
-                        
-                        if (byte_counter == 3) begin
-                            byte_counter <= 0;
-                            doppler_data_pending <= 1'b0;
-                            if (stream_cfar_en)
-                                current_state <= SEND_DETECTION_DATA;
-                            else
-                                current_state <= SEND_FOOTER;
-                        end else begin
-                            byte_counter <= byte_counter + 1;
-                        end
-                    end else if (!doppler_data_pending) begin
-                        // No doppler data available yet — skip to next stream
-                        byte_counter <= 0;
-                        if (stream_cfar_en)
-                            current_state <= SEND_DETECTION_DATA;
-                        else
-                            current_state <= SEND_FOOTER;
-                    end
-                end
-                
-                SEND_DETECTION_DATA: begin
-                    if (!ft601_txe && cfar_data_pending) begin
-                        ft601_data_oe <= 1;
-                        ft601_be <= 4'b0001;
-                        ft601_data_out <= {24'b0, 7'b0, cfar_detection_cap};
-                        ft601_wr_n <= 0;
-                        cfar_data_pending <= 1'b0;
-                        current_state <= SEND_FOOTER;
-                    end else if (!cfar_data_pending) begin
-                        // No CFAR data available yet — skip to footer
-                        current_state <= SEND_FOOTER;
-                    end
-                end
-                
-                SEND_FOOTER: begin
-                    if (!ft601_txe) begin
-                        ft601_data_oe <= 1;
-                        ft601_be <= 4'b0001;
-                        ft601_data_out <= {24'b0, FOOTER};
-                        ft601_wr_n <= 0;
-                        current_state <= WAIT_ACK;
-                    end
-                end
 
                 // Gap 2: Status readback — send 6 x 32-bit status words
                 // Format: HEADER, status_words[0..5], FOOTER
@@ -581,6 +630,14 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
                 WAIT_ACK: begin
                     ft601_wr_n <= 1;
                     ft601_data_oe <= 0;  // Release data bus
+                    // Clear pending flags — data consumed
+                    doppler_data_pending <= 1'b0;
+                    cfar_data_pending    <= 1'b0;
+                    // Advance frame sync counter
+                    if (sample_counter == NUM_CELLS - 12'd1)
+                        sample_counter <= 12'd0;
+                    else
+                        sample_counter <= sample_counter + 12'd1;
                     current_state <= IDLE;
                 end
             endcase
@@ -613,8 +670,8 @@ ODDR #(
 `else
 // Simulation: behavioral clock forwarding
 reg ft601_clk_out_sim;
-always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
+always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
-    if (!ft601_reset_n)
+    if (!ft601_effective_reset_n)
         ft601_clk_out_sim <= 1'b0;
     else
         ft601_clk_out_sim <= 1'b1;

9_Firmware/9_2_FPGA/usb_data_interface_ft2232h.v

@@ -36,6 +36,13 @@
  * Clock domains:
  *   clk       = 100 MHz system clock (radar data domain)
  *   ft_clk    = 60 MHz from FT2232H CLKOUT (USB FIFO domain)
+ *
+ * USB disconnect recovery:
+ *   A clock-activity watchdog in the clk domain detects when ft_clk stops
+ *   (USB cable unplugged). After ~0.65 ms of silence (65536 system clocks)
+ *   it asserts ft_clk_lost, which is OR'd into the FT-domain reset so
+ *   FSMs and FIFOs return to a clean state. When ft_clk resumes, a 2-stage
+ *   reset synchronizer deasserts the reset cleanly in the ft_clk domain.
  */
 
 module usb_data_interface_ft2232h (
@@ -59,7 +66,9 @@ module usb_data_interface_ft2232h (
     output reg ft_rd_n,             // Read strobe (active low)
     output reg ft_wr_n,             // Write strobe (active low)
     output reg ft_oe_n,             // Output enable (active low) — bus direction
-    output reg ft_siwu,             // Send Immediate / WakeUp
+    output reg ft_siwu,             // Send Immediate / WakeUp — UNUSED: held low.
+                                    // SIWU could flush the TX FIFO for lower latency
+                                    // but is not needed at current data rates. Deferred.
 
     // Clock from FT2232H (directly used — no ODDR forwarding needed)
     input wire ft_clk,              // 60 MHz from FT2232H CLKOUT
@@ -134,6 +143,7 @@ localparam [2:0] RD_IDLE       = 3'd0,
 reg [2:0] rd_state;
 reg [1:0] rd_byte_cnt;   // 0..3 for 4-byte command word
 reg [31:0] rd_shift_reg;  // Shift register to assemble 4-byte command
+reg rd_cmd_complete;      // Set when all 4 bytes received (distinguishes from abort)
 
 // ============================================================================
 // DATA BUS DIRECTION CONTROL
@@ -192,6 +202,70 @@ always @(posedge clk or negedge reset_n) begin
     end
 end
 
+// ============================================================================
+// CLOCK-ACTIVITY WATCHDOG (clk domain)
+// ============================================================================
+// Detects when ft_clk stops (USB cable unplugged). A toggle register in the
+// ft_clk domain flips every ft_clk edge. The clk domain synchronizes it and
+// checks for transitions. If no transition is seen for 2^16 = 65536 clk
+// cycles (~0.65 ms at 100 MHz), ft_clk_lost asserts.
+//
+// ft_clk_lost feeds into the effective reset for the ft_clk domain so that
+// FSMs and capture registers return to a clean state automatically.
+
+// Toggle register: flips every ft_clk edge (ft_clk domain)
+reg ft_heartbeat;
+always @(posedge ft_clk or negedge ft_reset_n) begin
+    if (!ft_reset_n)
+        ft_heartbeat <= 1'b0;
+    else
+        ft_heartbeat <= ~ft_heartbeat;
+end
+
+// Synchronize heartbeat into clk domain (2-stage)
+(* ASYNC_REG = "TRUE" *) reg [1:0] ft_hb_sync;
+reg ft_hb_prev;
+reg [15:0] ft_clk_timeout;
+reg ft_clk_lost;
+
+always @(posedge clk or negedge reset_n) begin
+    if (!reset_n) begin
+        ft_hb_sync    <= 2'b00;
+        ft_hb_prev    <= 1'b0;
+        ft_clk_timeout <= 16'd0;
+        ft_clk_lost   <= 1'b0;
+    end else begin
+        ft_hb_sync <= {ft_hb_sync[0], ft_heartbeat};
+        ft_hb_prev <= ft_hb_sync[1];
+
+        if (ft_hb_sync[1] != ft_hb_prev) begin
+            // ft_clk is alive — reset counter, clear lost flag
+            ft_clk_timeout <= 16'd0;
+            ft_clk_lost    <= 1'b0;
+        end else if (!ft_clk_lost) begin
+            if (ft_clk_timeout == 16'hFFFF)
+                ft_clk_lost <= 1'b1;
+            else
+                ft_clk_timeout <= ft_clk_timeout + 16'd1;
+        end
+    end
+end
+
+// Effective FT-domain reset: asserted by global reset OR clock loss.
+// Deassertion synchronized to ft_clk via 2-stage sync to avoid
+// metastability on the recovery edge.
+(* ASYNC_REG = "TRUE" *) reg [1:0] ft_reset_sync;
+wire ft_reset_raw_n = ft_reset_n & ~ft_clk_lost;
+
+always @(posedge ft_clk or negedge ft_reset_raw_n) begin
+    if (!ft_reset_raw_n)
+        ft_reset_sync <= 2'b00;
+    else
+        ft_reset_sync <= {ft_reset_sync[0], 1'b1};
+end
+
+wire ft_effective_reset_n = ft_reset_sync[1];
+
 // --- 3-stage synchronizers (ft_clk domain) ---
 // 3 stages for better MTBF at 60 MHz
 
@@ -228,12 +302,25 @@ reg cfar_detection_cap;
 reg doppler_data_pending;
 reg cfar_data_pending;
 
+// 1-cycle delayed range trigger.  range_valid_ft fires on the same clock
+// edge that range_profile_cap is captured (non-blocking).  If the FSM
+// reads range_profile_cap on that same edge it sees the STALE value.
+// Delaying the trigger by one cycle guarantees the capture register has
+// settled before the byte mux reads it.
+reg range_data_ready;
+
+// Frame sync: sample counter (ft_clk domain, wraps at NUM_CELLS)
+// Bit 7 of detection byte is set when sample_counter == 0 (frame start).
+// This allows the Python host to resynchronize without a protocol change.
+localparam [11:0] NUM_CELLS = 12'd2048;  // 64 range x 32 doppler
+reg [11:0] sample_counter;
+
 // Status snapshot (ft_clk domain)
 reg [31:0] status_words [0:5];
 
 integer si;  // status_words loop index
-always @(posedge ft_clk or negedge ft_reset_n) begin
+always @(posedge ft_clk or negedge ft_effective_reset_n) begin
-    if (!ft_reset_n) begin
+    if (!ft_effective_reset_n) begin
         range_toggle_sync   <= 3'b000;
         doppler_toggle_sync <= 3'b000;
         cfar_toggle_sync    <= 3'b000;
@@ -246,6 +333,7 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
         doppler_real_cap    <= 16'd0;
         doppler_imag_cap    <= 16'd0;
         cfar_detection_cap  <= 1'b0;
+        range_data_ready    <= 1'b0;
         // Default to range-only on reset (prevents write FSM deadlock)
         stream_ctrl_sync_0  <= 3'b001;
         stream_ctrl_sync_1  <= 3'b001;
@@ -279,6 +367,10 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
         if (cfar_valid_ft)
             cfar_detection_cap <= cfar_detection_hold;
 
+        // 1-cycle delayed trigger: ensures range_profile_cap has settled
+        // before the FSM reads it via the byte mux.
+        range_data_ready <= range_valid_ft;
+
         // Status snapshot on request
         if (status_req_ft) begin
             // Word 0: {0xFF[31:24], mode[23:22], stream[21:19], 3'b000[18:16], threshold[15:0]}
@@ -315,11 +407,16 @@ always @(*) begin
         5'd2:  data_pkt_byte = range_profile_cap[23:16];
         5'd3:  data_pkt_byte = range_profile_cap[15:8];
         5'd4:  data_pkt_byte = range_profile_cap[7:0];     // range LSB
-        5'd5:  data_pkt_byte = doppler_real_cap[15:8];      // doppler_real MSB
+        // Doppler fields: zero when stream_doppler_en is off
-        5'd6:  data_pkt_byte = doppler_real_cap[7:0];       // doppler_real LSB
+        5'd5:  data_pkt_byte = stream_doppler_en ? doppler_real_cap[15:8]  : 8'd0;
-        5'd7:  data_pkt_byte = doppler_imag_cap[15:8];      // doppler_imag MSB
+        5'd6:  data_pkt_byte = stream_doppler_en ? doppler_real_cap[7:0]   : 8'd0;
-        5'd8:  data_pkt_byte = doppler_imag_cap[7:0];       // doppler_imag LSB
+        5'd7:  data_pkt_byte = stream_doppler_en ? doppler_imag_cap[15:8]  : 8'd0;
-        5'd9:  data_pkt_byte = {7'b0, cfar_detection_cap};  // detection
+        5'd8:  data_pkt_byte = stream_doppler_en ? doppler_imag_cap[7:0]   : 8'd0;
+        // Detection field: zero when stream_cfar_en is off
+        // Bit 7 = frame_start flag (sample_counter == 0), bit 0 = cfar_detection
+        5'd9:  data_pkt_byte = stream_cfar_en
+                   ? {(sample_counter == 12'd0), 6'b0, cfar_detection_cap}
+                   : {(sample_counter == 12'd0), 7'd0};
         5'd10: data_pkt_byte = FOOTER;
         default: data_pkt_byte = 8'h00;
     endcase
@@ -376,12 +473,13 @@ end
 // Write FSM and Read FSM share the bus. Write FSM operates when Read FSM
 // is idle. Read FSM takes priority when host has data available.
 
-always @(posedge ft_clk or negedge ft_reset_n) begin
+always @(posedge ft_clk or negedge ft_effective_reset_n) begin
-    if (!ft_reset_n) begin
+    if (!ft_effective_reset_n) begin
         wr_state       <= WR_IDLE;
         wr_byte_idx    <= 5'd0;
         rd_state       <= RD_IDLE;
         rd_byte_cnt    <= 2'd0;
+        rd_cmd_complete <= 1'b0;
         rd_shift_reg   <= 32'd0;
         ft_data_out    <= 8'd0;
         ft_data_oe     <= 1'b0;
@@ -396,6 +494,7 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
         cmd_value      <= 16'd0;
         doppler_data_pending <= 1'b0;
         cfar_data_pending    <= 1'b0;
+        sample_counter       <= 12'd0;
     end else begin
         // Default: clear one-shot signals
         cmd_valid <= 1'b0;
@@ -437,17 +536,19 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
                 rd_shift_reg <= {rd_shift_reg[23:0], ft_data};
                 if (rd_byte_cnt == 2'd3) begin
                     // All 4 bytes received
-                    ft_rd_n     <= 1'b1;
+                    ft_rd_n         <= 1'b1;
-                    rd_byte_cnt <= 2'd0;
+                    rd_byte_cnt     <= 2'd0;
-                    rd_state    <= RD_DEASSERT;
+                    rd_cmd_complete <= 1'b1;
+                    rd_state        <= RD_DEASSERT;
                 end else begin
                     rd_byte_cnt <= rd_byte_cnt + 2'd1;
                     // Keep reading if more data available
                     if (ft_rxf_n) begin
                         // Host ran out of data mid-command — abort
-                        ft_rd_n     <= 1'b1;
+                        ft_rd_n         <= 1'b1;
-                        rd_byte_cnt <= 2'd0;
+                        rd_byte_cnt     <= 2'd0;
-                        rd_state    <= RD_DEASSERT;
+                        rd_cmd_complete <= 1'b0;
+                        rd_state        <= RD_DEASSERT;
                     end
                 end
             end
@@ -456,7 +557,8 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
                 // Deassert OE (1 cycle after RD deasserted)
                 ft_oe_n  <= 1'b1;
                 // Only process if we received a full 4-byte command
-                if (rd_byte_cnt == 2'd0) begin
+                if (rd_cmd_complete) begin
+                    rd_cmd_complete <= 1'b0;
                     rd_state <= RD_PROCESS;
                 end else begin
                     // Incomplete command — discard
@@ -491,8 +593,13 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
                         wr_state    <= WR_STATUS_SEND;
                         wr_byte_idx <= 5'd0;
                     end
-                    // Trigger on range_valid edge (primary data trigger)
+                    // Trigger on range_data_ready (1 cycle after range_valid_ft)
-                    else if (range_valid_ft && stream_range_en) begin
+                    // so that range_profile_cap has settled from the CDC block.
+                    // Gate on pending flags: only send when all enabled
+                    // streams have fresh data (avoids stale doppler/CFAR)
+                    else if (range_data_ready && stream_range_en
+                             && (!stream_doppler_en || doppler_data_pending)
+                             && (!stream_cfar_en    || cfar_data_pending)) begin
                         if (ft_rxf_n) begin  // No host read pending
                             wr_state    <= WR_DATA_SEND;
                             wr_byte_idx <= 5'd0;
@@ -538,6 +645,11 @@ always @(posedge ft_clk or negedge ft_reset_n) begin
                     // Clear pending flags — data consumed
                     doppler_data_pending <= 1'b0;
                     cfar_data_pending    <= 1'b0;
+                    // Advance frame sync counter
+                    if (sample_counter == NUM_CELLS - 12'd1)
+                        sample_counter <= 12'd0;
+                    else
+                        sample_counter <= sample_counter + 12'd1;
                     wr_state   <= WR_IDLE;
                 end
 

9_Firmware/9_3_GUI/GUI_V6.py

@@ -1,3 +1,9 @@
+# =============================================================================
+# DEPRECATED: GUI V6 is superseded by GUI_V65_Tk (tkinter) and V7 (PyQt6).
+# This file is retained for reference only. Do not use for new development.
+# Removal planned for next major release.
+# =============================================================================
+
 import tkinter as tk
 from tkinter import ttk, messagebox
 import threading

9_Firmware/9_3_GUI/GUI_V65_Tk.py

@@ -59,7 +59,7 @@ except (ModuleNotFoundError, ImportError):
 
 # Import protocol layer (no GUI deps)
 from radar_protocol import (
-    RadarProtocol, FT2232HConnection,
+    RadarProtocol, FT2232HConnection, FT601Connection,
     DataRecorder, RadarAcquisition,
     RadarFrame, StatusResponse,
     NUM_RANGE_BINS, NUM_DOPPLER_BINS, WATERFALL_DEPTH,
@@ -98,9 +98,10 @@ class DemoTarget:
 
     __slots__ = ("azimuth", "classification", "id", "range_m", "snr", "velocity")
 
-    # Physical range grid: 64 bins x ~4.8 m/bin = ~307 m max
+    # Physical range grid: 64 bins x ~24 m/bin = ~1536 m max
-    _RANGE_PER_BIN: float = (3e8 / (2 * 500e6)) * 16  # ~4.8 m
+    # Bin spacing = c / (2 * Fs) * decimation, where Fs = 100 MHz DDC output.
-    _MAX_RANGE: float = _RANGE_PER_BIN * NUM_RANGE_BINS  # ~307 m
+    _RANGE_PER_BIN: float = (3e8 / (2 * 100e6)) * 16  # ~24 m
+    _MAX_RANGE: float = _RANGE_PER_BIN * NUM_RANGE_BINS  # ~1536 m
 
     def __init__(self, tid: int):
         self.id = tid
@@ -187,10 +188,10 @@ class DemoSimulator:
         mag = np.zeros((NUM_RANGE_BINS, NUM_DOPPLER_BINS), dtype=np.float64)
         det = np.zeros((NUM_RANGE_BINS, NUM_DOPPLER_BINS), dtype=np.uint8)
 
-        # Range/Doppler scaling (approximate)
+        # Range/Doppler scaling: bin spacing = c/(2*Fs)*decimation
-        range_per_bin = (3e8 / (2 * 500e6)) * 16  # ~4.8 m/bin
+        range_per_bin = (3e8 / (2 * 100e6)) * 16  # ~24 m/bin
         max_range = range_per_bin * NUM_RANGE_BINS
-        vel_per_bin = 1.484  # m/s per Doppler bin (from WaveformConfig)
+        vel_per_bin = 5.34  # m/s per Doppler bin (radar_scene.py: lam/(2*16*PRI))
 
         for t in targets:
             if t.range_m > max_range or t.range_m < 0:
@@ -385,13 +386,14 @@ class RadarDashboard:
     UPDATE_INTERVAL_MS = 100  # 10 Hz display refresh
 
     # Radar parameters used for range-axis scaling.
-    BANDWIDTH = 500e6        # Hz — chirp bandwidth
+    SAMPLE_RATE = 100e6      # Hz — DDC output I/Q rate (matched filter input)
     C = 3e8                  # m/s — speed of light
 
-    def __init__(self, root: tk.Tk, connection: FT2232HConnection,
+    def __init__(self, root: tk.Tk, mock: bool,
                  recorder: DataRecorder, device_index: int = 0):
         self.root = root
-        self.conn = connection
+        self._mock = mock
+        self.conn: FT2232HConnection | FT601Connection | None = None
         self.recorder = recorder
         self.device_index = device_index
 
@@ -485,6 +487,16 @@ class RadarDashboard:
                                        style="Accent.TButton")
         self.btn_connect.pack(side="right", padx=4)
 
+        # USB Interface selector (production FT2232H / premium FT601)
+        self._usb_iface_var = tk.StringVar(value="FT2232H (Production)")
+        self.cmb_usb_iface = ttk.Combobox(
+            top, textvariable=self._usb_iface_var,
+            values=["FT2232H (Production)", "FT601 (Premium)"],
+            state="readonly", width=20,
+        )
+        self.cmb_usb_iface.pack(side="right", padx=4)
+        ttk.Label(top, text="USB:", font=("Menlo", 10)).pack(side="right")
+
         self.btn_record = ttk.Button(top, text="Record", command=self._on_record)
         self.btn_record.pack(side="right", padx=4)
 
@@ -515,9 +527,8 @@ class RadarDashboard:
 
     def _build_display_tab(self, parent):
         # Compute physical axis limits
-        range_res = self.C / (2.0 * self.BANDWIDTH)  # ~0.3 m per FFT bin
+        # Bin spacing = c / (2 * Fs_ddc) for matched-filter processing.
-        # After decimation 1024→64, each range bin = 16 FFT bins
+        range_per_bin = self.C / (2.0 * self.SAMPLE_RATE) * 16  # ~24 m
-        range_per_bin = range_res * 16
         max_range = range_per_bin * NUM_RANGE_BINS
 
         doppler_bin_lo = 0
@@ -1018,15 +1029,17 @@ class RadarDashboard:
 
     # ------------------------------------------------------------ Actions
     def _on_connect(self):
-        if self.conn.is_open:
+        if self.conn is not None and self.conn.is_open:
             # Disconnect
             if self._acq_thread is not None:
                 self._acq_thread.stop()
                 self._acq_thread.join(timeout=2)
                 self._acq_thread = None
             self.conn.close()
+            self.conn = None
             self.lbl_status.config(text="DISCONNECTED", foreground=RED)
             self.btn_connect.config(text="Connect")
+            self.cmb_usb_iface.config(state="readonly")
             log.info("Disconnected")
             return
 
@@ -1036,6 +1049,16 @@ class RadarDashboard:
         if self._replay_active:
             self._replay_stop()
 
+        # Create connection based on USB Interface selector
+        iface = self._usb_iface_var.get()
+        if "FT601" in iface:
+            self.conn = FT601Connection(mock=self._mock)
+        else:
+            self.conn = FT2232HConnection(mock=self._mock)
+
+        # Disable interface selector while connecting/connected
+        self.cmb_usb_iface.config(state="disabled")
+
         # Open connection in a background thread to avoid blocking the GUI
         self.lbl_status.config(text="CONNECTING...", foreground=YELLOW)
         self.btn_connect.config(state="disabled")
@@ -1062,6 +1085,8 @@ class RadarDashboard:
         else:
             self.lbl_status.config(text="CONNECT FAILED", foreground=RED)
             self.btn_connect.config(text="Connect")
+            self.cmb_usb_iface.config(state="readonly")
+            self.conn = None
 
     def _on_record(self):
         if self.recorder.recording:
@@ -1110,6 +1135,9 @@ class RadarDashboard:
                  f"Opcode 0x{opcode:02X} is hardware-only (ignored in replay)"))
             return
         cmd = RadarProtocol.build_command(opcode, value)
+        if self.conn is None:
+            log.warning("No connection — command not sent")
+            return
         ok = self.conn.write(cmd)
         log.info(f"CMD 0x{opcode:02X} val={value} ({'OK' if ok else 'FAIL'})")
 
@@ -1148,7 +1176,7 @@ class RadarDashboard:
         if self._replay_active or self._replay_ctrl is not None:
             self._replay_stop()
         if self._acq_thread is not None:
-            if self.conn.is_open:
+            if self.conn is not None and self.conn.is_open:
                 self._on_connect()  # disconnect
             else:
                 # Connection dropped unexpectedly — just clean up the thread
@@ -1547,17 +1575,17 @@ def main():
     args = parser.parse_args()
 
     if args.live:
-        conn = FT2232HConnection(mock=False)
+        mock = False
         mode_str = "LIVE"
     else:
-        conn = FT2232HConnection(mock=True)
+        mock = True
         mode_str = "MOCK"
 
     recorder = DataRecorder()
 
     root = tk.Tk()
 
-    dashboard = RadarDashboard(root, conn, recorder, device_index=args.device)
+    dashboard = RadarDashboard(root, mock, recorder, device_index=args.device)
 
     if args.record:
         filepath = os.path.join(
@@ -1582,8 +1610,8 @@ def main():
         if dashboard._acq_thread is not None:
             dashboard._acq_thread.stop()
             dashboard._acq_thread.join(timeout=2)
-        if conn.is_open:
+        if dashboard.conn is not None and dashboard.conn.is_open:
-            conn.close()
+            dashboard.conn.close()
         if recorder.recording:
             recorder.stop()
         root.destroy()

9_Firmware/9_3_GUI/GUI_V6_Demo.py

@@ -1,5 +1,11 @@
 #!/usr/bin/env python3
 
+# =============================================================================
+# DEPRECATED: GUI V6 Demo is superseded by GUI_V65_Tk and V7.
+# This file is retained for reference only. Do not use for new development.
+# Removal planned for next major release.
+# =============================================================================
+
 """
 Radar System GUI - Fully Functional Demo Version
 All buttons work, simulated radar data is generated in real-time

9_Firmware/9_3_GUI/GUI_versions.txt

@@ -6,7 +6,7 @@ GUI_V4 ==> Added pitch correction
 
 GUI_V5 ==> Added Mercury Color
 
-GUI_V6 ==> Added USB3 FT601 support
+GUI_V6 ==> Added USB3 FT601 support  [DEPRECATED — superseded by V65/V7]
 
 GUI_V65_Tk ==> Board bring-up dashboard (FT2232H reader, real-time R-D heatmap, CFAR overlay, waterfall, host commands, HDF5 recording, replay, demo mode)
 radar_protocol ==> Protocol layer (packet parsing, command building, FT2232H connection, data recorder, acquisition thread)

9_Firmware/9_3_GUI/radar_protocol.py

@@ -6,6 +6,7 @@ Pure-logic module for USB packet parsing and command building.
 No GUI dependencies — safe to import from tests and headless scripts.
 
 USB Interface: FT2232H USB 2.0 (8-bit, 50T production board) via pyftdi
+               FT601 USB 3.0 (32-bit, 200T premium board) via ftd3xx
 
 USB Packet Protocol (11-byte):
   TX (FPGA→Host):
@@ -22,7 +23,7 @@ import queue
 import logging
 import contextlib
 from dataclasses import dataclass, field
-from typing import Any
+from typing import Any, ClassVar
 from enum import IntEnum
 
 
@@ -200,7 +201,9 @@ class RadarProtocol:
         range_i = _to_signed16(struct.unpack_from(">H", raw, 3)[0])
         doppler_i = _to_signed16(struct.unpack_from(">H", raw, 5)[0])
         doppler_q = _to_signed16(struct.unpack_from(">H", raw, 7)[0])
-        detection = raw[9] & 0x01
+        det_byte = raw[9]
+        detection = det_byte & 0x01
+        frame_start = (det_byte >> 7) & 0x01
 
         return {
             "range_i": range_i,
@@ -208,6 +211,7 @@ class RadarProtocol:
             "doppler_i": doppler_i,
             "doppler_q": doppler_q,
             "detection": detection,
+            "frame_start": frame_start,
         }
 
     @staticmethod
@@ -433,7 +437,191 @@ class FT2232HConnection:
             pkt += struct.pack(">h", np.clip(range_i, -32768, 32767))
             pkt += struct.pack(">h", np.clip(dop_i, -32768, 32767))
             pkt += struct.pack(">h", np.clip(dop_q, -32768, 32767))
-            pkt.append(detection & 0x01)
+            # Bit 7 = frame_start (sample_counter == 0), bit 0 = detection
+            det_byte = (detection & 0x01) | (0x80 if idx == 0 else 0x00)
+            pkt.append(det_byte)
+            pkt.append(FOOTER_BYTE)
+
+            buf += pkt
+
+        self._mock_seq_idx = (start_idx + num_packets) % NUM_CELLS
+        return bytes(buf)
+
+
+# ============================================================================
+# FT601 USB 3.0 Connection (premium board only)
+# ============================================================================
+
+# Optional ftd3xx import (FTDI's proprietary driver for FT60x USB 3.0 chips).
+# pyftdi does NOT support FT601 — it only handles USB 2.0 chips (FT232H, etc.)
+try:
+    import ftd3xx  # type: ignore[import-untyped]
+    FTD3XX_AVAILABLE = True
+    _Ftd3xxError: type = ftd3xx.FTD3XXError  # type: ignore[attr-defined]
+except ImportError:
+    FTD3XX_AVAILABLE = False
+    _Ftd3xxError = OSError  # fallback for type-checking; never raised
+
+
+class FT601Connection:
+    """
+    FT601 USB 3.0 SuperSpeed FIFO bridge — premium board only.
+
+    The FT601 has a 32-bit data bus and runs at 100 MHz.
+    VID:PID = 0x0403:0x6030 or 0x6031 (FTDI FT60x).
+
+    Requires the ``ftd3xx`` library (``pip install ftd3xx`` on Windows,
+    or ``libft60x`` on Linux). This is FTDI's proprietary USB 3.0 driver;
+    ``pyftdi`` only supports USB 2.0 and will NOT work with FT601.
+
+    Public contract matches FT2232HConnection so callers can swap freely.
+    """
+
+    VID = 0x0403
+    PID_LIST: ClassVar[list[int]] = [0x6030, 0x6031]
+
+    def __init__(self, mock: bool = True):
+        self._mock = mock
+        self._dev = None
+        self._lock = threading.Lock()
+        self.is_open = False
+        # Mock state (reuses same synthetic data pattern)
+        self._mock_frame_num = 0
+        self._mock_rng = np.random.RandomState(42)
+
+    def open(self, device_index: int = 0) -> bool:
+        if self._mock:
+            self.is_open = True
+            log.info("FT601 mock device opened (no hardware)")
+            return True
+
+        if not FTD3XX_AVAILABLE:
+            log.error(
+                "ftd3xx library required for FT601 hardware — "
+                "install with: pip install ftd3xx"
+            )
+            return False
+
+        try:
+            self._dev = ftd3xx.create(device_index, ftd3xx.OPEN_BY_INDEX)
+            if self._dev is None:
+                log.error("No FT601 device found at index %d", device_index)
+                return False
+            # Verify chip configuration — only reconfigure if needed.
+            # setChipConfiguration triggers USB re-enumeration, which
+            # invalidates the device handle and requires a re-open cycle.
+            cfg = self._dev.getChipConfiguration()
+            needs_reconfig = (
+                cfg.FIFOMode != 0            # 245 FIFO mode
+                or cfg.ChannelConfig != 0    # 1 channel, 32-bit
+                or cfg.OptionalFeatureSupport != 0
+            )
+            if needs_reconfig:
+                cfg.FIFOMode = 0
+                cfg.ChannelConfig = 0
+                cfg.OptionalFeatureSupport = 0
+                self._dev.setChipConfiguration(cfg)
+                # Device re-enumerates — close stale handle, wait, re-open
+                self._dev.close()
+                self._dev = None
+                import time
+                time.sleep(2.0)  # wait for USB re-enumeration
+                self._dev = ftd3xx.create(device_index, ftd3xx.OPEN_BY_INDEX)
+                if self._dev is None:
+                    log.error("FT601 not found after reconfiguration")
+                    return False
+                log.info("FT601 reconfigured and re-opened (index %d)", device_index)
+            self.is_open = True
+            log.info("FT601 device opened (index %d)", device_index)
+            return True
+        except (OSError, _Ftd3xxError) as e:
+            log.error("FT601 open failed: %s", e)
+            self._dev = None
+            return False
+
+    def close(self):
+        if self._dev is not None:
+            with contextlib.suppress(Exception):
+                self._dev.close()
+            self._dev = None
+        self.is_open = False
+
+    def read(self, size: int = 4096) -> bytes | None:
+        """Read raw bytes from FT601. Returns None on error/timeout."""
+        if not self.is_open:
+            return None
+
+        if self._mock:
+            return self._mock_read(size)
+
+        with self._lock:
+            try:
+                data = self._dev.readPipe(0x82, size, raw=True)
+                return bytes(data) if data else None
+            except (OSError, _Ftd3xxError) as e:
+                log.error("FT601 read error: %s", e)
+                return None
+
+    def write(self, data: bytes) -> bool:
+        """Write raw bytes to FT601. Data must be 4-byte aligned for 32-bit bus."""
+        if not self.is_open:
+            return False
+
+        if self._mock:
+            log.info(f"FT601 mock write: {data.hex()}")
+            return True
+
+        # Pad to 4-byte alignment (FT601 32-bit bus requirement).
+        # NOTE: Radar commands are already 4 bytes, so this should be a no-op.
+        remainder = len(data) % 4
+        if remainder:
+            data = data + b"\x00" * (4 - remainder)
+
+        with self._lock:
+            try:
+                written = self._dev.writePipe(0x02, data, raw=True)
+                return written == len(data)
+            except (OSError, _Ftd3xxError) as e:
+                log.error("FT601 write error: %s", e)
+                return False
+
+    def _mock_read(self, size: int) -> bytes:
+        """Generate synthetic radar packets (same pattern as FT2232H mock)."""
+        time.sleep(0.05)
+        self._mock_frame_num += 1
+
+        buf = bytearray()
+        num_packets = min(NUM_CELLS, size // DATA_PACKET_SIZE)
+        start_idx = getattr(self, "_mock_seq_idx", 0)
+
+        for n in range(num_packets):
+            idx = (start_idx + n) % NUM_CELLS
+            rbin = idx // NUM_DOPPLER_BINS
+            dbin = idx % NUM_DOPPLER_BINS
+
+            range_i = int(self._mock_rng.normal(0, 100))
+            range_q = int(self._mock_rng.normal(0, 100))
+            if abs(rbin - 20) < 3:
+                range_i += 5000
+                range_q += 3000
+
+            dop_i = int(self._mock_rng.normal(0, 50))
+            dop_q = int(self._mock_rng.normal(0, 50))
+            if abs(rbin - 20) < 3 and abs(dbin - 8) < 2:
+                dop_i += 8000
+                dop_q += 4000
+
+            detection = 1 if (abs(rbin - 20) < 2 and abs(dbin - 8) < 2) else 0
+
+            pkt = bytearray()
+            pkt.append(HEADER_BYTE)
+            pkt += struct.pack(">h", np.clip(range_q, -32768, 32767))
+            pkt += struct.pack(">h", np.clip(range_i, -32768, 32767))
+            pkt += struct.pack(">h", np.clip(dop_i, -32768, 32767))
+            pkt += struct.pack(">h", np.clip(dop_q, -32768, 32767))
+            # Bit 7 = frame_start (sample_counter == 0), bit 0 = detection
+            det_byte = (detection & 0x01) | (0x80 if idx == 0 else 0x00)
+            pkt.append(det_byte)
             pkt.append(FOOTER_BYTE)
 
             buf += pkt
@@ -600,6 +788,12 @@ class RadarAcquisition(threading.Thread):
             if sample.get("detection", 0):
                 self._frame.detections[rbin, dbin] = 1
                 self._frame.detection_count += 1
+            # Accumulate FPGA range profile data (matched-filter output)
+            # Each sample carries the range_i/range_q for this range bin.
+            # Accumulate magnitude across Doppler bins for the range profile.
+            ri = int(sample.get("range_i", 0))
+            rq = int(sample.get("range_q", 0))
+            self._frame.range_profile[rbin] += abs(ri) + abs(rq)
 
         self._sample_idx += 1
 
@@ -607,11 +801,11 @@ class RadarAcquisition(threading.Thread):
             self._finalize_frame()
 
     def _finalize_frame(self):
-        """Complete frame: compute range profile, push to queue, record."""
+        """Complete frame: push to queue, record."""
         self._frame.timestamp = time.time()
         self._frame.frame_number = self._frame_num
-        # Range profile = sum of magnitude across Doppler bins
+        # range_profile is already accumulated from FPGA range_i/range_q
-        self._frame.range_profile = np.sum(self._frame.magnitude, axis=1)
+        # data in _ingest_sample(). No need to synthesize from doppler magnitude.
 
         # Push to display queue (drop old if backed up)
         try:

9_Firmware/9_3_GUI/test_GUI_V65_Tk.py

@@ -16,7 +16,7 @@ import unittest
 import numpy as np
 
 from radar_protocol import (
-    RadarProtocol, FT2232HConnection, DataRecorder, RadarAcquisition,
+    RadarProtocol, FT2232HConnection, FT601Connection, DataRecorder, RadarAcquisition,
     RadarFrame, StatusResponse, Opcode,
     HEADER_BYTE, FOOTER_BYTE, STATUS_HEADER_BYTE,
     NUM_RANGE_BINS, NUM_DOPPLER_BINS,
@@ -312,6 +312,61 @@ class TestFT2232HConnection(unittest.TestCase):
         self.assertFalse(conn.write(b"\x00\x00\x00\x00"))
 
 
+class TestFT601Connection(unittest.TestCase):
+    """Test mock FT601 connection (mirrors FT2232H tests)."""
+
+    def test_mock_open_close(self):
+        conn = FT601Connection(mock=True)
+        self.assertTrue(conn.open())
+        self.assertTrue(conn.is_open)
+        conn.close()
+        self.assertFalse(conn.is_open)
+
+    def test_mock_read_returns_data(self):
+        conn = FT601Connection(mock=True)
+        conn.open()
+        data = conn.read(4096)
+        self.assertIsNotNone(data)
+        self.assertGreater(len(data), 0)
+        conn.close()
+
+    def test_mock_read_contains_valid_packets(self):
+        """Mock data should contain parseable data packets."""
+        conn = FT601Connection(mock=True)
+        conn.open()
+        raw = conn.read(4096)
+        packets = RadarProtocol.find_packet_boundaries(raw)
+        self.assertGreater(len(packets), 0)
+        for start, end, ptype in packets:
+            if ptype == "data":
+                result = RadarProtocol.parse_data_packet(raw[start:end])
+                self.assertIsNotNone(result)
+        conn.close()
+
+    def test_mock_write(self):
+        conn = FT601Connection(mock=True)
+        conn.open()
+        cmd = RadarProtocol.build_command(0x01, 1)
+        self.assertTrue(conn.write(cmd))
+        conn.close()
+
+    def test_write_pads_to_4_bytes(self):
+        """FT601 write() should pad data to 4-byte alignment."""
+        conn = FT601Connection(mock=True)
+        conn.open()
+        # 3-byte payload should be padded internally (no error)
+        self.assertTrue(conn.write(b"\x01\x02\x03"))
+        conn.close()
+
+    def test_read_when_closed(self):
+        conn = FT601Connection(mock=True)
+        self.assertIsNone(conn.read())
+
+    def test_write_when_closed(self):
+        conn = FT601Connection(mock=True)
+        self.assertFalse(conn.write(b"\x00\x00\x00\x00"))
+
+
 class TestDataRecorder(unittest.TestCase):
     """Test HDF5 recording (skipped if h5py not available)."""
 

9_Firmware/9_3_GUI/test_v7.py

@@ -65,9 +65,9 @@ class TestRadarSettings(unittest.TestCase):
 
     def test_defaults(self):
         s = _models().RadarSettings()
-        self.assertEqual(s.system_frequency, 10e9)
+        self.assertEqual(s.system_frequency, 10.5e9)
-        self.assertEqual(s.coverage_radius, 50000)
+        self.assertEqual(s.coverage_radius, 1536)
-        self.assertEqual(s.max_distance, 50000)
+        self.assertEqual(s.max_distance, 1536)
 
 
 class TestGPSData(unittest.TestCase):
@@ -425,26 +425,28 @@ class TestWaveformConfig(unittest.TestCase):
     def test_defaults(self):
         from v7.models import WaveformConfig
         wc = WaveformConfig()
-        self.assertEqual(wc.sample_rate_hz, 4e6)
+        self.assertEqual(wc.sample_rate_hz, 100e6)
-        self.assertEqual(wc.bandwidth_hz, 500e6)
+        self.assertEqual(wc.bandwidth_hz, 20e6)
-        self.assertEqual(wc.chirp_duration_s, 300e-6)
+        self.assertEqual(wc.chirp_duration_s, 30e-6)
-        self.assertEqual(wc.center_freq_hz, 10.525e9)
+        self.assertEqual(wc.pri_s, 167e-6)
+        self.assertEqual(wc.center_freq_hz, 10.5e9)
         self.assertEqual(wc.n_range_bins, 64)
         self.assertEqual(wc.n_doppler_bins, 32)
+        self.assertEqual(wc.chirps_per_subframe, 16)
         self.assertEqual(wc.fft_size, 1024)
         self.assertEqual(wc.decimation_factor, 16)
 
     def test_range_resolution(self):
-        """range_resolution_m should be ~5.62 m/bin with ADI defaults."""
+        """range_resolution_m should be ~23.98 m/bin (matched filter, 100 MSPS)."""
         from v7.models import WaveformConfig
         wc = WaveformConfig()
-        self.assertAlmostEqual(wc.range_resolution_m, 5.621, places=1)
+        self.assertAlmostEqual(wc.range_resolution_m, 23.983, places=1)
 
     def test_velocity_resolution(self):
-        """velocity_resolution_mps should be ~1.484 m/s/bin."""
+        """velocity_resolution_mps should be ~5.34 m/s/bin (PRI=167us, 16 chirps)."""
         from v7.models import WaveformConfig
         wc = WaveformConfig()
-        self.assertAlmostEqual(wc.velocity_resolution_mps, 1.484, places=2)
+        self.assertAlmostEqual(wc.velocity_resolution_mps, 5.343, places=1)
 
     def test_max_range(self):
         """max_range_m = range_resolution * n_range_bins."""
@@ -466,7 +468,7 @@ class TestWaveformConfig(unittest.TestCase):
         """Non-default parameters correctly change derived values."""
         from v7.models import WaveformConfig
         wc1 = WaveformConfig()
-        wc2 = WaveformConfig(bandwidth_hz=1e9)  # double BW → halve range res
+        wc2 = WaveformConfig(sample_rate_hz=200e6)  # double Fs → halve range bin
         self.assertAlmostEqual(wc2.range_resolution_m, wc1.range_resolution_m / 2, places=2)
 
     def test_zero_center_freq_velocity(self):
@@ -925,9 +927,9 @@ class TestExtractTargetsFromFrame(unittest.TestCase):
         """Detection at range bin 10 → range = 10 * range_resolution."""
         from v7.processing import extract_targets_from_frame
         frame = self._make_frame(det_cells=[(10, 16)])  # dbin=16 = center → vel=0
-        targets = extract_targets_from_frame(frame, range_resolution=5.621)
+        targets = extract_targets_from_frame(frame, range_resolution=23.983)
         self.assertEqual(len(targets), 1)
-        self.assertAlmostEqual(targets[0].range, 10 * 5.621, places=2)
+        self.assertAlmostEqual(targets[0].range, 10 * 23.983, places=1)
         self.assertAlmostEqual(targets[0].velocity, 0.0, places=2)
 
     def test_velocity_sign(self):

9_Firmware/9_3_GUI/v7/__init__.py

@@ -26,6 +26,7 @@ from .models import (
 # Hardware interfaces — production protocol via radar_protocol.py
 from .hardware import (
     FT2232HConnection,
+    FT601Connection,
     RadarProtocol,
     Opcode,
     RadarAcquisition,
@@ -89,7 +90,7 @@ __all__ = [  # noqa: RUF022
     "USB_AVAILABLE", "FTDI_AVAILABLE", "SCIPY_AVAILABLE",
     "SKLEARN_AVAILABLE", "FILTERPY_AVAILABLE",
     # hardware — production FPGA protocol
-    "FT2232HConnection", "RadarProtocol", "Opcode",
+    "FT2232HConnection", "FT601Connection", "RadarProtocol", "Opcode",
     "RadarAcquisition", "RadarFrame", "StatusResponse", "DataRecorder",
     "STM32USBInterface",
     # processing

9_Firmware/9_3_GUI/v7/dashboard.py

@@ -13,13 +13,14 @@ RadarDashboard is a QMainWindow with six tabs:
   6. Settings    — Host-side DSP parameters + About section
 
 Uses production radar_protocol.py for all FPGA communication:
-  - FT2232HConnection for real hardware
+  - FT2232HConnection for production board (FT2232H USB 2.0)
+  - FT601Connection for premium board (FT601 USB 3.0) — selectable from GUI
   - Unified replay via SoftwareFPGA + ReplayEngine + ReplayWorker
   - Mock mode (FT2232HConnection(mock=True)) for development
 
 The old STM32 magic-packet start flow has been removed. FPGA registers
 are controlled directly via 4-byte {opcode, addr, value_hi, value_lo}
-commands sent over FT2232H.
+commands sent over FT2232H or FT601.
 """
 
 from __future__ import annotations
@@ -55,6 +56,7 @@ from .models import (
 )
 from .hardware import (
     FT2232HConnection,
+    FT601Connection,
     RadarProtocol,
     RadarFrame,
     StatusResponse,
@@ -142,7 +144,7 @@ class RadarDashboard(QMainWindow):
         )
 
         # Hardware interfaces — production protocol
-        self._connection: FT2232HConnection | None = None
+        self._connection: FT2232HConnection | FT601Connection | None = None
         self._stm32 = STM32USBInterface()
         self._recorder = DataRecorder()
 
@@ -364,7 +366,7 @@ class RadarDashboard(QMainWindow):
         # Row 0: connection mode + device combos + buttons
         ctrl_layout.addWidget(QLabel("Mode:"), 0, 0)
         self._mode_combo = QComboBox()
-        self._mode_combo.addItems(["Mock", "Live FT2232H", "Replay"])
+        self._mode_combo.addItems(["Mock", "Live", "Replay"])
         self._mode_combo.setCurrentIndex(0)
         ctrl_layout.addWidget(self._mode_combo, 0, 1)
 
@@ -377,6 +379,13 @@ class RadarDashboard(QMainWindow):
         refresh_btn.clicked.connect(self._refresh_devices)
         ctrl_layout.addWidget(refresh_btn, 0, 4)
 
+        # USB Interface selector (production FT2232H / premium FT601)
+        ctrl_layout.addWidget(QLabel("USB Interface:"), 0, 5)
+        self._usb_iface_combo = QComboBox()
+        self._usb_iface_combo.addItems(["FT2232H (Production)", "FT601 (Premium)"])
+        self._usb_iface_combo.setCurrentIndex(0)
+        ctrl_layout.addWidget(self._usb_iface_combo, 0, 6)
+
         self._start_btn = QPushButton("Start Radar")
         self._start_btn.setStyleSheet(
             f"QPushButton {{ background-color: {DARK_SUCCESS}; color: white; font-weight: bold; }}"
@@ -1001,7 +1010,8 @@ class RadarDashboard(QMainWindow):
         self._conn_ft2232h = self._make_status_label("FT2232H")
         self._conn_stm32 = self._make_status_label("STM32 USB")
 
-        conn_layout.addWidget(QLabel("FT2232H:"), 0, 0)
+        self._conn_usb_label = QLabel("USB Data:")
+        conn_layout.addWidget(self._conn_usb_label, 0, 0)
         conn_layout.addWidget(self._conn_ft2232h, 0, 1)
         conn_layout.addWidget(QLabel("STM32 USB:"), 1, 0)
         conn_layout.addWidget(self._conn_stm32, 1, 1)
@@ -1167,7 +1177,7 @@ class RadarDashboard(QMainWindow):
         about_lbl = QLabel(
             "<b>AERIS-10 Radar System V7</b><br>"
             "PyQt6 Edition with Embedded Leaflet Map<br><br>"
-            "<b>Data Interface:</b> FT2232H USB 2.0 (production protocol)<br>"
+            "<b>Data Interface:</b> FT2232H USB 2.0 (production) / FT601 USB 3.0 (premium)<br>"
             "<b>FPGA Protocol:</b> 4-byte register commands, 0xAA/0xBB packets<br>"
             "<b>Map:</b> OpenStreetMap + Leaflet.js<br>"
             "<b>Framework:</b> PyQt6 + QWebEngine<br>"
@@ -1224,7 +1234,7 @@ class RadarDashboard(QMainWindow):
     # =====================================================================
 
     def _send_fpga_cmd(self, opcode: int, value: int):
-        """Send a 4-byte register command to the FPGA via FT2232H."""
+        """Send a 4-byte register command to the FPGA via USB (FT2232H or FT601)."""
         if self._connection is None or not self._connection.is_open:
             logger.warning(f"Cannot send 0x{opcode:02X}={value}: no connection")
             return
@@ -1287,16 +1297,26 @@ class RadarDashboard(QMainWindow):
 
             if "Mock" in mode:
                 self._replay_mode = False
-                self._connection = FT2232HConnection(mock=True)
+                iface = self._usb_iface_combo.currentText()
+                if "FT601" in iface:
+                    self._connection = FT601Connection(mock=True)
+                else:
+                    self._connection = FT2232HConnection(mock=True)
                 if not self._connection.open():
                     QMessageBox.critical(self, "Error", "Failed to open mock connection.")
                     return
             elif "Live" in mode:
                 self._replay_mode = False
-                self._connection = FT2232HConnection(mock=False)
+                iface = self._usb_iface_combo.currentText()
+                if "FT601" in iface:
+                    self._connection = FT601Connection(mock=False)
+                    iface_name = "FT601"
+                else:
+                    self._connection = FT2232HConnection(mock=False)
+                    iface_name = "FT2232H"
                 if not self._connection.open():
                     QMessageBox.critical(self, "Error",
-                                         "Failed to open FT2232H. Check USB connection.")
+                                         f"Failed to open {iface_name}. Check USB connection.")
                     return
             elif "Replay" in mode:
                 self._replay_mode = True
@@ -1368,6 +1388,7 @@ class RadarDashboard(QMainWindow):
                 self._start_btn.setEnabled(False)
                 self._stop_btn.setEnabled(True)
                 self._mode_combo.setEnabled(False)
+                self._usb_iface_combo.setEnabled(False)
                 self._demo_btn_main.setEnabled(False)
                 self._demo_btn_map.setEnabled(False)
                 n_frames = self._replay_engine.total_frames
@@ -1417,6 +1438,7 @@ class RadarDashboard(QMainWindow):
             self._start_btn.setEnabled(False)
             self._stop_btn.setEnabled(True)
             self._mode_combo.setEnabled(False)
+            self._usb_iface_combo.setEnabled(False)
             self._demo_btn_main.setEnabled(False)
             self._demo_btn_map.setEnabled(False)
             self._status_label_main.setText(f"Status: Running ({mode})")
@@ -1462,6 +1484,7 @@ class RadarDashboard(QMainWindow):
         self._start_btn.setEnabled(True)
         self._stop_btn.setEnabled(False)
         self._mode_combo.setEnabled(True)
+        self._usb_iface_combo.setEnabled(True)
         self._demo_btn_main.setEnabled(True)
         self._demo_btn_map.setEnabled(True)
         self._status_label_main.setText("Status: Radar stopped")
@@ -1954,6 +1977,12 @@ class RadarDashboard(QMainWindow):
         self._set_conn_indicator(self._conn_ft2232h, conn_open)
         self._set_conn_indicator(self._conn_stm32, self._stm32.is_open)
 
+        # Update USB label to reflect which interface is active
+        if isinstance(self._connection, FT601Connection):
+            self._conn_usb_label.setText("FT601:")
+        else:
+            self._conn_usb_label.setText("FT2232H:")
+
         gps_count = self._gps_packet_count
         if self._gps_worker:
             gps_count = self._gps_worker.gps_count

9_Firmware/9_3_GUI/v7/hardware.py

@@ -25,6 +25,7 @@ if USB_AVAILABLE:
 sys.path.insert(0, os.path.join(os.path.dirname(__file__), ".."))
 from radar_protocol import (  # noqa: F401 — re-exported for v7 package
     FT2232HConnection,
+    FT601Connection,
     RadarProtocol,
     Opcode,
     RadarAcquisition,
@@ -46,8 +47,9 @@ class STM32USBInterface:
 
     Used ONLY for receiving GPS data from the MCU.
 
-    FPGA register commands are sent via FT2232H (see FT2232HConnection
+    FPGA register commands are sent via the USB data interface — either
-    from radar_protocol.py). The old send_start_flag() / send_settings()
+    FT2232HConnection (production) or FT601Connection (premium), both
+    from radar_protocol.py. The old send_start_flag() / send_settings()
     methods have been removed — they used an incompatible magic-packet
     protocol that the FPGA does not understand.
     """

9_Firmware/9_3_GUI/v7/map_widget.py

@@ -98,7 +98,7 @@ class RadarMapWidget(QWidget):
         )
         self._targets: list[RadarTarget] = []
         self._pending_targets: list[RadarTarget] | None = None
-        self._coverage_radius = 50_000   # metres
+        self._coverage_radius = 1_536   # metres (64 bins x ~24 m/bin)
         self._tile_server = TileServer.OPENSTREETMAP
         self._show_coverage = True
         self._show_trails = False

9_Firmware/9_3_GUI/v7/models.py

@@ -108,12 +108,12 @@ class RadarSettings:
     range_resolution and velocity_resolution should be calibrated to
     the actual waveform parameters.
     """
-    system_frequency: float = 10e9      # Hz (carrier, used for velocity calc)
+    system_frequency: float = 10.5e9    # Hz (carrier, used for velocity calc)
-    range_resolution: float = 781.25    # Meters per range bin (default: 50km/64)
+    range_resolution: float = 24.0       # Meters per range bin (c/(2*Fs)*decim)
-    velocity_resolution: float = 1.0    # m/s per Doppler bin (calibrate to waveform)
+    velocity_resolution: float = 1.0     # m/s per Doppler bin (calibrate to waveform)
-    max_distance: float = 50000         # Max detection range (m)
+    max_distance: float = 1536           # Max detection range (m)
-    map_size: float = 50000             # Map display size (m)
+    map_size: float = 2000               # Map display size (m)
-    coverage_radius: float = 50000      # Map coverage radius (m)
+    coverage_radius: float = 1536        # Map coverage radius (m)
 
 
 @dataclass
@@ -199,39 +199,46 @@ class WaveformConfig:
     Encapsulates the radar waveform so that range/velocity resolution
     can be derived automatically instead of hardcoded in RadarSettings.
 
-    Defaults match the ADI CN0566 Phaser capture parameters used in
+    Defaults match the AERIS-10 production system parameters from
-    the golden_reference cosim (4 MSPS, 500 MHz BW, 300 us chirp).
+    radar_scene.py / plfm_chirp_controller.v:
+      100 MSPS DDC output, 20 MHz chirp BW, 30 us long chirp,
+      167 us long-chirp PRI, X-band 10.5 GHz carrier.
     """
 
-    sample_rate_hz: float = 4e6          # ADC sample rate
+    sample_rate_hz: float = 100e6        # DDC output I/Q rate (matched filter input)
-    bandwidth_hz: float = 500e6          # Chirp bandwidth
+    bandwidth_hz: float = 20e6           # Chirp bandwidth (not used in range calc;
-    chirp_duration_s: float = 300e-6     # Chirp ramp time
+                                         # retained for time-bandwidth product / display)
-    center_freq_hz: float = 10.525e9     # Carrier frequency
+    chirp_duration_s: float = 30e-6      # Long chirp ramp time
+    pri_s: float = 167e-6               # Pulse repetition interval (chirp + listen)
+    center_freq_hz: float = 10.5e9       # Carrier frequency (radar_scene.py: F_CARRIER)
     n_range_bins: int = 64               # After decimation
-    n_doppler_bins: int = 32             # After Doppler FFT
+    n_doppler_bins: int = 32             # Total Doppler bins (2 sub-frames x 16)
+    chirps_per_subframe: int = 16        # Chirps in one Doppler sub-frame
     fft_size: int = 1024                 # Pre-decimation FFT length
     decimation_factor: int = 16          # 1024 → 64
 
     @property
     def range_resolution_m(self) -> float:
-        """Meters per decimated range bin (FMCW deramped baseband).
+        """Meters per decimated range bin (matched-filter pulse compression).
 
-        For deramped FMCW: bin spacing = c * Fs * T / (2 * N_FFT * BW).
+        For FFT-based matched filtering, each IFFT output bin spans
-        After decimation the bin spacing grows by *decimation_factor*.
+        c / (2 * Fs) in range, where Fs is the I/Q sample rate at the
+        matched-filter input (DDC output).  After decimation the bin
+        spacing grows by *decimation_factor*.
         """
         c = 299_792_458.0
-        raw_bin = (
+        raw_bin = c / (2.0 * self.sample_rate_hz)
-            c * self.sample_rate_hz * self.chirp_duration_s
-            / (2.0 * self.fft_size * self.bandwidth_hz)
-        )
         return raw_bin * self.decimation_factor
 
     @property
     def velocity_resolution_mps(self) -> float:
-        """m/s per Doppler bin.  lambda / (2 * n_doppler * chirp_duration)."""
+        """m/s per Doppler bin.
+
+        lambda / (2 * chirps_per_subframe * PRI), matching radar_scene.py.
+        """
         c = 299_792_458.0
         wavelength = c / self.center_freq_hz
-        return wavelength / (2.0 * self.n_doppler_bins * self.chirp_duration_s)
+        return wavelength / (2.0 * self.chirps_per_subframe * self.pri_s)
 
     @property
     def max_range_m(self) -> float:

9_Firmware/9_3_GUI/v7/workers.py

@@ -334,7 +334,7 @@ class TargetSimulator(QObject):
             self._add_random_target()
 
     def _add_random_target(self):
-        range_m = random.uniform(5000, 40000)
+        range_m = random.uniform(50, 1400)
         azimuth = random.uniform(0, 360)
         velocity = random.uniform(-100, 100)
         elevation = random.uniform(-5, 45)
@@ -368,7 +368,7 @@ class TargetSimulator(QObject):
 
         for t in self._targets:
             new_range = t.range - t.velocity * 0.5
-            if new_range < 500 or new_range > 50000:
+            if new_range < 10 or new_range > 1536:
                 continue  # target exits coverage — drop it
 
             new_vel = max(-150, min(150, t.velocity + random.uniform(-2, 2)))

9_Firmware/tests/cross_layer/contract_parser.py

@@ -188,7 +188,7 @@ def parse_python_data_packet_fields(filepath: Path | None = None) -> list[DataPa
             width_bits=size * 8
         ))
 
-    # Match detection = raw[9] & 0x01
+    # Match detection = raw[9] & 0x01  (direct access)
     for m in re.finditer(r'(\w+)\s*=\s*raw\[(\d+)\]\s*&\s*(0x[0-9a-fA-F]+|\d+)', body):
         name = m.group(1)
         offset = int(m.group(2))
@@ -196,6 +196,24 @@ def parse_python_data_packet_fields(filepath: Path | None = None) -> list[DataPa
             name=name, byte_start=offset, byte_end=offset, width_bits=1
         ))
 
+    # Match intermediate variable pattern: var = raw[N], then field = var & MASK
+    for m in re.finditer(r'(\w+)\s*=\s*raw\[(\d+)\]', body):
+        var_name = m.group(1)
+        offset = int(m.group(2))
+        # Find fields derived from this intermediate variable
+        for m2 in re.finditer(
+            rf'(\w+)\s*=\s*(?:\({var_name}\s*>>\s*\d+\)\s*&|{var_name}\s*&)\s*'
+            r'(0x[0-9a-fA-F]+|\d+)',
+            body,
+        ):
+            name = m2.group(1)
+            # Skip if already captured by direct raw[] access pattern
+            if not any(f.name == name for f in fields):
+                fields.append(DataPacketField(
+                    name=name, byte_start=offset, byte_end=offset,
+                    width_bits=1
+                ))
+
     fields.sort(key=lambda f: f.byte_start)
     return fields
 
@@ -584,12 +602,28 @@ def parse_verilog_data_mux(
 
     for m in re.finditer(
         r"5'd(\d+)\s*:\s*data_pkt_byte\s*=\s*(.+?);",
-        mux_body
+        mux_body, re.DOTALL
     ):
         idx = int(m.group(1))
         expr = m.group(2).strip()
         entries.append((idx, expr))
 
+    # Helper: extract the dominant signal name from a mux expression.
+    # Handles direct refs like ``range_profile_cap[31:24]``, ternaries
+    # like ``stream_doppler_en ? doppler_real_cap[15:8] : 8'd0``, and
+    # concat-ternaries like ``stream_cfar_en ? {…, cfar_detection_cap} : …``.
+    def _extract_signal(expr: str) -> str | None:
+        # If it's a ternary, use the true-branch to find the data signal
+        tern = re.match(r'\w+\s*\?\s*(.+?)\s*:\s*.+', expr, re.DOTALL)
+        target = tern.group(1) if tern else expr
+        # Look for a known data signal (xxx_cap pattern or cfar_detection_cap)
+        cap_match = re.search(r'(\w+_cap)\b', target)
+        if cap_match:
+            return cap_match.group(1)
+        # Fall back to first identifier before a bit-select
+        sig_match = re.match(r'(\w+?)(?:\[|$)', target)
+        return sig_match.group(1) if sig_match else None
+
     # Group consecutive bytes by signal root name
     fields: list[DataPacketField] = []
     i = 0
@@ -599,22 +633,21 @@ def parse_verilog_data_mux(
             i += 1
             continue
 
-        # Extract signal name (e.g., range_profile_cap from range_profile_cap[31:24])
+        signal = _extract_signal(expr)
-        sig_match = re.match(r'(\w+?)(?:\[|$)', expr)
+        if not signal:
-        if not sig_match:
             i += 1
             continue
 
-        signal = sig_match.group(1)
         start_byte = idx
         end_byte = idx
 
         # Find consecutive bytes of the same signal
         j = i + 1
         while j < len(entries):
-            next_idx, next_expr = entries[j]
+            _next_idx, next_expr = entries[j]
-            if next_expr.startswith(signal):
+            next_sig = _extract_signal(next_expr)
-                end_byte = next_idx
+            if next_sig == signal:
+                end_byte = _next_idx
                 j += 1
             else:
                 break

9_Firmware/tests/cross_layer/tb_cross_layer_ft2232h.v

@@ -620,8 +620,10 @@ module tb_cross_layer_ft2232h;
               "Data pkt: byte 7 = 0x56 (doppler_imag MSB)");
         check(captured_bytes[8] === 8'h78,
               "Data pkt: byte 8 = 0x78 (doppler_imag LSB)");
-        check(captured_bytes[9] === 8'h01,
+        // Byte 9 = {frame_start, 6'b0, cfar_detection}
-              "Data pkt: byte 9 = 0x01 (cfar_detection=1)");
+        // After reset sample_counter==0, so frame_start=1 → 0x81
+        check(captured_bytes[9] === 8'h81,
+              "Data pkt: byte 9 = 0x81 (frame_start=1, cfar_detection=1)");
         check(captured_bytes[10] === 8'h55,
               "Data pkt: byte 10 = 0x55 (footer)");
 

9_Firmware/tests/cross_layer/test_ddc_cosim_fuzz.py

@@ -0,0 +1,185 @@
+"""
+DDC Cosim Fuzz Runner (audit F-3.2)
+===================================
+Parameterized seed sweep over the existing DDC cosim testbench.
+
+For each seed the runner:
+  1. Generates a random plausible radar scene (1-4 targets, random range /
+     velocity / RCS, random noise level) via tb/cosim/radar_scene.py, using
+     the seed for full determinism.
+  2. Writes a temporary ADC hex file.
+  3. Compiles tb_ddc_cosim.v with -DSCENARIO_FUZZ (once, cached across seeds)
+     and runs vvp with +hex, +csv, +tag plusargs.
+  4. Parses the RTL output CSV and checks:
+       - non-empty output (the pipeline produced baseband samples)
+       - all I/Q values are within signed-18-bit range
+       - no NaN / parse errors
+       - sample count is within the expected bound from CIC decimation ratio
+
+The intent is liveness / crash-fuzz, not bit-exact cross-check. Bit-exact
+validation is covered by the static scenarios (single_target, multi_target,
+etc) in the existing suite. Fuzz complements that by surfacing edge-case
+corruption, saturation, or overflow on random-but-valid inputs.
+
+Marks:
+  - The default fuzz sweep uses 8 seeds for fast CI.
+  - Use `-m slow` to unlock the full 100-seed sweep matched to the audit ask.
+
+Compile + run times per seed on a laptop with iverilog 13: ~6 s. The default
+8-seed sweep fits in a ~1 minute pytest run; the 100-seed sweep takes ~10-12
+minutes.
+"""
+from __future__ import annotations
+
+import os
+import random
+import subprocess
+import sys
+import tempfile
+from pathlib import Path
+
+import pytest
+
+THIS_DIR = Path(__file__).resolve().parent
+REPO_ROOT = THIS_DIR.parent.parent.parent
+FPGA_DIR = REPO_ROOT / "9_Firmware" / "9_2_FPGA"
+COSIM_DIR = FPGA_DIR / "tb" / "cosim"
+
+sys.path.insert(0, str(COSIM_DIR))
+import radar_scene  # noqa: E402
+
+FAST_SEEDS = list(range(8))
+SLOW_SEEDS = list(range(100))
+
+# Pipeline constants
+N_ADC_SAMPLES = 16384
+CIC_DECIMATION = 4
+FIR_DECIMATION = 1
+EXPECTED_BB_MIN = N_ADC_SAMPLES // (CIC_DECIMATION * 4)   # pessimistic lower bound
+EXPECTED_BB_MAX = N_ADC_SAMPLES // CIC_DECIMATION         # upper bound before FIR drain
+SIGNED_18_MIN = -(1 << 17)
+SIGNED_18_MAX = (1 << 17) - 1
+
+SOURCE_FILES = [
+    "tb/tb_ddc_cosim.v",
+    "ddc_400m.v",
+    "nco_400m_enhanced.v",
+    "cic_decimator_4x_enhanced.v",
+    "fir_lowpass.v",
+    "cdc_modules.v",
+]
+
+
+@pytest.fixture(scope="module")
+def compiled_fuzz_vvp(tmp_path_factory):
+    """Compile tb_ddc_cosim.v once per pytest session with SCENARIO_FUZZ."""
+    iverilog = _iverilog_bin()
+    if not iverilog:
+        pytest.skip("iverilog not available on PATH")
+
+    out_dir = tmp_path_factory.mktemp("ddc_fuzz_build")
+    vvp = out_dir / "tb_ddc_cosim_fuzz.vvp"
+    sources = [str(FPGA_DIR / p) for p in SOURCE_FILES]
+    cmd = [
+        iverilog, "-g2001", "-DSIMULATION", "-DSCENARIO_FUZZ",
+        "-o", str(vvp), *sources,
+    ]
+    res = subprocess.run(cmd, cwd=FPGA_DIR, capture_output=True, text=True, check=False)
+    if res.returncode != 0:
+        pytest.skip(f"iverilog compile failed:\n{res.stderr}")
+    return vvp
+
+
+def _iverilog_bin() -> str | None:
+    from shutil import which
+    return which("iverilog")
+
+
+def _random_scene(seed: int) -> list[radar_scene.Target]:
+    rng = random.Random(seed)
+    n = rng.randint(1, 4)
+    return [
+        radar_scene.Target(
+            range_m=rng.uniform(50, 1500),
+            velocity_mps=rng.uniform(-40, 40),
+            rcs_dbsm=rng.uniform(-10, 20),
+            phase_deg=rng.uniform(0, 360),
+        )
+        for _ in range(n)
+    ]
+
+
+def _run_seed(seed: int, vvp: Path, work: Path) -> tuple[int, list[tuple[int, int]]]:
+    """Generate stimulus, run the DUT, return (bb_sample_count, [(i,q)...])."""
+    targets = _random_scene(seed)
+    noise = random.Random(seed ^ 0xA5A5).uniform(0.5, 6.0)
+    adc = radar_scene.generate_adc_samples(
+        targets, N_ADC_SAMPLES, noise_stddev=noise, seed=seed
+    )
+
+    hex_path = work / f"adc_fuzz_{seed:04d}.hex"
+    csv_path = work / f"rtl_bb_fuzz_{seed:04d}.csv"
+    radar_scene.write_hex_file(str(hex_path), adc, bits=8)
+
+    vvp_bin = _vvp_bin()
+    if not vvp_bin:
+        pytest.skip("vvp not available")
+
+    cmd = [
+        vvp_bin, str(vvp),
+        f"+hex={hex_path}",
+        f"+csv={csv_path}",
+        f"+tag=seed{seed:04d}",
+    ]
+    res = subprocess.run(cmd, cwd=FPGA_DIR, capture_output=True, text=True, check=False, timeout=120)
+    assert res.returncode == 0, f"vvp exit={res.returncode}\nstdout:\n{res.stdout}\nstderr:\n{res.stderr}"
+    assert csv_path.exists(), (
+        f"vvp completed rc=0 but CSV was not produced at {csv_path}\n"
+        f"cmd: {cmd}\nstdout:\n{res.stdout[-2000:]}\nstderr:\n{res.stderr[-500:]}"
+    )
+
+    rows = []
+    with csv_path.open() as fh:
+        header = fh.readline()
+        assert "baseband_i" in header and "baseband_q" in header, f"unexpected CSV header: {header!r}"
+        for line in fh:
+            parts = line.strip().split(",")
+            if len(parts) != 3:
+                continue
+            _, i_str, q_str = parts
+            rows.append((int(i_str), int(q_str)))
+    return len(rows), rows
+
+
+def _vvp_bin() -> str | None:
+    from shutil import which
+    return which("vvp")
+
+
+def _fuzz_assertions(seed: int, rows: list[tuple[int, int]]) -> None:
+    n = len(rows)
+    assert EXPECTED_BB_MIN <= n <= EXPECTED_BB_MAX, (
+        f"seed {seed}: bb sample count {n} outside [{EXPECTED_BB_MIN},{EXPECTED_BB_MAX}]"
+    )
+    for idx, (i, q) in enumerate(rows):
+        assert SIGNED_18_MIN <= i <= SIGNED_18_MAX, (
+            f"seed {seed} row {idx}: baseband_i={i} out of signed-18 range"
+        )
+        assert SIGNED_18_MIN <= q <= SIGNED_18_MAX, (
+            f"seed {seed} row {idx}: baseband_q={q} out of signed-18 range"
+        )
+    all_zero = all(i == 0 and q == 0 for i, q in rows)
+    assert not all_zero, f"seed {seed}: all-zero baseband output — pipeline likely stalled"
+
+
+@pytest.mark.parametrize("seed", FAST_SEEDS)
+def test_ddc_fuzz_fast(seed: int, compiled_fuzz_vvp: Path, tmp_path: Path) -> None:
+    _, rows = _run_seed(seed, compiled_fuzz_vvp, tmp_path)
+    _fuzz_assertions(seed, rows)
+
+
+@pytest.mark.slow
+@pytest.mark.parametrize("seed", SLOW_SEEDS)
+def test_ddc_fuzz_full(seed: int, compiled_fuzz_vvp: Path, tmp_path: Path) -> None:
+    _, rows = _run_seed(seed, compiled_fuzz_vvp, tmp_path)
+    _fuzz_assertions(seed, rows)

CONTRIBUTING.md

@@ -5,140 +5,109 @@ for getting a change reviewed and merged.
 
 ## Getting started
 
-1. Fork the repository and create a topic branch from `develop`.
+1. Fork the repository and create a topic branch from `develop`. The `main` branch is for production releases only.
-2. Keep generated outputs (Vivado projects, bitstreams, build logs)
+2. Keep generated outputs (Vivado projects, bitstreams, build logs) out of version control.
-   out of version control — the `.gitignore` already covers most of
+
-   these.
+### Security Mandate: Package Installation
+Due to supply chain attack risks, **ALL package installations MUST use the `sfw` (secure firewall) prefix**.
+- Python: `sfw uv pip install <package>` (Do not use raw pip)
+- Node/JS: `sfw npm install <package>`
+- Rust/Cargo: `sfw cargo <command>`
+
+Never run bare package installation commands without the `sfw` prefix.
 
 ## Repository layout
 
 | Path | Contents |
 |------|----------|
 | `4_Schematics and Boards Layout/` | KiCad schematics, Gerbers, BOM/CPL |
+| `9_Firmware/9_1_Microcontroller/` | STM32 MCU C/C++ firmware and unit tests |
 | `9_Firmware/9_2_FPGA/` | Verilog RTL, constraints, testbenches, build scripts |
-| `9_Firmware/9_2_FPGA/formal/` | SymbiYosys formal-verification wrappers |
+| `9_Firmware/9_3_GUI/` | Python radar dashboard (Tkinter/PyQt6) and CLI tools |
-| `9_Firmware/9_2_FPGA/scripts/` | Vivado TCL build & debug scripts |
+| `9_Firmware/tests/cross_layer/` | Python-based system invariant/contract tests |
-| `9_Firmware/9_3_GUI/` | Python radar dashboard (Tkinter + matplotlib) |
 | `docs/` | GitHub Pages documentation site |
 
-## Before submitting a pull request
+## Code Standards & Tooling
 
-- **Python** — verify syntax: `python3 -m py_compile <file>`
+- **Python (GUI, Scripts, Tests)**:
-- **Verilog** — if you have Vivado, run the relevant `build*.tcl`;
+  - We use `uv` for dependency management.
-  if not, note which scripts your change affects
+  - We strictly enforce linting with `ruff`. Run `uv run ruff check .` before committing.
-- **Whitespace** — `git diff --check` should be clean
+  - Test with `pytest`.
-- Keep PRs focused: one logical change per PR is easier to review
+- **Verilog (FPGA)**:
-- **Run the regression tests** (see below)
+  - The RTL (`radar_system_top.v`) is the single source of truth for opcode values, bit widths, reset defaults, and valid ranges.
+  - Testbenches must include **adversarial validation**: actively test boundary conditions, race conditions, unexpected input sequences, and reset mid-operation.
+  - Use `iverilog` for simulation.
+- **C/C++ (MCU)**:
+  - Use `make test` for host-side unit testing (cpputest).
+- **System-Level Invariants**:
+  - Whenever adding code, verify that system-level invariants (across module, process, and chip boundaries) hold true.
 
-## Running regression tests
+## AI Usage Policy
 
-After any change, run the relevant test suites to verify nothing is
+The use of AI is permitted but we have to make sure that the quality and control of the codebase doesn't depend on the agents but the maintainer pushing the changes, meaning they are fully responsible for the code they commit.
-broken. All commands assume you are at the repository root.
 
-### Prerequisites
+1. **Human Accountability** — The committing engineer is fully responsible for AI-generated code as if they wrote it. Every PR must be understood and defensible by a human.
+2. **Mandatory Review** — No raw AI output may be committed unread. AI code must pass the same review bar as hand-written code.
+3. **Full CI Before Commit** — All AI-assisted changes must pass the complete CI suite locally (lint, unit, regression, cross-layer) before commit.
 
-| Tool | Used by | Install |
+## Running the Test Suites
-|------|---------|---------|
-| [Icarus Verilog](http://iverilog.icarus.com/) (`iverilog`) | FPGA regression | `brew install icarus-verilog` / `apt install iverilog` |
-| Python 3.8+ | GUI tests, co-sim | Usually pre-installed |
-| GNU Make | MCU tests | Usually pre-installed |
-| [SymbiYosys](https://symbiyosys.readthedocs.io/) (`sby`) | Formal verification | Optional — see SymbiYosys docs |
 
-### FPGA regression (RTL lint + unit/integration/signal-processing tests)
+We use GitHub Actions for CI, which runs four main jobs on every PR. Run these locally before pushing.
 
+### 1. Python & Linting
+```bash
+uv run ruff check .
+cd 9_Firmware/9_3_GUI
+uv run pytest test_GUI_V65_Tk.py test_v7.py -v
+```
+
+### 2. FPGA Regression
 ```bash
 cd 9_Firmware/9_2_FPGA
 bash run_regression.sh
 ```
+This runs five phases (Lint, Changed Modules, Integration, Signal Processing, Infrastructure, and **P0 Adversarial Tests**). All must pass.
 
-This runs four phases:
+### 3. MCU Unit Tests
-
-| Phase | What it checks |
-|-------|----------------|
-| 0 — Lint | `iverilog -Wall` on all production RTL + static regex checks |
-| 1 — Changed Modules | Unit tests for individual blocks (CIC, Doppler, CFAR, etc.) |
-| 2 — Integration | DDC chain, receiver golden-compare, system-top, end-to-end |
-| 3 — Signal Processing | FFT engine, NCO, FIR, matched filter chain |
-| 4 — Infrastructure | CDC modules, edge detector, USB interface, range-bin decimator, mode controller |
-
-All tests must pass (exit code 0). Advisory lint warnings (e.g., `case
-without default`) are non-blocking.
-
-### MCU unit tests
-
 ```bash
 cd 9_Firmware/9_1_Microcontroller/tests
-make clean && make all
+make clean && make
 ```
 
-Runs 20 C-based unit tests covering safety, bug-fix, and gap-3 tests.
+### 4. Cross-Layer Contract Tests
-Every test binary must exit 0.
-
-### GUI / dashboard tests
-
 ```bash
-cd 9_Firmware/9_3_GUI
+uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py -v
-python3 -m pytest test_GUI_V65_Tk.py -v
-# or without pytest:
-python3 -m unittest test_GUI_V65_Tk -v
 ```
 
-57+ protocol and rendering tests. The `test_record_and_stop` test
+## Before merging: CI checklist
-requires `h5py` and will be skipped if it is not installed.
 
-### Co-simulation (Python vs RTL golden comparison)
+All PRs must pass CI:
 
-Run from the co-sim directory after a successful FPGA regression (the
+| Job | What it checks |
-regression generates the RTL CSV outputs that the co-sim scripts compare
+|----|---------------|
-against):
+| `python-tests` | ruff clean + pytest green |
+| `mcu-tests` | make all exits 0 |
+| `fpga-regression` | run_regression.sh exits 0 |
+| `cross-layer-tests` | pytest exits 0 |
 
-```bash
+## Important Notes
-cd 9_Firmware/9_2_FPGA/tb/cosim
 
-# Validate all .mem files (twiddles, chirp ROMs, addressing)
+- **NO LEGACY COMPATIBILITY** unless explicitly requested by the maintainer.
-python3 validate_mem_files.py
+- **The FPGA RTL (`radar_system_top.v`) is the single source of truth** for opcode values, bit widths, reset defaults, and valid ranges. All other layers must align to it.
+- **Adversarial testing is mandatory**: Every test must actively try to break the code.
+- **Testbench timing**: Always add a `#1` delay after `@(posedge clk)` before driving DUT inputs with blocking assignments.
+- **Pre-fetch FIFO**: Remember `wr_full` is asserted after DEPTH+1 writes, not just DEPTH.
 
-# DDC chain: RTL vs Python model (5 scenarios)
+## Checklist Before Push
-python3 compare.py dc
-python3 compare.py single_target
-python3 compare.py multi_target
-python3 compare.py noise_only
-python3 compare.py sine_1mhz
 
-# Doppler processor: RTL vs golden reference
+- [ ] `uv run ruff check .` — no lint errors
-python3 compare_doppler.py stationary
+- [ ] `uv run pytest test_GUI_V65_Tk.py test_v7.py -v` — all pass
-
+- [ ] `cd 9_Firmware/9_2_FPGA && bash run_regression.sh` — all 5 phases pass
-# Matched filter: RTL vs Python model (4 scenarios)
+- [ ] `cd 9_Firmware/9_1_Microcontroller/tests && make clean && make` — pass
-python3 compare_mf.py all
+- [ ] `uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py` — pass
-```
+- [ ] `git diff --check` — no whitespace issues
-
+- [ ] PR targets `develop` branch
-Each script prints PASS/FAIL per scenario and exits non-zero on failure.
-
-### Formal verification (optional)
-
-Requires SymbiYosys (`sby`), Yosys, and a solver (z3 or boolector):
-
-```bash
-cd 9_Firmware/9_2_FPGA/formal
-sby -f fv_doppler_processor.sby
-sby -f fv_radar_mode_controller.sby
-```
-
-### Quick checklist
-
-Before pushing, confirm:
-
-1. `bash run_regression.sh` — all phases pass
-2. `make all` (MCU tests) — 20/20 pass
-3. `python3 -m unittest test_GUI_V65_Tk -v` — all pass
-4. `python3 validate_mem_files.py` — all checks pass
-5. `python3 compare.py dc && python3 compare_doppler.py stationary && python3 compare_mf.py all`
-6. `git diff --check` — no whitespace issues
-
-## Areas where help is especially welcome
-
-See the list in [README.md](README.md#-contributing).
 
 ## Questions?
 
-Open a GitHub issue — that way the discussion is visible to everyone.
+Open a GitHub issue — discussion is visible to everyone.

README.md

@@ -7,7 +7,6 @@
 [![Frequency: 10.5GHz](https://img.shields.io/badge/Frequency-10.5GHz-blue)](https://github.com/NawfalMotii79/PLFM_RADAR)
 [![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg)](https://github.com/NawfalMotii79/PLFM_RADAR/pulls)
 
-![AERIS-10 Radar System](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/3fb1dabf-2c6d-4b5d-b471-48bc461ce914.jpg)
 
 AERIS-10 is an open-source, low-cost 10.5 GHz phased array radar system featuring Pulse Linear Frequency Modulated (LFM) modulation. Available in two versions (3km and 20km range), it's designed for researchers, drone developers, and serious SDR enthusiasts who want to explore and experiment with phased array radar technology.
 
@@ -47,13 +46,13 @@ The AERIS-10 main sub-systems are:
 
 - **Main Board** containing:
   - **DAC** - Generates the RADAR Chirps
-  - **2x Microwave Mixers (LT5552)** - For up-conversion and IF-down-conversion
+  - **2x Microwave Mixers (LTC5552)** - For up-conversion and IF-down-conversion
   - **4x 4-Channel Phase Shifters (ADAR1000)** - For RX and TX chain beamforming
   - **16x Front End Chips (ADTR1107)** - Used for both Low Noise Amplifying (RX) and Power Amplifying (TX) stages
   - **XC7A50T FPGA** - Handles RADAR Signal Processing on the upstream FTG256 board:
     - PLFM Chirps generation via the DAC
     - Raw ADC data read
-    - Digital Gain Control (host-configurable gain shift)
+    - Hybrid Automatic Gain Control (AGC) — cross-layer FPGA/STM32/GUI loop
     - I/Q Baseband Down-Conversion
     - Decimation
     - Filtering
@@ -92,7 +91,7 @@ The AERIS-10 main sub-systems are:
 ### Processing Pipeline
 
 1. **Waveform Generation** - DAC creates LFM chirps
-2. **Up/Down Conversion** - LT5552 mixers handle frequency translation
+2. **Up/Down Conversion** - LTC5552 mixers handle frequency translation
 3. **Beam Steering** - ADAR1000 phase shifters control 16 elements
 4. **Signal Processing (FPGA)**:
    - Raw ADC data capture
@@ -111,7 +110,8 @@ The AERIS-10 main sub-systems are:
    - Map integration
    - Radar control interface
 
-![AERIS-10 GUI Demo](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/GUI_V6.gif)
+![AERIS-10 Dashboard](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/GUI_V6.gif)
+<!-- V6 GIF removed — V6 is deprecated. V65 Tk and V7 PyQt6 are the active GUIs. -->
 
 ## 📊 Technical Specifications
 

docs/index.html

@@ -32,6 +32,11 @@
     </section>
 
     <section class="stats-grid">
+      <article class="card stat notice">
+        <h2>Production Board USB</h2>
+        <p class="metric">FT2232H (USB 2.0)</p>
+        <p class="muted">50T production board uses FT2232H. FT601 USB 3.0 is available on 200T premium dev board only.</p>
+      </article>
       <article class="card stat">
         <h2>Tracked Timing Baseline</h2>
         <p class="metric">WNS +0.058 ns</p>

pyproject.toml

@@ -19,6 +19,11 @@ dev = [
 # ---------------------------------------------------------------------------
 # Ruff configuration
 # ---------------------------------------------------------------------------
+[tool.pytest.ini_options]
+markers = [
+    "slow: full-sweep tests (opt-in via -m slow); audit F-3.2 100-seed fuzz",
+]
+
 [tool.ruff]
 target-version = "py312"
 line-length = 100

uv.lock

@@ -0,0 +1,216 @@
+version = 1
+revision = 1
+requires-python = ">=3.12"
+
+[[package]]
+name = "aeris-10-radar"
+version = "1.0.0"
+source = { virtual = "." }
+
+[package.dev-dependencies]
+dev = [
+    { name = "h5py" },
+    { name = "numpy" },
+    { name = "pytest" },
+    { name = "ruff" },
+]
+
+[package.metadata]
+
+[package.metadata.requires-dev]
+dev = [
+    { name = "h5py", specifier = ">=3.10" },
+    { name = "numpy", specifier = ">=1.26" },
+    { name = "pytest", specifier = ">=8" },
+    { name = "ruff", specifier = ">=0.5" },
+]
+
+[[package]]
+name = "colorama"
+version = "0.4.6"
+source = { registry = "https://pypi.org/simple" }
+sdist = { url = "https://files.pythonhosted.org/packages/d8/53/6f443c9a4a8358a93a6792e2acffb9d9d5cb0a5cfd8802644b7b1c9a02e4/colorama-0.4.6.tar.gz", hash = "sha256:08695f5cb7ed6e0531a20572697297273c47b8cae5a63ffc6d6ed5c201be6e44", size = 27697 }
+wheels = [
+    { url = "https://files.pythonhosted.org/packages/d1/d6/3965ed04c63042e047cb6a3e6ed1a63a35087b6a609aa3a15ed8ac56c221/colorama-0.4.6-py2.py3-none-any.whl", hash = "sha256:4f1d9991f5acc0ca119f9d443620b77f9d6b33703e51011c16baf57afb285fc6", size = 25335 },
+]
+
+[[package]]
+name = "h5py"
+version = "3.16.0"
+source = { registry = "https://pypi.org/simple" }
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