Added BOM and Gerbers

BOM and Gerbers, ready to be sent to PCB manufacturer

4_Schematics and Boards Layout/4_7_Production Files/Gerber_Main_Board/RADAR_Main_Board.csv

@@ -0,0 +1,105 @@
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+"2";"22pF";"CC0201";"C0201";"C308, C309";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"C";"";"";
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+"2";"7.8pF";"CC0201";"C0201";"C61, C62";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"C";"";"";
+"1";"830R";"R-EU_R0402";"R0402";"R36";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"";"";"";"";"R";"";"";
+"4";"840R";"RR0201";"R0201";"R78, R79, R80, R81";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"R";"";"";
+"2";"AD8352ACPZ-R7";"AD8352ACPZ-R7";"CP_16_3_ADI";"U4, U8";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.analog.com/media/en/technical-documentation/data-sheets/ad8352.pdf";"2 GHz Ultralow Distortion Differential RF/IF Amplifier";"";"Analog Devices Inc";"AD8352ACPZ-R7";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"AD9484BCPZ-500";"AD9484BCPZ-500";"CP_56_5_ADI";"U1";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.analog.com/media/en/technical-documentation/data-sheets/AD9484.pdf";"8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter";"";"Analog Devices Inc";"AD9484BCPZ-500";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"AD9708AR";"AD9708AR";"RW_28_ADI";"U3";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"AD9708AR";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"4";"ADAR1000ACCZN";"ADAR1000ACCZN";"CC-88-1_ADI";"ADAR1_, ADAR2_, ADAR3_, ADAR4_";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"ADAR1000ACCZN";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"RF";"";
+"3";"ADS7830IPWR";"ADS7830IPWR";"PW16";"U10, U88, U89";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/ads7830";"8-Bit, 8-Channel Sampling A/D Converter with I2C Interface 16-TSSOP -40 to 85";"";"Texas Instruments";"ADS7830IPWR";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"16";"ADTR1107ACCZ";"ADTR1107ACCZ";"CC-24-8_ADI";"ADTR1107_1, ADTR1107_2, ADTR1107_3, ADTR1107_4, ADTR1107_5, ADTR1107_6, ADTR1107_7, ADTR1107_8, ADTR1107_9, ADTR1107_10, ADTR1107_11, ADTR1107_12, ADTR1107_13, ADTR1107_14, ADTR1107_15, ADTR1107_16";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"ADTR1107ACCZ";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"RF";"";
+"1";"AT93C46A-10SQ-2.7";"AT93C46A-10SQ-2.7";"SOIC8";"IC1";"Three-wire Automotive Temperature Serial EEPROM 1K (64 x 16)";"";"";"";"";"";"";"";"";"";"";"";"";"";"AT93C46DN-SH-B";"1455086";"58M3879";"";"0";"";"";"";"";"";"";"";"";
+"5";"BLM15HB121SN1";"BLM15HB121SN1";"0402";"L5, L6, L7, L19, L20";"EMIFIL (R) Chip Ferrite Bead for GHz Noise";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"";"";"";"";"";"";"";
+"2";"BPF2";"BPF2";"BPF2";"U$2, U$3";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"4";"Blue";"LED-BLUE0603";"LED-0603";"D2, D3, D4, D5";"Blue SMD LED";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"DIO-08575";"";"";"";"";"";"Blue";
+"2";"CJT-T-P-HH-ST-TH1";"CJT-T-P-HH-ST-TH1";"CJTTPHHSTTH1";"J19, J21";"Conn Twinax F 0Hz to 4GHz 100Ohm Solder ST Thru-Hole Gold";"";"";"";"";"Conn Twinax F 0Hz to 4GHz 100Ohm Solder ST Thru-Hole Gold";"7.31mm";"SAMTEC";"CJT-T-P-HH-ST-TH1";"";"";"200-CJTTPHHSTTH1";"https://www.mouser.co.uk/ProductDetail/Samtec/CJT-T-P-HH-ST-TH1?qs=PB6%2FjmICvI3dfW8RDpxn0g%3D%3D";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"2";"DAC5578SRGET";"DAC5578SRGET";"RGE24_2P7X2P7";"U7, U69";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/dac5578";"8-bit, Octal Channel, Ultra-Low Glitch, Voltage Output, 2-Wire Interface DAC 24-VQFN -40 to 125";"";"Texas Instruments";"DAC5578SRGET";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"ECS-120-10-36B2-JTN-TR";"CRYSTAL-12MHZ";"CRYSTAL-SMD-2X2.5MM";"Y1";"12.0MHz Crystal";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"XTAL-15540";"";"";"";"";"";"";
+"1";"EP4RKU+";"EP4RKU+";"DG1677-2_MNC";"U16";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"EP4RKU+";"";"Mini Circuits";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"FT2232HQ";"FT2232HQ";"64QFN_FT2232HQ_FTD";"U6";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"";"";"FT2232HQ";"";"FTDI, Future Technology Devices International Ltd";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"16";"INA241A3IDGKRDGK0008A-MFG";"INA241A3IDGKRDGK0008A-MFG";"DGK0008A-MFG";"U11, U73, U74, U75, U76, U77, U78, U79, U80, U81, U82, U83, U84, U85, U86, U87";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"-5-V to 110-V bidirectional ultraprecise current sense amplifier with enhanced PWM rejection 8-VSSOP -40 to 125";"";"Texas Instruments";"INA241A3IDGKR";"";"";"";"";"";"";"";"";"";"";"";"";"RefDes";"";"";"";"TYPE";"";
+"2";"LTC5552IUDBTRMPBF";"LTC5552IUDBTRMPBF";"UDB_12_ADI";"U5, U13";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"LTC5552IUDB#TRMPBF";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"17";"M3SWA2-34DR+";"M3SWA2-34DR+";"16_QFN";"RF_SW_1, RF_SW_2, RF_SW_3, RF_SW_4, RF_SW_5, RF_SW_6, RF_SW_7, RF_SW_8, RF_SW_9, RF_SW_10, RF_SW_11, RF_SW_12, RF_SW_13, RF_SW_14, RF_SW_15, RF_SW_16, U$1";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"2";"MINI-USB-32005-201";"MINI-USB-32005-201";"32005-201";"X2, X53";"MINI USB-B Conector";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"unknown";"unknown";"";"5";"";"";"";"";"";"";"";"";
+"1";"MOMENTARY-SWITCH-SPST-SMD-4.6X2.8MM";"MOMENTARY-SWITCH-SPST-SMD-4.6X2.8MM";"TACTILE_SWITCH_SMD_4.6X2.8MM";"S1";"Momentary Switch (Pushbutton) - SPST";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"SWCH-15606";"";"";"";"";"";"";
+"1";"MT25QL01GBBB8E12-0AUT";"MT25QL01GBBB8E12-0AUT";"BGA24_MT25QL_MRN";"U9";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"MT25QL01GBBB8E12-0AUT";"";"Micron";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"NX3215SA-32.768KHz";"NX3225GD-8MHZ-STD-CRA-3";"XTAL_NX3225GD-8MHZ-STD-CRA-3_N";"XTAL3";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"NX3225GD-8MHZ-STD-CRA-3";"";"NDK";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"NX3225GD-8MHZ-STD-CRA-3";"NX3225GD-8MHZ-STD-CRA-3";"XTAL_NX3225GD-8MHZ-STD-CRA-3_N";"XTAL1";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"NX3225GD-8MHZ-STD-CRA-3";"";"NDK";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"4";"OPA4703EA/250";"OPA4703EA/250";"PW14";"OPA_1, OPA_2, OPA_3, OPA_4";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/opa4703";"Quad, 12-V, 1-MHz, low-offset operational amplifier 14-TSSOP -40 to 85";"";"Texas Instruments";"OPA4703EA/250";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"STM32F746ZGT7";"STM32F746ZGT7";"LQFP-144_STM";"U2";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"STM32F746ZGT7";"";"STMicroelectronics";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"34";"SZMMSZ5232BT1G";"SZMMSZ5232BT1G";"SOD-123_ONS";"U14, U15, U17, U37, U38, U39, U40, U41, U43, U44, U45, U46, U47, U48, U49, U50, U51, U52, U53, U54, U55, U56, U57, U58, U59, U60, U61, U62, U63, U64, U65, U66, U67, U68";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"SZMMSZ5232BT1G";"";"onsemi";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"XC7A50T-2FTG256I";"XC7A50T-2FTG256I";"BGA256C100P16X16_1700X1700X155";"U42";"Artix-7 Field Programmable Gate Array (FPGA) IC 170 2764800 52160 256-LBGA  Check availability";"In Stock";"https://www.snapeda.com/parts/XC7A50T-2FTG256I/Xilinx/view-part/?ref=eda";"";"";"                                                      Artix-7 Field Programmable Gate Array (FPGA) IC 170 2764800 52160 256-LBGA                                              ";"";"";"";"Xilinx Inc.";"";"";"";"XC7A50T-2FTG256I";"";"";"";"LBGA-256 Xilinx Inc.";"";"None";"";"";"https://www.snapeda.com/parts/XC7A50T-2FTG256I/Xilinx/view-part/?ref=snap";"";"";"";"";

4_Schematics and Boards Layout/4_7_Production Files/Gerber_Main_Board/RADAR_Main_Board.dri

@@ -1,8 +1,8 @@
 Generated by EAGLE CAM Processor 7.4.0
 
-Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.dri
+Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Prod_V2/RADAR_Main_Board.dri
 
- Date              : 06/04/2026 22:10
+ Date              : 19/04/2026 23:21
  Drills            : generated
  Device            : Excellon drill station, coordinate format 2.5 inch
 
@@ -27,8 +27,8 @@ Drills used:
 
  Code  Size       used
 
- T01   0.0059inch  1609
+ T01   0.0059inch  1604
- T02   0.0079inch  1892
+ T02   0.0079inch  2243
  T03   0.0100inch    18
  T04   0.0118inch   355
  T05   0.0138inch   113
@@ -43,8 +43,8 @@ Drills used:
  T14   0.0472inch     4
  T15   0.1260inch     8
 
-Total number of drills: 4438
+Total number of drills: 4784
 
 Plotfiles:
 
- C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.drd
+ C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Prod_V2/RADAR_Main_Board.drd

4_Schematics and Boards Layout/4_7_Production Files/Gerber_Main_Board/RADAR_Main_Board.gpi

@@ -1,9 +1,9 @@
 Generated by EAGLE CAM Processor 7.4.0
 
-Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.gpi
+Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Prod_V2/RADAR_Main_Board.gpi
 
- Date              : 06/04/2026 22:41
+ Date              : 19/04/2026 23:50
- Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.bsk
+ Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Prod_V2/RADAR_Main_Board.bsk
  Apertures         : generated: 
  Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch
 

4_Schematics and Boards Layout/4_7_Production Files/Gerber_PA/RF_PA.L1

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 D32*
 X0076000Y0051197D03*

4_Schematics and Boards Layout/4_7_Production Files/Gerber_PA/RF_PA.L2

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4_Schematics and Boards Layout/4_7_Production Files/Gerber_PA/RF_PA.L3

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4_Schematics and Boards Layout/4_7_Production Files/Gerber_PA/RF_PA.drd

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4_Schematics and Boards Layout/4_7_Production Files/Gerber_PA/RF_PA.dri

@@ -2,14 +2,14 @@ Generated by EAGLE CAM Processor 7.4.0
 
 Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerAmplifierBoard/RF_PA.dri
 
- Date              : 05/04/2026 00:08
+ Date              : 19/04/2026 01:42
  Drills            : generated
  Device            : Excellon drill station, coordinate format 2.5 inch
 
 Parameter settings:
 
- Tolerance Drill + :  2.50 %
+ Tolerance Drill + :  0.00 %
- Tolerance Drill - :  2.50 %
+ Tolerance Drill - :  0.00 %
  Rotate            : no
  Mirror            : no
  Optimize          : yes
@@ -27,7 +27,7 @@ Drills used:
 
  Code  Size       used
 
- T01   0.0059inch   103
+ T01   0.0059inch   128
  T02   0.0079inch    24
  T03   0.0138inch   215
  T04   0.0394inch     5
@@ -35,7 +35,7 @@ Drills used:
  T06   0.0520inch     2
  T07   0.1260inch     7
 
-Total number of drills: 364
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 Plotfiles:
 

4_Schematics and Boards Layout/4_7_Production Files/Gerber_PA/RF_PA.gpi

@@ -2,7 +2,7 @@ Generated by EAGLE CAM Processor 7.4.0
 
 Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerAmplifierBoard/RF_PA.gpi
 
- Date              : 05/04/2026 00:07
+ Date              : 19/04/2026 01:42
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  Apertures         : generated: 
  Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch

4_Schematics and Boards Layout/4_7_Production Files/Gerber_PowerBoard/PowerBoard.bsk

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@@ -0,0 +1,29 @@
+"Qty";"Value";"Device";"Package";"Parts";"Description";"COPYRIGHT";"DATASHEET";"DESCRIPTION";"HEIGHT";"MANUFACTURER_NAME";"MANUFACTURER_PART_NUMBER";"MF";"MFR_NAME";"MOUSER_PART_NUMBER";"MOUSER_PRICE-STOCK";"MPN";"OC_FARNELL";"OC_NEWARK";"POPULARITY";"REFDES";"SPICEPREFIX";"TYPE";
+"1";"";"AK300/2";"AK300/2";"X1";"CONNECTOR";"";"";"";"";"";"";"";"";"";"";"";"unknown";"unknown";"16";"";"";"";
+"1";"";"MA10-2";"MA10-2";"SV1";"PIN HEADER";"";"";"";"";"";"";"";"";"";"";"";"unknown";"unknown";"3";"";"";"";
+"21";"0.1µF";"C-EUC0805";"C0805";"C1, C6, C12, C18, C29, C30, C36, C42, C54, C60, C66, C71, C76, C77, C83, C89, C109, C119, C129, C144, C154";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"88";"";"C";"";
+"27";"10k";"R-EU_M0805";"M0805";"R2, R4, R6, R8, R10, R12, R14, R16, R18, R20, R22, R24, R26, R28, R30, R32, R34, R36, R38, R40, R42, R44, R46, R48, R50, R52, R56";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"4";"10nF";"C-EUC0603";"C0603";"C150, C152, C160, C162";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"73";"";"C";"";
+"4";"10µF";"C-EUC0603";"C0603";"C151, C153, C161, C163";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"73";"";"C";"";
+"60";"10µF";"C-EUC0805";"C0805";"C4, C5, C9, C10, C15, C16, C21, C22, C24, C25, C28, C33, C34, C39, C40, C45, C46, C50, C51, C52, C53, C57, C58, C63, C64, C69, C70, C74, C75, C80, C81, C86, C87, C92, C93, C94, C95, C108, C112, C113, C114, C115, C118, C122, C123, C124, C125, C128, C132, C133, C134, C135, C138, C139, C140, C143, C147, C148, C157, C158";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"88";"";"C";"";
+"2";"11.5k";"R-EU_M0805";"M0805";"R54, R58";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"4";"12k";"R-EU_M0805";"M0805";"R9, R35, R43, R47";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"13.7k";"R-EU_M0805";"M0805";"R3";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"12";"1µF";"C-EUC0805";"C0805";"C26, C27, C106, C107, C116, C117, C126, C127, C136, C137, C141, C142";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"88";"";"C";"";
+"2";"2.2µH";"POWER_INDUCTOR";"IND_VLP8040T-1R0N_TDK";"U$1, U$2";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"35";"22-23-2021";"22-23-2021";"22-23-2021";"X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, X32, X33, X34, X35, X36";".100" (2.54mm) Center Header - 2 Pin";"";"";"";"";"";"";"MOLEX";"";"";"";"22-23-2021";"1462926";"25C3832";"40";"";"";"";
+"52";"22µF";"C-EUC0603";"C0603";"C2, C3, C7, C8, C11, C13, C14, C17, C19, C20, C23, C31, C32, C35, C37, C38, C41, C43, C44, C47, C48, C49, C55, C56, C59, C61, C62, C65, C67, C68, C72, C73, C78, C79, C82, C84, C85, C88, C90, C91, C110, C111, C120, C121, C130, C131, C145, C146, C149, C155, C156, C159";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"73";"";"C";"";
+"1";"23.4k";"R-EU_M0805";"M0805";"R49";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"2k";"R-EU_M0805";"M0805";"R39";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"3.09k";"R-EU_M0805";"M0805";"R1";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"19";"3.3µH";"POWER_INDUCTOR";"IND_VLP8040T-1R0N_TDK";"U$3, U$4, U$5, U$6, U$7, U$8, U$9, U$10, U$11, U$12, U$13, U$14, U$15, U$16, U$17, U$18, U$19, U$20, U$21";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"6";"32.2k";"R-EU_M0805";"M0805";"R5, R7, R11, R13, R15, R19";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"34.8k";"R-EU_M0805";"M0805";"R21";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"2";"35.7k";"R-EU_M0805";"M0805";"R53, R57";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"11";"56.2k";"R-EU_M0805";"M0805";"R17, R23, R25, R27, R29, R31, R37, R41, R45, R51, R55";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"61.9k";"R-EU_M0805";"M0805";"R33";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"6";"ADM7151ACPZ-04-R7";"ADM7151ACPZ-04-R7";"CP_8_11_ADI";"U5, U23, U25, U27, U29, U30";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.analog.com/media/en/technical-documentation/data-sheets/ADM7151.pdf";"800 mA Ultralow Noise, High PSRR, RF Linear Regulator";"";"Analog Devices Inc";"ADM7151ACPZ-04-R7";"";"";"";"";"";"";"";"";"";"";"";
+"5";"LM2662MX/NOPB";"LM2662MX/NOPB";"M08A";"U18, U19, U20, U21, U22";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"LM2662MX/NOPB";"";"Texas Instruments";"";"";"";"";"";"";"";"";"LM2662M";
+"10";"T521W476M020ATE045";"T521W476M020ATE045";"T521W";"C96, C97, C98, C99, C100, C101, C102, C103, C104, C105";"T521, Tantalum, Polymer Tantalum, Commercial Grade, 47 uF, 20%, 20 VDC, 105C, -55C, 105C, SMD, Polymer, Molded, Low Profile/ESR, NonCombustible, 2,000 Hrs, 9 % , 45 mOhms, 94 uA, 222.95 mg, 7343, 1.4mm, Height Max = 1.5mm, 1000, 52  Weeks";"";"";"T521, Tantalum, Polymer Tantalum, Commercial Grade, 47 uF, 20%, 20 VDC, 105C, -55C, 105C, SMD, Polymer, Molded, Low Profile/ESR, NonCombustible, 2,000 Hrs, 9 % , 45 mOhms, 94 uA, 222.95 mg, 7343, 1.4mm, Height Max = 1.5mm, 1000, 52  Weeks";"1.5mm";"KEMET";"T521W476M020ATE045";"";"";"80-T521W476M20ATE045";"https://www.mouser.co.uk/ProductDetail/KEMET/T521W476M020ATE045?qs=Ad%252Bh9aq9FyVtchBw1jwoFA%3D%3D";"";"";"";"";"";"";"";
+"21";"TPS562208DDCT";"TPS562208DDCT";"DDC0006A_N";"U1, U2, U3, U4, U6, U7, U8, U9, U10, U11, U12, U13, U14, U15, U16, U17, U24, U26, U28, U31, U33";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/tps562208";"4.5 V to 17 V input, 2 A output, synchronous step-down converter in FCCM mode 6-SOT-23-THIN -40 to 125";"";"Texas Instruments";"TPS562208DDCT";"";"";"";"";"";"";"";"";"RefDes";"";"TYPE";
+"2";"TPS7A8300RGRR";"TPS7A8300RGRR";"RGR20_2P05X2P05_TEX";"U32, U34";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/tps7a8300";"2-A, low-VIN, low-2-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good wi 20-VQFN -40 to 125";"";"Texas Instruments";"TPS7A8300RGRR";"";"";"";"";"";"";"";"";"";"";"";

4_Schematics and Boards Layout/4_7_Production Files/Gerber_PowerBoard/PowerBoard.dri

@@ -2,7 +2,7 @@ Generated by EAGLE CAM Processor 7.4.0
 
 Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerBoard/PowerBoard.dri
 
- Date              : 04/04/2026 22:46
+ Date              : 19/04/2026 19:18
  Drills            : generated
  Device            : Excellon drill station, coordinate format 2.5 inch
 

4_Schematics and Boards Layout/4_7_Production Files/Gerber_PowerBoard/PowerBoard.gpi

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+ Date              : 19/04/2026 19:21
+ Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerBoard/PowerBoard.bsp
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+ Coordinate Format : 2.5
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+ Zero Suppression  : None
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4_Schematics and Boards Layout/4_7_Production Files/Gerber_freq_synth/Clocks_Freq_Synth_board.L5

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@@ -182,14 +184,10 @@ X0294063Y0355677D03*
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4_Schematics and Boards Layout/4_7_Production Files/Gerber_freq_synth/Clocks_Freq_Synth_board.L6

@@ -349,13 +349,6 @@ X0061780Y0026543D03*
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4_Schematics and Boards Layout/4_7_Production Files/Gerber_freq_synth/Clocks_Freq_Synth_board.csv

@@ -0,0 +1,41 @@
+"Qty";"Value";"Device";"Package";"Parts";"Description";"COPYRIGHT";"DESCRIPTION";"HEIGHT";"MANUFACTURER_NAME";"MANUFACTURER_PART_NUMBER";"MF";"MFR_NAME";"MOUSER_PART_NUMBER";"MOUSER_PRICE-STOCK";"MPN";"OC_FARNELL";"OC_NEWARK";"POPULARITY";"PROD_ID";"SPICEPREFIX";"VALUE";
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+"5";"";"L-EUL5650M";"L5650M";"L9, L10, L11, L12, L13";"INDUCTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"L";"";
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+"1";"0.1µf";"C-EUC0201";"C0201";"C92";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"0.33µF";"C-EUC0201";"C0201";"C2, C6";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"0.47µF";"C-EUC0201";"C0201";"C9, C10";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"1";"0.47µf";"C-EUC0201";"C0201";"C3";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"3";"0.65k";"R-EU_R0201";"R0201";"R6, R8, R10";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"9";"0R";"R-EU_R0201";"R0201";"R5, R14, R15, R19, R20, R27, R28, R32, R33";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
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+"1";"1000pF";"C-EUC0201";"C0201";"C8";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"4";"100R";"R-EU_R0201";"R0201";"R1, R12, R13, R26";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"2";"10nF";"C-EUC0201";"C0201";"C61, C84";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"3";"10nF";"C-EUC0402";"C0402";"C15, C17, C19";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"18";"";"C";"";
+"6";"10pF";"C-EUC0201";"C0201";"C1, C62, C63, C85, C86, C89";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"5";"10µF";"C-EUC1210";"C1210";"C23, C27, C31, C45, C47";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"11";"142-0731-211";"142-0731-211";"1420731211";"J1, J2, J5, J6, J7, J8, J9, J10, J11, J12, J13";"SMA Connector Jack, Female Socket 50 Ohms Through Hole Solder";"";"SMA Connector Jack, Female Socket 50 Ohms Through Hole Solder";"9.8852mm";"Cinch Connectivity Solutions";"142-0731-211";"";"";"530-142-0731-211";"https://www.mouser.co.uk/ProductDetail/Johnson-Cinch-Connectivity-Solutions/142-0731-211?qs=HFfMDpzxxd0OVzI3hm9tuA%3D%3D";"";"";"";"";"";"";"";
+"6";"1k";"R-EU_R0201";"R0201";"R2, R3, R4, R7, R9, R11";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
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+"8";"200k";"R-EU_R0201";"R0201";"R22, R23, R24, R25, R35, R36, R37, R38";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"6";"22-23-2021";"22-23-2021";"22-23-2021";"X10, X11, X12, X13, X14, X15";".100" (2.54mm) Center Header - 2 Pin";"";"";"";"";"";"MOLEX";"";"";"";"22-23-2021";"1462926";"25C3832";"40";"";"";"";
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+"6";"22µF";"C-EUC1210";"C1210";"C21, C25, C29, C33, C46, C51";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
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+"2";"330R";"R-EU_R0201";"R0201";"R18, R31";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"20";"4.7µF";"C-EUC0201";"C0201";"C38, C39, C40, C48, C49, C50, C55, C56, C57, C58, C72, C73, C74, C75, C76, C77, C78, C79, C80, C81";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"500R";"R-EU_R0201";"R0201";"R21, R34";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"2";"931R";"R-EU_R0201";"R0201";"R16, R29";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"1";"AD9523BCPZ";"AD9523BCPZ";"QFN50P1000X1000X100-73N";"IC1";"AD9523BCPZ, PLL Clock Driver Dual, 72-Pin LFCSP VQ";"";"AD9523BCPZ, PLL Clock Driver Dual, 72-Pin LFCSP VQ";"mm";"Analog Devices";"AD9523BCPZ";"";"";"584-AD9523BCPZ";"https://www.mouser.com/Search/Refine.aspx?Keyword=584-AD9523BCPZ";"";"";"";"";"";"";"";
+"2";"ADF4382ABCCZ";"ADF4382ABCCZ";"CC-48-10_ADI";"U1, U6";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"ADF4382ABCCZ";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";
+"4";"ATS1005-3DB-FD-T05";"ATS1005-3DB-FD-T05";"SMT_DB-FD-T05_SUS";"U4, U5, U8, U10";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"Susumu";"ATS1005-3DB-FD-T05";"";"";"";"";"";"";"";"";"";"";"";
+"2";"CJT-T-P-HH-ST-TH1";"CJT-T-P-HH-ST-TH1";"CONN_CJT-T-P-XX-ST-TH1_SAI";"J3, J4";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"Samtec Inc";"CJT-T-P-HH-ST-TH1";"";"";"";"";"";"";"";"";"";"";"";
+"2";"CVHD-950-50.000";"CVHD-950-50.000";"SMD4_CVHD-950_CRX";"X5, X6";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"Crystek Crystals";"CVHD-950-50.000";"";"";"";"";"";"";"";"";"";"";"";
+"1";"ECOC-2522-100.000-3HC";"ECOC-2522-100.000-3HC";"SMD5_ECOC-2522_25P4X22_ECS";"X4";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"ECS International";"ECOC-2522-100.000-3HC";"";"";"";"";"";"";"";"";"";"";"";
+"4";"FBMH1608HL601-T";"FBMH1608HL601-T";"BEADC1608X90N";"FB1, FB2, FB3, FB4";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"2";"Green";"LED-GREEN-0603-WE";"LED-0603";"D1, D2";"Green SMD LED";"";"";"";"";"";"";"";"";"";"";"";"";"";"DIO-16512";"";"Green";
+"4";"MTX2-143+";"MTX2-143+";"DQ1225_MNC";"U2, U3, U7, U9";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"MTX2-143+";"";"Mini Circuits";"";"";"";"";"";"";"";"";"";

4_Schematics and Boards Layout/4_7_Production Files/Gerber_freq_synth/Clocks_Freq_Synth_board.drd

@@ -798,8 +798,6 @@ X127429Y228217
 X118177Y228118
 X109220Y227921
 X100854Y226740
-X102724Y234713
-X102724Y234713
 X102724Y243571
 X102823Y255579
 X102528Y264437

4_Schematics and Boards Layout/4_7_Production Files/Gerber_freq_synth/Clocks_Freq_Synth_board.dri

@@ -2,7 +2,7 @@ Generated by EAGLE CAM Processor 7.4.0
 
 Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/FrequencySynthesizerBoard/Clocks_Freq_Synth_board.dri
 
- Date              : 05/04/2026 01:09
+ Date              : 19/04/2026 21:57
  Drills            : generated
  Device            : Excellon drill station, coordinate format 2.5 inch
 
@@ -33,13 +33,13 @@ Drills used:
  T04   0.0197inch    34
  T05   0.0250inch     4
  T06   0.0330inch     8
- T07   0.0394inch    84
+ T07   0.0394inch    82
  T08   0.0400inch    26
  T09   0.0470inch    44
  T10   0.0787inch     1
  T11   0.1260inch     4
 
-Total number of drills: 909
+Total number of drills: 907
 
 Plotfiles:
 

4_Schematics and Boards Layout/4_7_Production Files/Gerber_freq_synth/Clocks_Freq_Synth_board.gpi

@@ -2,7 +2,7 @@ Generated by EAGLE CAM Processor 7.4.0
 
 Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/FrequencySynthesizerBoard/Clocks_Freq_Synth_board.gpi
 
- Date              : 05/04/2026 01:12
+ Date              : 19/04/2026 21:58
  Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/FrequencySynthesizerBoard/Clocks_Freq_Synth_board.bsk
  Apertures         : generated: 
  Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch

4_Schematics and Boards Layout/4_7_Production Files/Gerber_freq_synth/Clocks_Freq_Synth_board.mnt

@@ -0,0 +1,174 @@
+C1 48.37 59.91  90 10pF C0201
+C2 31.74 13.52   0 0.33ｵF C0201
+C3 49.46 45.72   0 0.47ｵf C0201
+C4 49.48 43.39   0  C0201
+C5 49.52 42.39   0  C0201
+C6 49.52 41.92   0 0.33ｵF C0201
+C7 49.51 40.39   0  C0201
+C8 49.51 39.87   0 1000pF C0201
+C9 48.76 37.89  90 0.47ｵF C0201
+C10 48.63 39.42   0 0.47ｵF C0201
+C11 47.37 50.30 270 1ｵF C0201
+C12 46.81 50.30 270 1ｵF C0201
+C13 45.40 50.35 270 1ｵF C0201
+C14 44.82 50.35 270 1ｵF C0201
+C15 86.78 30.16   0 10nF C0402
+C16 49.07 44.65  90 0.1ｵF C0201
+C17 64.58 24.27 270 10nF C0402
+C18 50.57 34.64 180 0.1ｵF C0201
+C19 52.86 24.27 270 10nF C0402
+C20 55.66 34.54   0 0.1ｵF C0201
+C21 10.00 30.60 270 22ｵF C1210
+C22 58.71 34.53   0 0.1ｵF C0201
+C23 21.00 30.50 270 10ｵF C1210
+C24 62.13 37.42   0 0.1ｵF C0201
+C25 35.40  4.90 270 22ｵF C1210
+C26 61.84 40.65  90 0.1ｵF C0201
+C27 45.90  5.30 270 10ｵF C1210
+C28 62.06 43.41   0 0.1ｵF C0201
+C29 81.20  4.90 270 22ｵF C1210
+C30 57.71 46.83   0 0.1ｵF C0201
+C31 70.50  5.00 270 10ｵF C1210
+C32 54.48 46.90  90 0.1ｵF C0201
+C33 18.10 95.10  90 22ｵF C1210
+C34 49.20 38.86 180 0.1ｵF C0201
+C35 57.21 34.54   0 0.1ｵF C0201
+C36 61.16 34.74   0 0.1ｵF C0201
+C37 62.20 38.96   0 0.1ｵF C0201
+C38 42.23 55.44 180 4.7ｵF C0201
+C39 42.56 52.07 270 4.7ｵF C0201
+C40 46.11 50.52   0 4.7ｵF C0201
+C41 62.26 41.88   0 0.1ｵF C0201
+C42 61.85 45.25  90 0.1ｵF C0201
+C43 56.56 46.73   0 0.1ｵF C0201
+C44 52.33 46.82 180 0.1ｵF C0201
+C45 19.40 85.70 180 10ｵF C1210
+C46 34.30 93.80 270 22ｵF C1210
+C47 30.90 86.70   0 10ｵF C1210
+C48 48.11 50.54   0 4.7ｵF C0201
+C49 48.11 50.06   0 4.7ｵF C0201
+C50 51.64 53.12 270 4.7ｵF C0201
+C51 87.70 87.30  90 22ｵF C1210
+C55 44.21 59.60   0 4.7ｵF C0201
+C56 51.86 59.44 180 4.7ｵF C0201
+C57 51.69 57.60  90 4.7ｵF C0201
+C58 51.62 54.17 270 4.7ｵF C0201
+C59 49.65 49.57  90 1ｵF C0201
+C60 52.95 54.60  90 31pF C0201
+C61 53.66 52.04   0 10nF C0201
+C62 49.86 50.62 270 10pF C0201
+C63 45.84 61.00  90 10pF C0201
+C64 46.57 61.00  90 0.1ｵF C0201
+C65 45.15 61.00  90 0.1ｵF C0201
+C66 49.11 59.94  90 0.1ｵF C0201
+C67 47.66 59.94  90 0.1ｵF C0201
+C68 61.74 50.36 270 1ｵF C0201
+C69 61.19 50.33 270 1ｵF C0201
+C70 59.82 50.03 270 1ｵF C0201
+C71 59.19 50.02 270 1ｵF C0201
+C72 66.00 53.21 270 4.7ｵF C0201
+C73 66.10 54.16 270 4.7ｵF C0201
+C74 66.04 57.61  90 4.7ｵF C0201
+C75 64.72 59.83 180 4.7ｵF C0201
+C76 58.07 59.64   0 4.7ｵF C0201
+C77 56.62 55.38 180 4.7ｵF C0201
+C78 56.92 52.33 180 4.7ｵF C0201
+C79 60.47 50.84   0 4.7ｵF C0201
+C80 62.25 50.66 270 4.7ｵF C0201
+C81 62.70 50.66 270 4.7ｵF C0201
+C82 64.80 49.14 180 1ｵF C0201
+C83 67.62 55.61  90 31pF C0201
+C84 68.70 54.96  90 10nF C0201
+C85 63.74 50.66 270 10pF C0201
+C86 60.20 61.00  90 10pF C0201
+C87 60.94 61.00  90 0.1ｵF C0201
+C88 59.44 61.00  90 0.1ｵF C0201
+C89 62.70 59.91  90 10pF C0201
+C90 63.47 59.91  90 0.1ｵF C0201
+C91 61.97 59.91  90 0.1ｵF C0201
+C92 16.93 67.92 180 0.1ｵf C0201
+D1 41.75 59.88  90 Green LED-0603
+D2 56.83 60.61  90 Green LED-0603
+FB1 68.41 56.87 180 FBMH1608HL601-T BEADC1608X90N
+FB2 53.58 56.01 180 FBMH1608HL601-T BEADC1608X90N
+FB3 52.06 49.65   0 FBMH1608HL601-T BEADC1608X90N
+FB4 63.46 48.33 270 FBMH1608HL601-T BEADC1608X90N
+IC1 55.70 40.67   0 AD9523BCPZ QFN50P1000X1000X100-73N
+J1 52.94 90.00   0 142-0731-211 1420731211
+J2 92.86 49.36  90 142-0731-211 1420731211
+J5 64.56 17.84   0 142-0731-211 1420731211
+J6 52.79 18.27   0 142-0731-211 1420731211
+J7 92.71 30.20  90 142-0731-211 1420731211
+J8 92.71 16.28   0 142-0731-211 1420731211
+J9  9.85 82.37 180 142-0731-211 1420731211
+J10 45.93 74.00   0 142-0731-211 1420731211
+J11 60.20 74.00   0 142-0731-211 1420731211
+J12 74.38 71.98  45 142-0731-211 1420731211
+J13 11.67 67.91  90 142-0731-211 1420731211
+L1 48.80 59.32   0 1.3nH L0201
+L2 46.29 60.40   0 1.3nH L0201
+L3 45.44 60.40   0 1.3nH L0201
+L4 47.95 59.32   0 1.3nH L0201
+L5 60.67 60.40   0 1.3nH L0201
+L6 59.77 60.40   0 1.3nH L0201
+L7 63.17 59.31   0 1.3nH L0201
+L8 62.27 59.31   0 1.3nH L0201
+L9 15.40 31.90 180  L5650M
+L10 40.80  6.20 180  L5650M
+L11 75.80  6.30   0  L5650M
+L12 22.20 91.00  90  L5650M
+L13 29.60 92.70  90  L5650M
+R1 61.47 51.11   0 100R R0201
+R2  7.14 58.81 180 1k R0201
+R3  7.38 59.72 270 1k R0201
+R4 31.78 14.16   0 1k R0201
+R5 48.02 38.16   0 0R R0201
+R6 16.38 13.37 270 0.65k R0201
+R7 16.37 12.32 270 1k R0201
+R8 13.86 21.50  90 0.65k R0201
+R9 13.82 22.69  90 1k R0201
+R10 16.36 21.55  90 0.65k R0201
+R11 16.42 22.70  90 1k R0201
+R12 47.11 51.07   0 100R R0201
+R13 45.11 51.07   0 100R R0201
+R14 51.74 56.17 270 0R R0201
+R15 51.96 55.04   0 0R R0201
+R16 52.78 53.71 180 931R R0201
+R17 52.48 52.85  90 30R R0201
+R18 52.71 52.07   0 330R R0201
+R19 51.62 50.89   0 0R R0201
+R20 50.61 50.88   0 0R R0201
+R21 42.53 57.17 270 500R R0201
+R22 41.78 56.69 270 200k R0201
+R23 41.34 55.73  90 200k R0201
+R24 42.32 54.09 270 200k R0201
+R25 41.39 54.64 270 200k R0201
+R26 59.47 51.16   0 100R R0201
+R27 65.87 56.55   0 0R R0201
+R28 65.90 55.35   0 0R R0201
+R29 66.92 55.36 180 931R R0201
+R30 67.63 54.52  90 30R R0201
+R31 68.47 54.26   0 330R R0201
+R32 65.46 50.90   0 0R R0201
+R33 64.54 50.90   0 0R R0201
+R34 56.82 58.21 270 500R R0201
+R35 56.94 56.71 270 200k R0201
+R36 55.84 56.16 270 200k R0201
+R37 56.84 54.16 270 200k R0201
+R38 56.24 54.61 270 200k R0201
+R39 63.22 41.38   0 22R R0201
+R40 59.45 33.47 270 22R R0201
+R41 57.97 33.47 270 22R R0201
+U1 47.12 55.12 180 ADF4382ABCCZ CC-48-10_ADI
+U2 45.91 65.00 270 MTX2-143+ DQ1225_MNC
+U3 52.91 64.38 270 MTX2-143+ DQ1225_MNC
+U4 45.91 68.00 180 ATS1005-3DB-FD-T05 SMT_DB-FD-T05_SUS
+U5 52.94 68.68 180 ATS1005-3DB-FD-T05 SMT_DB-FD-T05_SUS
+U6 61.48 55.12 180 ADF4382ABCCZ CC-48-10_ADI
+U7 60.21 65.00 270 MTX2-143+ DQ1225_MNC
+U8 60.20 68.00 180 ATS1005-3DB-FD-T05 SMT_DB-FD-T05_SUS
+U9 67.91 65.62 225 MTX2-143+ DQ1225_MNC
+U10 70.09 67.84 135 ATS1005-3DB-FD-T05 SMT_DB-FD-T05_SUS
+X4 23.07 49.95   0 ECOC-2522-100.000-3HC SMD5_ECOC-2522_25P4X22_ECS
+X5 34.12 31.62  90 CVHD-950-50.000 SMD4_CVHD-950_CRX
+X6 33.87 19.97  90 CVHD-950-50.000 SMD4_CVHD-950_CRX

4_Schematics and Boards Layout/4_7_Production Files/Gerber_freq_synth/Clocks_Freq_Synth_board.smb

@@ -159,8 +159,6 @@ X0127429Y0228217D03*
 X0118177Y0228118D03*
 X0109220Y0227921D03*
 X0100854Y0226740D03*
-X0102724Y0234713D03*
-X0102724Y0234713D03*
 X0102724Y0243571D03*
 X0102823Y0255579D03*
 X0102528Y0264437D03*

4_Schematics and Boards Layout/4_7_Production Files/Gerber_freq_synth/Clocks_Freq_Synth_board.smt

@@ -1334,10 +1334,8 @@ X0102528Y0273197D03*
 X0102528Y0264437D03*
 X0102823Y0255579D03*
 X0102724Y0243571D03*
-X0102724Y0234713D03*
-X0102724Y0234713D03*
-X0100854Y0226740D03*
 X0109220Y0227921D03*
+X0100854Y0226740D03*
 X0118177Y0228118D03*
 X0127429Y0228217D03*
 X0136976Y0228217D03*

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_AGC.cpp

@@ -24,7 +24,6 @@ ADAR1000_AGC::ADAR1000_AGC()
     , saturation_event_count(0)
 {
     memset(cal_offset, 0, sizeof(cal_offset));
-    if (holdoff_frames == 0) holdoff_frames = 1;
 }
 
 // ---------------------------------------------------------------------------

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp

@@ -868,22 +868,11 @@ void ADAR1000Manager::adarSetRamBypass(uint8_t deviceIndex, uint8_t broadcast) {
 }
 
 void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
-    // channel is 1-based (CH1..CH4) per API contract documented in
-    // ADAR1000_AGC.cpp and matching ADI datasheet terminology.
-    // Reject out-of-range early so a stale 0-based caller does not
-    // silently wrap to ((0-1) & 0x03) == 3 and write to CH4.
-    // See issue #90.
-    if (channel < 1 || channel > 4) {
-        DIAG("BF", "adarSetRxPhase: channel %u out of range [1..4], ignored", channel);
-        return;
-    }
     uint8_t i_val = VM_I[phase % 128];
     uint8_t q_val = VM_Q[phase % 128];
 
-    // Subtract 1 to convert 1-based channel to 0-based register offset
+    uint32_t mem_addr_i = REG_CH1_RX_PHS_I + (channel & 0x03) * 2;
-    // before masking. See issue #90.
+    uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + (channel & 0x03) * 2;
-    uint32_t mem_addr_i = REG_CH1_RX_PHS_I + ((channel - 1) & 0x03) * 2;
-    uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + ((channel - 1) & 0x03) * 2;
 
     adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
     adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
@@ -891,16 +880,11 @@ void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8
 }
 
 void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
-    // channel is 1-based (CH1..CH4). See issue #90.
-    if (channel < 1 || channel > 4) {
-        DIAG("BF", "adarSetTxPhase: channel %u out of range [1..4], ignored", channel);
-        return;
-    }
     uint8_t i_val = VM_I[phase % 128];
     uint8_t q_val = VM_Q[phase % 128];
 
-    uint32_t mem_addr_i = REG_CH1_TX_PHS_I + ((channel - 1) & 0x03) * 2;
+    uint32_t mem_addr_i = REG_CH1_TX_PHS_I + (channel & 0x03) * 2;
-    uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + ((channel - 1) & 0x03) * 2;
+    uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + (channel & 0x03) * 2;
 
     adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
     adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
@@ -908,23 +892,13 @@ void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8
 }
 
 void ADAR1000Manager::adarSetRxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
-    // channel is 1-based (CH1..CH4). See issue #90.
+    uint32_t mem_addr = REG_CH1_RX_GAIN + (channel & 0x03);
-    if (channel < 1 || channel > 4) {
-        DIAG("BF", "adarSetRxVgaGain: channel %u out of range [1..4], ignored", channel);
-        return;
-    }
-    uint32_t mem_addr = REG_CH1_RX_GAIN + ((channel - 1) & 0x03);
     adarWrite(deviceIndex, mem_addr, gain, broadcast);
     adarWrite(deviceIndex, REG_LOAD_WORKING, 0x1, broadcast);
 }
 
 void ADAR1000Manager::adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
-    // channel is 1-based (CH1..CH4). See issue #90.
+    uint32_t mem_addr = REG_CH1_TX_GAIN + (channel & 0x03);
-    if (channel < 1 || channel > 4) {
-        DIAG("BF", "adarSetTxVgaGain: channel %u out of range [1..4], ignored", channel);
-        return;
-    }
-    uint32_t mem_addr = REG_CH1_TX_GAIN + ((channel - 1) & 0x03);
     adarWrite(deviceIndex, mem_addr, gain, broadcast);
     adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
 }

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/USBHandler.cpp

@@ -13,7 +13,6 @@ void USBHandler::reset() {
     start_flag_received = false;
     buffer_index = 0;
     current_settings.resetToDefaults();
-    fault_ack_received = false;
 }
 
 void USBHandler::processUSBData(const uint8_t* data, uint32_t length) {
@@ -24,18 +23,6 @@ void USBHandler::processUSBData(const uint8_t* data, uint32_t length) {
     
     DIAG("USB", "processUSBData: %lu bytes, state=%d", (unsigned long)length, (int)current_state);
     
-    // FAULT_ACK: host sends exactly 4 bytes [0x40, 0x00, 0x00, 0x00].
-    // Requires exact 4-byte packet length: settings packets are always
-    // >= 82 bytes, so a lone 4-byte payload is unambiguous. Scanning
-    // inside larger packets would false-trigger on the IEEE 754
-    // encoding of 2.0 (0x4000000000000000) embedded in settings doubles.
-    static const uint8_t FAULT_ACK_SEQ[4] = {0x40, 0x00, 0x00, 0x00};
-    if (length == 4 && memcmp(data, FAULT_ACK_SEQ, 4) == 0) {
-        fault_ack_received = true;
-        DIAG("USB", "FAULT_ACK received");
-        return;
-    }
-    
     switch (current_state) {
         case USBState::WAITING_FOR_START:
             processStartFlag(data, length);

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/USBHandler.h

@@ -29,11 +29,6 @@ public:
     // Reset USB handler
     void reset();
 
-    // Fault-acknowledgement: host sends FAULT_ACK (0x40) to clear
-    // system_emergency_state and exit the safe-mode blink loop.
-    bool isFaultAckReceived() const { return fault_ack_received; }
-    void clearFaultAck()            { fault_ack_received = false; }
-
 private:
     RadarSettings current_settings;
     USBState current_state;
@@ -43,7 +38,6 @@ private:
     static constexpr uint32_t MAX_BUFFER_SIZE = 256;
     uint8_t usb_buffer[MAX_BUFFER_SIZE];
     uint32_t buffer_index;
-    bool fault_ack_received;
     
     void processStartFlag(const uint8_t* data, uint32_t length);
     void processSettingsData(const uint8_t* data, uint32_t length);

9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp

@@ -627,7 +627,7 @@ typedef enum {
 
 static SystemError_t last_error = ERROR_NONE;
 static uint32_t error_count = 0;
-static volatile bool system_emergency_state = false;
+static bool system_emergency_state = false;
 
 // Error handler function
 SystemError_t checkSystemHealth(void) {
@@ -2054,10 +2054,6 @@ int main(void)
 	            HAL_GPIO_TogglePin(LED_3_GPIO_Port, LED_3_Pin);
 	            HAL_GPIO_TogglePin(LED_4_GPIO_Port, LED_4_Pin);
 	            HAL_Delay(250);
-	            if (usbHandler.isFaultAckReceived()) {
-	                system_emergency_state = false;
-	                usbHandler.clearFaultAck();
-	            }
 	        }
 	        DIAG("SYS", "Exited safe mode blink loop -- system_emergency_state cleared");
 	    }

9_Firmware/9_1_Microcontroller/tests/Makefile

@@ -70,8 +70,7 @@ TESTS_STANDALONE := test_bug12_pa_cal_loop_inverted \
                     test_gap3_idq_periodic_reread \
                     test_gap3_emergency_state_ordering \
                     test_gap3_overtemp_emergency_stop \
-                    test_gap3_health_watchdog_cold_start \
+                    test_gap3_health_watchdog_cold_start
-                    test_gap3_fault_ack_clears_emergency
 
 # Tests that need platform_noos_stm32.o + mocks
 TESTS_WITH_PLATFORM := test_bug11_platform_spi_transmit_only
@@ -179,9 +178,6 @@ test_gap3_overtemp_emergency_stop: test_gap3_overtemp_emergency_stop.c
 test_gap3_health_watchdog_cold_start: test_gap3_health_watchdog_cold_start.c
 	$(CC) $(CFLAGS) $< -o $@
 
-test_gap3_fault_ack_clears_emergency: test_gap3_fault_ack_clears_emergency.c
-	$(CC) $(CFLAGS) $< -o $@
-
 # Tests that need platform_noos_stm32.o + mocks
 $(TESTS_WITH_PLATFORM): %: %.c $(MOCK_OBJS) $(PLATFORM_OBJ)
 	$(CC) $(CFLAGS) $(INCLUDES) $< $(MOCK_OBJS) $(PLATFORM_OBJ) -o $@

9_Firmware/9_1_Microcontroller/tests/test_gap3_fault_ack_clears_emergency.c

@@ -1,121 +0,0 @@
-/*******************************************************************************
- * test_gap3_fault_ack_clears_emergency.c
- *
- * Verifies the FAULT_ACK clear path for system_emergency_state:
- *   - USBHandler detects exactly [0x40, 0x00, 0x00, 0x00] in a 4-byte packet
- *   - Detection is false-positive-free: larger packets (settings data) carrying
- *     the same bytes as a subsequence must NOT trigger the ack
- *   - Main-loop blink logic clears system_emergency_state on receipt
- *
- * Logic extracted from USBHandler.cpp + main.cpp to mirror the actual code
- * paths without requiring HAL headers.
- ******************************************************************************/
-#include <assert.h>
-#include <stdio.h>
-#include <stdbool.h>
-#include <string.h>
-#include <stdint.h>
-
-/* ── Simulated USBHandler state ─────────────────────────────────────────── */
-static bool fault_ack_received = false;
-static volatile bool system_emergency_state = false;
-
-static const uint8_t FAULT_ACK_SEQ[4] = {0x40, 0x00, 0x00, 0x00};
-
-/* Mirrors USBHandler::processUSBData() detection logic */
-static void sim_processUSBData(const uint8_t *data, uint32_t length)
-{
-    if (data == NULL || length == 0) return;
-    if (length == 4 && memcmp(data, FAULT_ACK_SEQ, 4) == 0) {
-        fault_ack_received = true;
-        return;
-    }
-    /* (normal state machine omitted — not under test here) */
-}
-
-/* Mirrors one iteration of the blink loop in main.cpp */
-static void sim_blink_iteration(void)
-{
-    /* HAL_GPIO_TogglePin + HAL_Delay omitted */
-    if (fault_ack_received) {
-        system_emergency_state = false;
-        fault_ack_received = false;
-    }
-}
-
-int main(void)
-{
-    printf("=== Gap-3 FAULT_ACK clears system_emergency_state ===\n");
-
-    /* Test 1: exact 4-byte FAULT_ACK packet sets the flag */
-    printf("  Test 1: exact FAULT_ACK packet detected... ");
-    fault_ack_received = false;
-    const uint8_t ack_pkt[4] = {0x40, 0x00, 0x00, 0x00};
-    sim_processUSBData(ack_pkt, 4);
-    assert(fault_ack_received == true);
-    printf("PASS\n");
-
-    /* Test 2: flag cleared and system_emergency_state exits blink loop */
-    printf("  Test 2: blink loop exits on FAULT_ACK... ");
-    system_emergency_state = true;
-    fault_ack_received = true;
-    sim_blink_iteration();
-    assert(system_emergency_state == false);
-    assert(fault_ack_received == false);
-    printf("PASS\n");
-
-    /* Test 3: blink loop does NOT exit without ack */
-    printf("  Test 3: blink loop holds without ack... ");
-    system_emergency_state = true;
-    fault_ack_received = false;
-    sim_blink_iteration();
-    assert(system_emergency_state == true);
-    printf("PASS\n");
-
-    /* Test 4: settings-sized packet carrying [0x40,0x00,0x00,0x00] as first
-     * 4 bytes does NOT trigger ack (IEEE 754 double 2.0 = 0x4000000000000000) */
-    printf("  Test 4: settings packet with 2.0 double does not false-trigger... ");
-    fault_ack_received = false;
-    uint8_t settings_pkt[82];
-    memset(settings_pkt, 0, sizeof(settings_pkt));
-    /* First 4 bytes look like FAULT_ACK but packet length is 82 */
-    settings_pkt[0] = 0x40; settings_pkt[1] = 0x00;
-    settings_pkt[2] = 0x00; settings_pkt[3] = 0x00;
-    sim_processUSBData(settings_pkt, sizeof(settings_pkt));
-    assert(fault_ack_received == false);
-    printf("PASS\n");
-
-    /* Test 5: 3-byte packet (truncated) does not trigger */
-    printf("  Test 5: truncated 3-byte packet ignored... ");
-    fault_ack_received = false;
-    const uint8_t short_pkt[3] = {0x40, 0x00, 0x00};
-    sim_processUSBData(short_pkt, 3);
-    assert(fault_ack_received == false);
-    printf("PASS\n");
-
-    /* Test 6: wrong opcode byte in 4-byte packet does not trigger */
-    printf("  Test 6: wrong opcode (0x28 AGC_ENABLE) not detected as FAULT_ACK... ");
-    fault_ack_received = false;
-    const uint8_t agc_pkt[4] = {0x28, 0x00, 0x00, 0x01};
-    sim_processUSBData(agc_pkt, 4);
-    assert(fault_ack_received == false);
-    printf("PASS\n");
-
-    /* Test 7: multiple blink iterations — loop stays active until ack */
-    printf("  Test 7: loop stays active across multiple iterations until ack... ");
-    system_emergency_state = true;
-    fault_ack_received = false;
-    sim_blink_iteration();
-    assert(system_emergency_state == true);
-    sim_blink_iteration();
-    assert(system_emergency_state == true);
-    /* Now ack arrives */
-    sim_processUSBData(ack_pkt, 4);
-    assert(fault_ack_received == true);
-    sim_blink_iteration();
-    assert(system_emergency_state == false);
-    printf("PASS\n");
-
-    printf("\n=== Gap-3 FAULT_ACK: ALL 7 TESTS PASSED ===\n\n");
-    return 0;
-}

9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v

@@ -32,50 +32,11 @@ localparam COMB_WIDTH = 28;
 // adjacent DSP48E1 tiles — zero fabric delay, guaranteed to meet 400+ MHz
 // on 7-series regardless of speed grade.
 //
-// Active-high reset derived from reset_n (inverted and REGISTERED).
+// Active-high reset derived from reset_n (inverted).
 // CEP (clock enable for P register) gated by data_valid.
-//
+// ============================================================================
-// ----------------------------------------------------------------------------
+
-// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
+wire reset_h = ~reset_n;  // active-high reset for DSP48E1 RSTP
-// ----------------------------------------------------------------------------
-// Previously this was a combinational wire (`wire reset_h = ~reset_n`). Vivado
-// collapsed all per-module inversions across the DDC hierarchy into a SINGLE
-// shared LUT1, whose output fanned out to 702 loads (DSP48E1 RSTP/RSTB/RSTC
-// plus FDRE R pins of all comb-stage DSP48E1s inferred via use_dsp="yes").
-// Route delay alone on that net was 2.019–2.268 ns — nearly one full 2.5 ns
-// period. Timing failed by 626 ps on the 400 MHz domain.
-//
-// Fix: convert reset_h to a REGISTERED signal with (* max_fanout = 50 *).
-// Vivado treats max_fanout on a REG (not a wire) as authoritative and
-// replicates the register into N copies, each placed near its ≈50 loads.
-// Invariants preserved:
-//   I1 (correctness):       reset_h is still active-high, equals ~reset_n
-//                           after one clk edge; CIC reset is a RECEIVER-side
-//                           synchronizer anyway (driven by reset_n_400m which
-//                           is already sync'd in the parent DDC), so adding
-//                           one more clk cycle of latency is safe.
-//   I2 (glitch-free):       Registered output => inherently glitch-free,
-//                           feeding DSP48E1 RST pins (which are synchronous
-//                           to CLK, so they capture on the same edge anyway).
-//   I3 (power-up safety):   reset_h is NOT async-reset itself. On power-up,
-//                           FDRE INIT=0 starts reset_h LOW. First clk edge
-//                           samples ~reset_n which is LOW on power-up (the
-//                           parent DDC holds reset_n_400m low until the 2-
-//                           stage synchronizer releases), so reset_h goes
-//                           HIGH on cycle 1 and all DSPs see reset during
-//                           the following cycles. System is held in reset
-//                           for enough cycles that any initial register
-//                           state garbage is overwritten. ✅
-//   I4 (reset de-assertion):reset_h goes LOW one cycle AFTER reset_n_400m
-//                           goes HIGH. Downstream DSPs come out of reset on
-//                           the next clk edge after that. Total latency
-//                           from system reset release to first valid sample:
-//                           2 (sync chain) + 1 (reset_h reg) + 1 (first
-//                           DSP output) = 4 cycles at 400 MHz = 10 ns.
-//                           Negligible vs system reset assertion duration.
-// ----------------------------------------------------------------------------
-(* max_fanout = 50 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
-always @(posedge clk) reset_h <= ~reset_n;
 
 // Sign-extended input for integrator_0 C port (48-bit)
 wire [ACC_WIDTH-1:0] data_in_c = {{(ACC_WIDTH-18){data_in[17]}}, data_in};
@@ -738,11 +699,10 @@ initial begin
 end
 
 // Decimation control + monitoring (integrators are now DSP48E1 instances)
-// Sync reset via reset_h (registered, max_fanout=50) — eliminates the shared
+// Sync reset: enables FDRE inference for better timing at 400 MHz.
-// LUT1 inverter that previously fanned out to all fabric FDRE R pins plus
+// Reset is already synchronous to clk via reset synchronizer in parent module.
-// DSP48E1 RST pins (702 loads total). See "RESET FAN-OUT INVARIANT" at top.
 always @(posedge clk) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         integrator_sampled <= 0;
         decimation_counter <= 0;
         data_valid_delayed <= 0;
@@ -795,9 +755,9 @@ always @(posedge clk) begin
 end
 
 // Pipeline the valid signal for comb section
-// Sync reset via reset_h — same replicated-register source as DSP48E1 RSTs.
+// Sync reset: matches decimation control block reset style.
 always @(posedge clk) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         data_valid_comb <= 0;
         data_valid_comb_pipe <= 0;
         data_valid_comb_0_out <= 0;
@@ -832,7 +792,7 @@ end
 //   - Each stage: comb[i] = comb[i-1] - comb_delay[i][last]
 
 always @(posedge clk) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         for (i = 0; i < STAGES; i = i + 1) begin
             comb[i] <= 0;
             for (j = 0; j < COMB_DELAY; j = j + 1) begin

9_Firmware/9_2_FPGA/ddc_400m.v

@@ -53,6 +53,46 @@ reg [2:0] saturation_count;
 reg overflow_detected;
 reg [7:0] error_counter;
 
+// ============================================================================
+// 400 MHz Reset Synchronizer
+//
+// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
+// Using it directly as an async reset in the 400 MHz domain causes the reset
+// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
+// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
+// domain, requiring 18.243ns of routing (WNS = -18.081ns).
+//
+// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
+// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
+// path from reset_n to all 400 MHz registers). Reset deassertion is
+// synchronized to clk_400m rising edge, preventing metastability.
+//
+// All 400 MHz submodules (NCO, CIC, mixers, LFSR) use reset_n_400m.
+// All 100 MHz submodules (FIR, output stage) continue using reset_n directly
+// (already synchronized to 100 MHz at radar_system_top level).
+// ============================================================================
+(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
+(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
+
+// Active-high reset for DSP48E1 RST ports (avoids LUT1 inverter fan-out)
+(* max_fanout = 50 *) reg reset_400m;
+
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
+        reset_sync_400m <= 2'b00;
+        reset_400m      <= 1'b1;
+    end else begin
+        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
+        reset_400m      <= ~reset_sync_400m[1];
+    end
+end
+
+// CDC synchronization for control signals (2-stage synchronizers)
+(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
+(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
+wire mixers_enable_sync;
+wire force_saturation_sync;
+
 // Debug monitoring signals
 reg [31:0] sample_counter;
 wire signed [17:0] debug_mixed_i_trunc;
@@ -90,6 +130,8 @@ reg baseband_valid_reg;
 wire [7:0] phase_dither_bits;
 reg [31:0] phase_inc_dithered;
 
+
+
 // ============================================================================
 // Debug Signal Assignments
 // ============================================================================
@@ -100,66 +142,13 @@ assign debug_mixed_i_trunc = mixed_i[25:8];
 assign debug_mixed_q_trunc = mixed_q[25:8];
 
 // ============================================================================
-// 400 MHz Reset Synchronizer
+// Clock Domain Crossing for Control Signals (2-stage synchronizers)
-//
-// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
-// Using it directly as an async reset in the 400 MHz domain causes the reset
-// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
-// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
-// domain, requiring 18.243ns of routing (WNS = -18.081ns).
-//
-// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
-// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
-// path from reset_n to all 400 MHz registers). Reset deassertion is
-//
-// reset_400m   : ACTIVE-HIGH registered reset with (* max_fanout = 50 *).
-//                This is THE signal fed to every synchronous 400 MHz FDRE
-//                and every DSP48E1 RST pin in this module and its children
-//                (NCO, CIC, LFSR). Vivado replicates the register (~14
-//                copies) so each replica drives ≈50 loads regionally,
-//                eliminating the single-LUT1 / 702-load net that caused
-//                WNS=-0.626 ns in Build N.
-//
-// System-level invariants preserved:
-//   I1  Reset assertion propagates to all 400 MHz regs within ≤3 clk edges
-//       (2 sync + 1 replicated-reg fanout).  At 400 MHz = 7.5 ns << any
-//       system-level reset assertion duration.
-//   I2  Reset de-assertion is always synchronous to clk_400m (via
-//       reset_sync_400m), never glitches.
-//   I3  DSP48E1 RST pins are all fed from Q of a register — glitch-free.
-//   I4  No new CDC introduced: reset_400m is entirely in clk_400m domain.
-//   I5  Power-up: reset_n is asserted externally and mmcm_locked is low;
-//       reset_sync_400m stays 2'b00, reset_400m stays 1'b1, downstream
-//       FDREs stay cleared. Safe.
 // ============================================================================
-(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m = 2'b00;
-(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
-
-// Active-high replicated reset for all synchronous 400 MHz consumers
-(* max_fanout = 50 *) reg reset_400m = 1'b1;
-
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
-        reset_sync_400m <= 2'b00;
-        reset_400m      <= 1'b1;
-    end else begin
-        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
-        reset_400m      <= ~reset_sync_400m[1];
-    end
-end
-
-// CDC synchronization for control signals (2-stage synchronizers)
-(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
-(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
-wire mixers_enable_sync;
-wire force_saturation_sync;
 assign mixers_enable_sync = mixers_enable_sync_chain[1];
 assign force_saturation_sync = force_saturation_sync_chain[1];
 
-// Sync reset via reset_400m (replicated, max_fanout=50). Was async on
+always @(posedge clk_400m or negedge reset_n_400m) begin
-// reset_n_400m — see "400 MHz RESET DISTRIBUTION" comment above.
+    if (!reset_n_400m) begin
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
         mixers_enable_sync_chain <= 2'b00;
         force_saturation_sync_chain <= 2'b00;
     end else begin
@@ -171,8 +160,8 @@ end
 // ============================================================================
 // Sample Counter and Debug Monitoring
 // ============================================================================
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (reset_400m || reset_monitors) begin
+    if (!reset_n_400m || reset_monitors) begin
         sample_counter <= 0;
         error_counter <= 0;
     end else if (adc_data_valid_i && adc_data_valid_q ) begin
@@ -200,8 +189,8 @@ lfsr_dither_enhanced #(
 localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
 
 // Apply dithering to reduce spurious tones (registered for 400 MHz timing)
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (reset_400m)
+    if (!reset_n_400m)
         phase_inc_dithered <= PHASE_INC_120MHZ;
     else
         phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
@@ -240,8 +229,8 @@ assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
                       {1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
 
 // Valid pipeline: 5-stage shift register (1 NCO pipe + 3 DSP48E1 AREG+MREG+PREG + 1 retiming)
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (reset_400m) begin
+    if (!reset_n_400m) begin
         dsp_valid_pipe <= 5'b00000;
     end else begin
         dsp_valid_pipe <= {dsp_valid_pipe[3:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
@@ -257,8 +246,8 @@ reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal;  // Mod
 reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg;            // Models PREG
 
 // Stage 0: NCO pipeline — breaks long NCO→DSP route (matches synthesis fabric registers)
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (reset_400m) begin
+    if (!reset_n_400m) begin
         cos_nco_pipe <= 0;
         sin_nco_pipe <= 0;
     end else begin
@@ -268,8 +257,8 @@ always @(posedge clk_400m) begin
 end
 
 // Stage 1: AREG/BREG equivalent (uses pipelined NCO outputs)
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (reset_400m) begin
+    if (!reset_n_400m) begin
         adc_signed_reg <= 0;
         cos_pipe_reg <= 0;
         sin_pipe_reg <= 0;
@@ -281,8 +270,8 @@ always @(posedge clk_400m) begin
 end
 
 // Stage 2: MREG equivalent
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (reset_400m) begin
+    if (!reset_n_400m) begin
         mult_i_internal <= 0;
         mult_q_internal <= 0;
     end else begin
@@ -292,8 +281,8 @@ always @(posedge clk_400m) begin
 end
 
 // Stage 3: PREG equivalent
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (reset_400m) begin
+    if (!reset_n_400m) begin
         mult_i_reg <= 0;
         mult_q_reg <= 0;
     end else begin
@@ -303,8 +292,8 @@ always @(posedge clk_400m) begin
 end
 
 // Stage 4: Post-DSP retiming register (matches synthesis path)
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (reset_400m) begin
+    if (!reset_n_400m) begin
         mult_i_retimed <= 0;
         mult_q_retimed <= 0;
     end else begin
@@ -322,8 +311,8 @@ wire [47:0] dsp_p_i, dsp_p_q;
 // (1.505ns routing observed in Build 26). These fabric registers are placed
 // near the DSP by the placer, splitting the route into two shorter segments.
 // DONT_TOUCH on the reg declaration (above) prevents absorption/retiming.
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (reset_400m) begin
+    if (!reset_n_400m) begin
         cos_nco_pipe <= 0;
         sin_nco_pipe <= 0;
     end else begin
@@ -340,10 +329,11 @@ DSP48E1 #(
     .USE_DPORT("FALSE"),
     .USE_MULT("MULTIPLY"),
     .USE_SIMD("ONE48"),
+    // Pipeline register attributes — all enabled for max timing
     .AREG(1),
     .BREG(1),
     .MREG(1),
-    .PREG(1),
+    .PREG(1),           // P register enabled — absorbs CLK→P delay for timing closure
     .ADREG(0),
     .ACASCREG(1),
     .BCASCREG(1),
@@ -354,6 +344,7 @@ DSP48E1 #(
     .DREG(0),
     .INMODEREG(0),
     .OPMODEREG(0),
+    // Pattern detector (unused)
     .AUTORESET_PATDET("NO_RESET"),
     .MASK(48'h3fffffffffff),
     .PATTERN(48'h000000000000),
@@ -505,8 +496,8 @@ wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WID
 // Stage 4: Post-DSP retiming register — breaks DSP48E1 CLK→P to fabric path
 // Without this, the DSP output prop delay (1.866ns) + routing (0.515ns) exceeds
 // the 2.500ns clock period at slow process corner
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (reset_400m) begin
+    if (!reset_n_400m) begin
         mult_i_retimed <= 0;
         mult_q_retimed <= 0;
     end else begin
@@ -522,8 +513,8 @@ end
 // force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
 // polluting the critical input path with extra logic
 // ============================================================================
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (reset_400m) begin
+    if (!reset_n_400m) begin
         mixed_i <= 0;
         mixed_q <= 0;
         mixed_valid <= 0;
@@ -768,17 +759,8 @@ generate
     end
 endgenerate
 
-// ============================================================================
+always @(posedge clk or negedge reset_n) begin
-// RESET FAN-OUT INVARIANT: registered active-high reset with max_fanout=50.
+    if (!reset_n) begin
-// See cic_decimator_4x_enhanced.v for full reasoning. reset_n here is driven
-// by the parent DDC's reset_n_400m (already synchronized to clk_400m), so
-// sync reset on the LFSR is safe. INIT=1'b1 holds LFSR in reset on power-up.
-// ============================================================================
-(* max_fanout = 50 *) reg reset_h = 1'b1;
-always @(posedge clk) reset_h <= ~reset_n;
-
-always @(posedge clk) begin
-    if (reset_h) begin
         lfsr_reg <= {DITHER_WIDTH{1'b1}};  // Non-zero initial state
         cycle_counter <= 0;
         lock_detected <= 0;

9_Firmware/9_2_FPGA/nco_400m_enhanced.v

@@ -59,25 +59,6 @@ reg [1:0] quadrant_reg2;                 // Pass-through for Stage 5 MUX
 // Valid pipeline: tracks 6-stage latency
 reg [5:0] valid_pipe;
 
-// ============================================================================
-// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
-// ============================================================================
-// reset_h is an ACTIVE-HIGH, REGISTERED copy of ~reset_n with (* max_fanout=50 *).
-// Vivado replicates this register (14+ copies) so each copy drives ≈50 loads
-// regionally, avoiding the single-LUT1 / 702-load net that caused timing
-// failure in Build N. It feeds:
-//   - DSP48E1 RSTP/RSTC on the phase-accumulator DSP (below)
-//   - All pipeline-stage fabric FDREs (synchronous reset)
-// Invariants (see cic_decimator_4x_enhanced.v for full reasoning):
-//   I1 correctness:      reset_h == ~reset_n one cycle later
-//   I2 glitch-free:      registered output
-//   I3 power-up safe:    INIT=1'b1 holds all downstream in reset until first
-//                        valid clock edge; reset_n is low on power-up anyway
-//   I4 de-assert lat.:   +1 cycle vs. direct async; negligible at 400 MHz
-// ============================================================================
-(* max_fanout = 50 *) reg reset_h = 1'b1;
-always @(posedge clk_400m) reset_h <= ~reset_n;
-
 // Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
 wire [7:0] lut_address = phase_with_offset[31:24];
 
@@ -154,8 +135,8 @@ wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe_cos];
 // Stage 2: phase_with_offset adds phase offset
 reg [31:0] phase_accumulator;
 
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         phase_accumulator <= 32'h00000000;
         phase_accum_reg   <= 32'h00000000;
         phase_with_offset <= 32'h00000000;
@@ -209,8 +190,8 @@ DSP48E1 #(
     .RSTA(1'b0),
     .RSTB(1'b0),
     .RSTM(1'b0),
-    .RSTP(reset_h),              // Reset P register (phase accumulator) — registered, max_fanout=50
+    .RSTP(!reset_n),             // Reset P register (phase accumulator) on !reset_n
-    .RSTC(reset_h),              // Reset C register (tuning word)       — registered, max_fanout=50
+    .RSTC(!reset_n),             // Reset C register (tuning word) on !reset_n
     .RSTALLCARRYIN(1'b0),
     .RSTALUMODE(1'b0),
     .RSTCTRL(1'b0),
@@ -264,8 +245,8 @@ DSP48E1 #(
 // Stage 1: Capture DSP48E1 P output into fabric register
 // Stage 2: Add phase offset to captured value
 // Split into two registered stages to break DSP48E1.P→CARRY4 critical path
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         phase_accum_reg   <= 32'h00000000;
         phase_with_offset <= 32'h00000000;
     end else if (phase_valid) begin
@@ -283,8 +264,8 @@ end
 //           Only 2 registers driven (lut_index_pipe + quadrant_pipe)
 //           Minimal fanout → short routes → easy timing
 // ============================================================================
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         lut_index_pipe_sin <= 6'b000000;
         lut_index_pipe_cos <= 6'b000000;
         quadrant_pipe      <= 2'b00;
@@ -300,8 +281,8 @@ end
 //           Registered address → combinational LUT6 read → register
 //           Only 1 logic level (LUT6), trivial timing
 // ============================================================================
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         sin_abs_reg <= 16'h0000;
         cos_abs_reg <= 16'h7FFF;
         quadrant_reg <= 2'b00;
@@ -317,8 +298,8 @@ end
 //          CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
 //          Also pass through abs values and quadrant for Stage 5
 // ============================================================================
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         sin_neg_reg <= 16'h0000;
         cos_neg_reg <= -16'h7FFF;
         sin_abs_reg2 <= 16'h0000;
@@ -337,8 +318,8 @@ end
 // Stage 5: Quadrant sign application → final sin/cos output
 //          Uses pre-computed negated values from Stage 4 — pure MUX, no arithmetic
 // ============================================================================
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         sin_out <= 16'h0000;
         cos_out <= 16'h7FFF;
     end else if (valid_pipe[4]) begin
@@ -366,8 +347,8 @@ end
 // ============================================================================
 // Valid pipeline and dds_ready (6-stage latency)
 // ============================================================================
-always @(posedge clk_400m) begin
+always @(posedge clk_400m or negedge reset_n) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         valid_pipe <= 6'b000000;
         dds_ready <= 1'b0;
     end else begin

9_Firmware/9_2_FPGA/rx_gain_control.v

@@ -169,11 +169,11 @@ endfunction
 // =========================================================================
 // Clamp a wider signed value to [-7, +7]
 function signed [3:0] clamp_gain;
-    input signed [5:0] val;  // 6-bit: covers [-22,+22] (max |gain|+step = 7+15)
+    input signed [4:0] val;  // 5-bit to handle overflow from add
     begin
-        if (val > 6'sd7)
+        if (val > 5'sd7)
             clamp_gain = 4'sd7;
-        else if (val < -6'sd7)
+        else if (val < -5'sd7)
             clamp_gain = -4'sd7;
         else
             clamp_gain = val[3:0];
@@ -246,15 +246,15 @@ always @(posedge clk or negedge reset_n) begin
                 // Use inclusive counts/peaks (accounting for simultaneous valid_in)
                 if (wire_frame_sat_incr || frame_sat_count > 8'd0) begin
                     // Clipping detected: reduce gain immediately (attack)
-                    agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain[3], agc_gain}) -
+                    agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain}) -
-                                           $signed({2'b00, agc_attack}));
+                                           $signed({1'b0, agc_attack}));
                     holdoff_counter <= agc_holdoff;  // Reset holdoff
                 end else if ((wire_frame_peak_update ? max_iq[14:7] : frame_peak[14:7])
                              < agc_target) begin
                     // Signal too weak: increase gain after holdoff expires
                     if (holdoff_counter == 4'd0) begin
-                        agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain[3], agc_gain}) +
+                        agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain}) +
-                                               $signed({2'b00, agc_decay}));
+                                               $signed({1'b0, agc_decay}));
                     end else begin
                         holdoff_counter <= holdoff_counter - 4'd1;
                     end

9_Firmware/9_3_GUI/radar_protocol.py

@@ -103,15 +103,6 @@ class Opcode(IntEnum):
     STATUS_REQUEST      = 0xFF
 
 
-# MCU-only commands — NOT dispatched to the FPGA opcode switch.
-# These values have no corresponding case in radar_system_top.v.
-# Listed here so the GUI can build and send them via build_command().
-# contract_parser.py filters MCU_ONLY_OPCODES out of the Python/Verilog
-# bidirectional check.
-FAULT_ACK = 0x40  # Exact 4-byte CDC packet; clears system_emergency_state
-MCU_ONLY_OPCODES: frozenset[int] = frozenset({0x40})
-
-
 # ============================================================================
 # Data Structures
 # ============================================================================

9_Firmware/9_3_GUI/test_v7.py

@@ -586,135 +586,6 @@ class TestSoftwareFPGA(unittest.TestCase):
         self.assertEqual(fpga.agc_holdoff, 0x0F)
 
 
-# ============================================================================
-# Test: live vs replay physical-unit parity — regression guard for unit drift
-#
-# Uses AST parse of workers.py (not inspect.getsource / import) so the test
-# runs in headless CI without PyQt6 — v7.workers imports PyQt6 unconditionally
-# at workers.py:24, and other worker tests here already use skipUnless(
-# _pyqt6_available()). Contract enforcement must not be gated on GUI deps.
-#
-# Asserts on AST nodes (Call / Attribute / BinOp), not source substrings, so
-# false-pass on comments or docstring wording is impossible.
-# ============================================================================
-
-
-class TestLiveReplayPhysicalUnitsParity(unittest.TestCase):
-    """Contract: live path (RadarDataWorker._run_host_dsp) and replay path
-    (ReplayWorker._emit_frame) both derive bin-to-physical conversion from
-    WaveformConfig — same source of truth, identical (range_m, velocity_ms)
-    for identical detections.
-
-    Regression context: before the fix, live path used
-    RadarSettings.velocity_resolution (default 1.0 in models.py:113) while
-    replay used WaveformConfig.velocity_resolution_mps (~5.343). Live GUI
-    therefore under-reported velocity by factor ~5.34x vs replay for
-    identical frames. See test_v7.py:449 for the WaveformConfig pin.
-    """
-
-    @staticmethod
-    def _parse_method(class_name: str, method_name: str):
-        """Return AST FunctionDef for class_name.method_name from workers.py,
-        without importing v7.workers (PyQt6-independent)."""
-        import ast
-        from pathlib import Path
-        path = Path(__file__).parent / "v7" / "workers.py"
-        tree = ast.parse(path.read_text(encoding="utf-8"))
-        for node in tree.body:
-            if isinstance(node, ast.ClassDef) and node.name == class_name:
-                for item in node.body:
-                    if isinstance(item, ast.FunctionDef) and item.name == method_name:
-                        return item
-        raise RuntimeError(f"{class_name}.{method_name} not found in workers.py")
-
-    @staticmethod
-    def _has_attribute_chain(tree, chain):
-        """True if AST tree contains a dotted attribute access matching chain.
-
-        Chain ('self', '_settings', 'range_resolution') matches
-        ``self._settings.range_resolution`` exactly.
-        """
-        import ast
-        for n in ast.walk(tree):
-            if isinstance(n, ast.Attribute):
-                parts = [n.attr]
-                cur = n.value
-                while isinstance(cur, ast.Attribute):
-                    parts.append(cur.attr)
-                    cur = cur.value
-                if isinstance(cur, ast.Name):
-                    parts.append(cur.id)
-                    parts.reverse()
-                    if tuple(parts) == tuple(chain):
-                        return True
-        return False
-
-    @staticmethod
-    def _has_call_to(tree, func_name):
-        """True if AST tree contains a call to a bare name (func_name())."""
-        import ast
-        for n in ast.walk(tree):
-            if (isinstance(n, ast.Call) and isinstance(n.func, ast.Name)
-                    and n.func.id == func_name):
-                return True
-        return False
-
-    @staticmethod
-    def _has_dbin_minus(tree, literal):
-        """True if AST tree contains ``dbin - <literal>`` binary op."""
-        import ast
-        for n in ast.walk(tree):
-            if (isinstance(n, ast.BinOp) and isinstance(n.op, ast.Sub)
-                    and isinstance(n.left, ast.Name) and n.left.id == "dbin"
-                    and isinstance(n.right, ast.Constant)
-                    and n.right.value == literal):
-                return True
-        return False
-
-    def test_live_path_uses_waveform_config(self):
-        """RadarDataWorker.__init__ must instantiate WaveformConfig() into
-        self._waveform; _run_host_dsp must read self._waveform.range_resolution_m
-        / velocity_resolution_mps — not self._settings equivalents."""
-        init = self._parse_method("RadarDataWorker", "__init__")
-        self.assertTrue(self._has_call_to(init, "WaveformConfig"),
-            "RadarDataWorker.__init__ must instantiate WaveformConfig() into self._waveform.")
-        method = self._parse_method("RadarDataWorker", "_run_host_dsp")
-        self.assertTrue(
-            self._has_attribute_chain(method, ("self", "_waveform", "range_resolution_m")),
-            "Live path must read self._waveform.range_resolution_m.")
-        self.assertTrue(
-            self._has_attribute_chain(method, ("self", "_waveform", "velocity_resolution_mps")),
-            "Live path must read self._waveform.velocity_resolution_mps. "
-            "RadarSettings.velocity_resolution default 1.0 caused ~5.34x "
-            "underreport vs replay (test_v7.py:449 pins ~5.343).")
-        self.assertFalse(self._has_attribute_chain(
-            method, ("self", "_settings", "range_resolution")),
-            "Live path still reads stale RadarSettings.range_resolution.")
-        self.assertFalse(self._has_attribute_chain(
-            method, ("self", "_settings", "velocity_resolution")),
-            "Live path still reads stale RadarSettings.velocity_resolution.")
-
-    def test_live_path_doppler_center_not_hardcoded(self):
-        """_run_host_dsp must derive doppler_center from frame shape, not
-        use hardcoded ``dbin - 16`` — mirrors processing.py:520."""
-        method = self._parse_method("RadarDataWorker", "_run_host_dsp")
-        self.assertFalse(self._has_dbin_minus(method, 16),
-            "Hardcoded doppler_center=16 breaks if frame shape changes. "
-            "Use frame.detections.shape[1] // 2 like processing.py:520.")
-
-    def test_replay_path_still_uses_waveform_config(self):
-        """Parity half: replay path (ReplayWorker._emit_frame) must keep
-        reading self._waveform.range_resolution_m / velocity_resolution_mps —
-        guards against someone breaking the replay side of the invariant."""
-        method = self._parse_method("ReplayWorker", "_emit_frame")
-        self.assertTrue(self._has_attribute_chain(
-            method, ("self", "_waveform", "range_resolution_m")),
-            "Replay path lost WaveformConfig range source of truth.")
-        self.assertTrue(self._has_attribute_chain(
-            method, ("self", "_waveform", "velocity_resolution_mps")),
-            "Replay path lost WaveformConfig velocity source of truth.")
-
-
 class TestSoftwareFPGASignalChain(unittest.TestCase):
     """SoftwareFPGA.process_chirps with real co-sim data."""
 

9_Firmware/9_3_GUI/v7/workers.py

@@ -23,7 +23,7 @@ import numpy as np
 
 from PyQt6.QtCore import QThread, QObject, QTimer, pyqtSignal
 
-from .models import RadarTarget, GPSData, RadarSettings, WaveformConfig
+from .models import RadarTarget, GPSData, RadarSettings
 from .hardware import (
     RadarAcquisition,
     RadarFrame,
@@ -84,7 +84,6 @@ class RadarDataWorker(QThread):
         self._recorder = recorder
         self._gps = gps_data_ref
         self._settings = settings or RadarSettings()
-        self._waveform = WaveformConfig()
         self._running = False
 
         # Frame queue for production RadarAcquisition → this thread
@@ -98,9 +97,6 @@ class RadarDataWorker(QThread):
         self._byte_count = 0
         self._error_count = 0
 
-    def set_waveform(self, wf: "WaveformConfig") -> None:
-        self._waveform = wf
-
     def stop(self):
         self._running = False
         if self._acquisition:
@@ -173,8 +169,8 @@ class RadarDataWorker(QThread):
         The FPGA already does: FFT, MTI, CFAR, DC notch.
         Host-side DSP adds: clustering, tracking, geo-coordinate mapping.
 
-        Bin-to-physical conversion uses self._waveform (WaveformConfig) to keep
+        Bin-to-physical conversion uses RadarSettings.range_resolution
-        live and replay units aligned. Override via set_waveform() if needed.
+        and velocity_resolution (should be calibrated to actual waveform).
         """
         targets: list[RadarTarget] = []
 
@@ -184,11 +180,8 @@ class RadarDataWorker(QThread):
 
         # Extract detections from FPGA CFAR flags
         det_indices = np.argwhere(frame.detections > 0)
-        r_res = self._waveform.range_resolution_m
+        r_res = self._settings.range_resolution
-        v_res = self._waveform.velocity_resolution_mps
+        v_res = self._settings.velocity_resolution
-        n_doppler = (frame.detections.shape[1] if frame.detections.ndim == 2
-                     else self._waveform.n_doppler_bins)
-        doppler_center = n_doppler // 2
 
         for idx in det_indices:
             rbin, dbin = idx
@@ -197,9 +190,8 @@ class RadarDataWorker(QThread):
 
             # Convert bin indices to physical units
             range_m = float(rbin) * r_res
-            # Doppler: centre bin = 0 m/s; positive bins = approaching.
+            # Doppler: centre bin (16) = 0 m/s; positive bins = approaching
-            # Derived from frame shape — mirrors processing.py:520.
+            velocity_ms = float(dbin - 16) * v_res
-            velocity_ms = float(dbin - doppler_center) * v_res
 
             # Apply pitch correction if GPS data available
             raw_elev = 0.0  # FPGA doesn't send elevation per-detection

9_Firmware/tests/cross_layer/contract_parser.py

@@ -108,23 +108,12 @@ class ConcatWidth:
 
 def parse_python_opcodes(filepath: Path | None = None) -> dict[int, OpcodeEntry]:
     """Parse the Opcode enum from radar_protocol.py.
-    Returns {opcode_value: OpcodeEntry}, excluding MCU_ONLY_OPCODES.
+    Returns {opcode_value: OpcodeEntry}.
-    MCU-only opcodes have no FPGA case statement and must not appear in
-    the bidirectional Python/Verilog contract check.
     """
     if filepath is None:
         filepath = GUI_DIR / "radar_protocol.py"
     text = filepath.read_text()
 
-    # Extract MCU_ONLY_OPCODES set so we can exclude those values below.
-    mcu_only: set[int] = set()
-    m_set = re.search(r'MCU_ONLY_OPCODES[^=]*=\s*frozenset\(\{([^}]*)\}\)', text)
-    if m_set:
-        for tok in m_set.group(1).split(','):
-            tok = tok.strip()
-            if tok.startswith(('0x', '0X')):
-                mcu_only.add(int(tok, 16))
-
     # Find the Opcode class body
     match = re.search(r'class Opcode\b.*?(?=\nclass |\Z)', text, re.DOTALL)
     if not match:
@@ -134,7 +123,6 @@ def parse_python_opcodes(filepath: Path | None = None) -> dict[int, OpcodeEntry]
     for m in re.finditer(r'(\w+)\s*=\s*(0x[0-9a-fA-F]+)', match.group()):
         name = m.group(1)
         value = int(m.group(2), 16)
-        if value not in mcu_only:
         opcodes[value] = OpcodeEntry(name=name, value=value)
     return opcodes
 

9_Firmware/tests/cross_layer/test_cross_layer_contract.py

@@ -26,14 +26,12 @@ layers agree (because both could be wrong).
 
 from __future__ import annotations
 
-import ast
 import os
 import re
 import struct
 import subprocess
 import tempfile
 from pathlib import Path
-from typing import ClassVar
 
 import pytest
 
@@ -627,420 +625,6 @@ class TestTier1AgcCrossLayerInvariant:
         )
 
 
-# ===================================================================
-# ADAR1000 channel→register round-trip invariant (issue #90)
-# ===================================================================
-#
-# Ground-truth invariant crossing three system layers:
-#   Chip (datasheet) -> Driver (MCU helpers) -> Application (callers).
-#
-# For every logical element ch in {0,1,2,3} (hardware channels CH1..CH4),
-# the round-trip
-#     caller_expr(ch) --> helper_offset(channel) * stride --> base + off
-# must land on the physical register REG_CH{ch+1}_* defined in the ADI
-# ADAR1000 register map parsed from ADAR1000_Manager.h.
-#
-# Catches:
-#   * #90 channel rotation regardless of which side is fixed (caller OR helper).
-#   * Wrong stride (e.g. phase written with stride 1 instead of 2).
-#   * Bad mask (e.g. `channel & 0x07`, `channel & 0x01`).
-#   * Wrong base register in a helper.
-#   * New setter added with mismatched convention.
-#   * Caller moved to a file the test no longer scans (fails loudly).
-#
-# Cannot be defeated by:
-#   * Renaming/refactoring helper layout: the setter coverage test
-#     (`test_helper_sites_exist_for_all_setters`) catches missing parse.
-#   * Changing 0x03 to 3 or adding a named constant: the offset is
-#     evaluated symbolically via AST, not matched by regex.
-
-
-def _parse_adar_register_map(header_text):
-    """Extract `#define REG_CHn_(RX|TX)_(GAIN|PHS_I|PHS_Q)` values."""
-    regs = {}
-    for m in re.finditer(
-        r"^#define\s+(REG_CH[1-4]_(?:RX|TX)_(?:GAIN|PHS_I|PHS_Q))\s+(0x[0-9A-Fa-f]+)",
-        header_text,
-        re.MULTILINE,
-    ):
-        regs[m.group(1)] = int(m.group(2), 16)
-    return regs
-
-
-def _safe_eval_int_expr(expr, **variables):
-    """
-    Evaluate a small integer expression with +, -, *, &, |, ^, ~, <<, >>.
-    Python's & / | / ^ / ~ / << / >> have the same semantics as C for the
-    operand widths we care about here (uint8_t after the mask makes the
-    result fit in 0..3). No floating point, no function calls, no names
-    outside ``variables``.
-
-    SECURITY: ``expr`` MUST come from a trusted source -- specifically,
-    C/C++ source text under version control in this repository (e.g.
-    arguments parsed out of ``main.cpp``/``ADAR1000_AGC.cpp``).  Although
-    the AST whitelist below rejects function calls, attribute access,
-    subscripts, and any name not in ``variables``, ``eval`` is still
-    invoked on the compiled tree.  Do NOT pass user-supplied / network /
-    GUI input here.
-    """
-    tree = ast.parse(expr, mode="eval")
-    allowed = (
-        ast.Expression, ast.BinOp, ast.UnaryOp, ast.Constant,
-        ast.Name, ast.Load,
-        ast.Add, ast.Sub, ast.Mult, ast.Mod, ast.FloorDiv,
-        ast.BitAnd, ast.BitOr, ast.BitXor,
-        ast.USub, ast.UAdd, ast.Invert,
-        ast.LShift, ast.RShift,
-    )
-    for node in ast.walk(tree):
-        if not isinstance(node, allowed):
-            raise ValueError(
-                f"disallowed AST node {type(node).__name__!s} in `{expr}`"
-            )
-    return eval(
-        compile(tree, "<expr>", "eval"),
-        {"__builtins__": {}},
-        variables,
-    )
-
-
-def _extract_adar_helper_sites(manager_cpp, setter_names):
-    """
-    For each setter, locate the body of ``void ADAR1000Manager::<setter>``
-    and return a list of (setter, base_register, offset_expr_c, stride)
-    for every ``REG_CHn_XXX + <expr>`` memory-address assignment.
-    """
-    sites = []
-    for setter in setter_names:
-        m = re.search(
-            rf"void\s+ADAR1000Manager::{setter}\s*\([^)]*\)\s*\{{(.+?)^\}}",
-            manager_cpp,
-            re.MULTILINE | re.DOTALL,
-        )
-        if not m:
-            continue
-        body = m.group(1)
-        for access in re.finditer(
-            r"=\s*(REG_CH[1-4]_(?:RX|TX)_(?:GAIN|PHS_I|PHS_Q))\s*\+\s*([^;]+);",
-            body,
-        ):
-            base = access.group(1)
-            rhs = access.group(2).strip()
-            # Trailing `* <integer>` = stride multiplier (2 for phase I/Q).
-            stride_match = re.match(r"(.+?)\s*\*\s*(\d+)\s*$", rhs)
-            if stride_match:
-                offset_expr = stride_match.group(1).strip()
-                stride = int(stride_match.group(2))
-            else:
-                offset_expr = rhs
-                stride = 1
-            sites.append((setter, base, offset_expr, stride))
-    return sites
-
-
-# Method-definition line pattern: `[qualifier...] <ret-type> <Class>::<setter>(`
-# Covers: plain `void X::f(`, `inline void X::f(`, `static bool X::f(`, etc.
-_DEFN_RE = re.compile(
-    r"^\s*(?:inline\s+|static\s+|virtual\s+|constexpr\s+|explicit\s+)*"
-    r"(?:void|bool|uint\w+|int\w*|auto)\s+\S+::\w+\s*\("
-)
-
-
-def _extract_adar_caller_sites(sources, setter):
-    """
-    Find every call ``<obj>.<setter>(dev, <channel_expr>, ...)`` across
-    ``sources = [(filename, text), ...]``. Returns (filename, line_no,
-    channel_expr) for each. Skips function declarations/definitions.
-
-    Arg list up to matching `)`: restricted to a single line. All existing
-    call sites fit on one line; a future multi-line refactor would drop
-    callers from the scan, which the round-trip test surfaces loudly via
-    `assert callers` (rather than silently missing a site).
-    """
-    out = []
-    call_re = re.compile(rf"\b{setter}\s*\(([^;]*?)\)\s*;")
-    for filename, text in sources:
-        for line_no, line in enumerate(text.splitlines(), start=1):
-            # Skip method definition / declaration lines.
-            if _DEFN_RE.match(line):
-                continue
-            cm = call_re.search(line)
-            if not cm:
-                continue
-            args = _split_top_level_commas(cm.group(1))
-            if len(args) < 2:
-                continue
-            channel_expr = args[1].strip()
-            out.append((filename, line_no, channel_expr))
-    return out
-
-
-def _split_top_level_commas(text):
-    """Split on commas that sit at paren-depth 0 (ignores nested calls)."""
-    parts, depth, cur = [], 0, []
-    for ch in text:
-        if ch == "(":
-            depth += 1
-            cur.append(ch)
-        elif ch == ")":
-            depth -= 1
-            cur.append(ch)
-        elif ch == "," and depth == 0:
-            parts.append("".join(cur))
-            cur = []
-        else:
-            cur.append(ch)
-    if cur:
-        parts.append("".join(cur))
-    return parts
-
-
-class TestTier1Adar1000ChannelRegisterRoundTrip:
-    """
-    Cross-layer round-trip: caller channel expr -> helper offset formula
-    -> physical register address must equal REG_CH{ch+1}_* for every
-    caller and every ch in {0,1,2,3}.
-
-    See module-level block comment above and upstream issue #90.
-    """
-
-    _SETTERS = (
-        "adarSetRxPhase",
-        "adarSetTxPhase",
-        "adarSetRxVgaGain",
-        "adarSetTxVgaGain",
-    )
-
-    # Register base -> stride override. Parsed values of stride are
-    # trusted; this table is the independent ground truth for cross-check.
-    _EXPECTED_STRIDE: ClassVar[dict[str, int]] = {
-        "REG_CH1_RX_GAIN": 1,
-        "REG_CH1_TX_GAIN": 1,
-        "REG_CH1_RX_PHS_I": 2,
-        "REG_CH1_RX_PHS_Q": 2,
-        "REG_CH1_TX_PHS_I": 2,
-        "REG_CH1_TX_PHS_Q": 2,
-    }
-
-    @classmethod
-    def setup_class(cls):
-        cls.header_txt = (cp.MCU_LIB_DIR / "ADAR1000_Manager.h").read_text()
-        cls.manager_txt = (cp.MCU_LIB_DIR / "ADAR1000_Manager.cpp").read_text()
-        cls.reg_map = _parse_adar_register_map(cls.header_txt)
-        cls.helper_sites = _extract_adar_helper_sites(
-            cls.manager_txt, cls._SETTERS,
-        )
-        # Auto-discover every C++ TU under the MCU tree so a new caller
-        # added to e.g. a future ``ADAR1000_Calibration.cpp`` cannot
-        # silently escape the round-trip check (issue #90 reviewer note).
-        # Exclude any path containing a ``tests`` segment so this test
-        # does not parse its own fixtures.  The resulting list is
-        # deterministic (sorted) for reproducible parametrization.
-        scanned = []
-        seen = set()
-        for root in (cp.MCU_LIB_DIR, cp.MCU_CODE_DIR):
-            for path in sorted(root.rglob("*.cpp")):
-                if "tests" in path.parts:
-                    continue
-                if path in seen:
-                    continue
-                seen.add(path)
-                scanned.append((path.name, path.read_text()))
-        cls.sources = scanned
-        # Sanity: the two TUs known to call ADAR1000 setters at the time
-        # of issue #90 must be in scope.  If a future refactor renames or
-        # moves them this assert fires loudly rather than silently
-        # passing an empty round-trip.
-        scanned_names = {n for (n, _) in scanned}
-        for required in ("ADAR1000_AGC.cpp", "main.cpp", "ADAR1000_Manager.cpp"):
-            assert required in scanned_names, (
-                f"Auto-discovery missed `{required}`; check MCU_LIB_DIR / "
-                f"MCU_CODE_DIR roots in contract_parser.py."
-            )
-
-    # ---------- Tier A: chip ground truth ----------------------------
-
-    def test_register_map_gain_stride_is_one_per_channel(self):
-        """Datasheet invariant: RX/TX VGA gain registers are 1 byte apart."""
-        for kind in ("RX_GAIN", "TX_GAIN"):
-            for n in range(1, 4):
-                delta = (
-                    self.reg_map[f"REG_CH{n+1}_{kind}"]
-                    - self.reg_map[f"REG_CH{n}_{kind}"]
-                )
-                assert delta == 1, (
-                    f"ADAR1000 register map invariant broken: "
-                    f"REG_CH{n+1}_{kind} - REG_CH{n}_{kind} = {delta}, "
-                    f"datasheet says 1. Either the header was mis-edited "
-                    f"or ADI released a part with a different map."
-                )
-
-    def test_register_map_phase_stride_is_two_per_channel(self):
-        """Datasheet invariant: phase I/Q pairs occupy 2 bytes per channel."""
-        for kind in ("RX_PHS_I", "RX_PHS_Q", "TX_PHS_I", "TX_PHS_Q"):
-            for n in range(1, 4):
-                delta = (
-                    self.reg_map[f"REG_CH{n+1}_{kind}"]
-                    - self.reg_map[f"REG_CH{n}_{kind}"]
-                )
-                assert delta == 2, (
-                    f"ADAR1000 register map invariant broken: "
-                    f"REG_CH{n+1}_{kind} - REG_CH{n}_{kind} = {delta}, "
-                    f"datasheet says 2."
-                )
-
-    # ---------- Tier B: driver parses cleanly -------------------------
-
-    def test_helper_sites_exist_for_all_setters(self):
-        """Every channel-indexed setter must parse at least one register access."""
-        found = {s for (s, _, _, _) in self.helper_sites}
-        missing = set(self._SETTERS) - found
-        assert not missing, (
-            f"Helper parse failed for: {sorted(missing)}. "
-            f"Either a setter was renamed (update _SETTERS), moved out of "
-            f"ADAR1000_Manager.cpp (extend scan scope), or the register-"
-            f"access form changed beyond `REG_CHn_XXX + <expr>`. "
-            f"DO NOT weaken this test without reviewing issue #90."
-        )
-
-    def test_helper_parsed_stride_matches_datasheet(self):
-        """Parsed helper strides must match the datasheet register spacing."""
-        for setter, base, offset_expr, stride in self.helper_sites:
-            expected = self._EXPECTED_STRIDE.get(base)
-            assert expected is not None, (
-                f"{setter} writes to unrecognised base `{base}`. "
-                f"If ADI added a new channel-indexed register block, "
-                f"extend _EXPECTED_STRIDE with its datasheet stride."
-            )
-            assert stride == expected, (
-                f"{setter} helper uses stride {stride} for `{base}` "
-                f"(`{offset_expr} * {stride}`), datasheet says {expected}. "
-                f"Writes will overlap or skip channels."
-            )
-
-    # ---------- Tier C: round-trip to physical register ---------------
-
-    def test_all_callers_pass_one_based_channel(self):
-        """
-        INVARIANT: every caller's channel argument must, for ch in
-        {0,1,2,3}, evaluate to a 1-based ADI channel index in {1,2,3,4}.
-
-        The bug fixed in #90 was that helpers used ``channel & 0x03``
-        directly, so a caller passing bare ``ch`` (0..3) appeared to
-        work for ch=0..2 and silently aliased ch=3 onto CH4-then-CH1.
-        After the fix, helpers do ``(channel - 1) & 0x03`` and reject
-        ``channel < 1 || channel > 4``.  A future caller written as
-        ``adarSetRxPhase(dev, ch, ...)`` (bare 0-based) or
-        ``adarSetRxPhase(dev, 0, ...)`` (literal 0) would silently be
-        dropped by the bounds-check at runtime; this test catches it at
-        CI time instead.
-
-        The check intentionally lives one tier above the round-trip test
-        so the failure message points the reader at the API contract
-        (1-based per ADI datasheet & ADAR1000_AGC.cpp:76) rather than at
-        a register-arithmetic mismatch.
-        """
-        offenders = []
-        for setter in self._SETTERS:
-            callers = _extract_adar_caller_sites(self.sources, setter)
-            for filename, line_no, ch_expr in callers:
-                for ch in range(4):
-                    try:
-                        channel_val = _safe_eval_int_expr(ch_expr, ch=ch)
-                    except (NameError, KeyError, ValueError) as e:
-                        offenders.append(
-                            f"  - {filename}:{line_no} {setter}("
-                            f"…, `{ch_expr}`, …) -- ch={ch}: "
-                            f"unparseable ({e})"
-                        )
-                        continue
-                    if channel_val not in (1, 2, 3, 4):
-                        offenders.append(
-                            f"  - {filename}:{line_no} {setter}("
-                            f"…, `{ch_expr}`, …) -- ch={ch}: "
-                            f"channel={channel_val}, expected 1..4"
-                        )
-        assert not offenders, (
-            "ADAR1000 1-based channel API contract violated. The fix "
-            "for issue #90 requires every caller to pass channel in "
-            "{1,2,3,4} (CH1..CH4 per ADI datasheet). Bare 0-based ch "
-            "or a literal 0 will be silently dropped by the helper's "
-            "bounds check.  Offenders:\n" + "\n".join(offenders)
-        )
-
-    @pytest.mark.parametrize(
-        "setter",
-        [
-            "adarSetRxPhase",
-            "adarSetTxPhase",
-            "adarSetRxVgaGain",
-            "adarSetTxVgaGain",
-        ],
-    )
-    def test_round_trip_lands_on_intended_physical_channel(self, setter):
-        """
-        INVARIANT: for every caller of ``<setter>`` and every logical ch
-        in {0,1,2,3}, the effective register address equals
-        REG_CH{ch+1}_*. Catches #90 regardless of fix direction.
-        """
-        callers = _extract_adar_caller_sites(self.sources, setter)
-        assert callers, (
-            f"No callers of `{setter}` found. Either the test scope is "
-            f"incomplete (extend `setup_class.sources`) or the symbol was "
-            f"inlined/removed. A blind test is a dangerous test — "
-            f"investigate before weakening."
-        )
-        helpers = [
-            (b, e, s) for (nm, b, e, s) in self.helper_sites if nm == setter
-        ]
-        assert helpers, f"helper body for `{setter}` not parseable"
-
-        errors = []
-        for filename, line_no, ch_expr in callers:
-            for ch in range(4):
-                try:
-                    channel_val = _safe_eval_int_expr(ch_expr, ch=ch)
-                except (NameError, KeyError, ValueError) as e:
-                    pytest.fail(
-                        f"{filename}:{line_no}: caller channel expression "
-                        f"`{ch_expr}` uses symbol outside {{ch}} or a "
-                        f"disallowed operator ({e}). Extend "
-                        f"_safe_eval_int_expr variables or rewrite the "
-                        f"call site with a supported expression."
-                    )
-                for base_sym, offset_expr, stride in helpers:
-                    try:
-                        offset = _safe_eval_int_expr(
-                            offset_expr, channel=channel_val,
-                        )
-                    except (NameError, KeyError, ValueError) as e:
-                        pytest.fail(
-                            f"helper `{setter}` offset expr "
-                            f"`{offset_expr}` uses symbol outside "
-                            f"{{channel}} or a disallowed operator ({e}). "
-                            f"Extend _safe_eval_int_expr variables if new "
-                            f"driver state is introduced."
-                        )
-                    final = self.reg_map[base_sym] + offset * stride
-                    expected_sym = base_sym.replace("CH1", f"CH{ch + 1}")
-                    expected = self.reg_map[expected_sym]
-                    if final != expected:
-                        errors.append(
-                            f"  - {filename}:{line_no} {setter} "
-                            f"caller `{ch_expr}` | ch={ch} -> "
-                            f"channel={channel_val} -> "
-                            f"`{base_sym} + ({offset_expr})"
-                            f"{' * ' + str(stride) if stride != 1 else ''}`"
-                            f" = 0x{final:03X} "
-                            f"(expected {expected_sym} = 0x{expected:03X})"
-                        )
-        assert not errors, (
-            f"ADAR1000 channel round-trip FAILED for {setter} "
-            f"({len(errors)} mismatches) — writes routed to wrong physical "
-            f"channel. This is issue #90.\n" + "\n".join(errors)
-        )
-
-
 class TestTier1DataPacketLayout:
     """Verify data packet byte layout matches between Python and Verilog."""