Merge pull request #108 from NawfalMotii79/fix/adar1000-channel-rotation

fix(adar1000): correct 1-based channel indexing in setters (issue #90)

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_AGC.cpp

@@ -24,7 +24,6 @@ ADAR1000_AGC::ADAR1000_AGC()
     , saturation_event_count(0)
 {
     memset(cal_offset, 0, sizeof(cal_offset));
-    if (holdoff_frames == 0) holdoff_frames = 1;
 }
 
 // ---------------------------------------------------------------------------

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/USBHandler.cpp

@@ -13,7 +13,6 @@ void USBHandler::reset() {
     start_flag_received = false;
     buffer_index = 0;
     current_settings.resetToDefaults();
-    fault_ack_received = false;
 }
 
 void USBHandler::processUSBData(const uint8_t* data, uint32_t length) {
@@ -24,18 +23,6 @@ void USBHandler::processUSBData(const uint8_t* data, uint32_t length) {
     
     DIAG("USB", "processUSBData: %lu bytes, state=%d", (unsigned long)length, (int)current_state);
     
-    // FAULT_ACK: host sends exactly 4 bytes [0x40, 0x00, 0x00, 0x00].
-    // Requires exact 4-byte packet length: settings packets are always
-    // >= 82 bytes, so a lone 4-byte payload is unambiguous. Scanning
-    // inside larger packets would false-trigger on the IEEE 754
-    // encoding of 2.0 (0x4000000000000000) embedded in settings doubles.
-    static const uint8_t FAULT_ACK_SEQ[4] = {0x40, 0x00, 0x00, 0x00};
-    if (length == 4 && memcmp(data, FAULT_ACK_SEQ, 4) == 0) {
-        fault_ack_received = true;
-        DIAG("USB", "FAULT_ACK received");
-        return;
-    }
-    
     switch (current_state) {
         case USBState::WAITING_FOR_START:
             processStartFlag(data, length);

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/USBHandler.h

@@ -29,11 +29,6 @@ public:
     // Reset USB handler
     void reset();
 
-    // Fault-acknowledgement: host sends FAULT_ACK (0x40) to clear
-    // system_emergency_state and exit the safe-mode blink loop.
-    bool isFaultAckReceived() const { return fault_ack_received; }
-    void clearFaultAck()            { fault_ack_received = false; }
-
 private:
     RadarSettings current_settings;
     USBState current_state;
@@ -43,7 +38,6 @@ private:
     static constexpr uint32_t MAX_BUFFER_SIZE = 256;
     uint8_t usb_buffer[MAX_BUFFER_SIZE];
     uint32_t buffer_index;
-    bool fault_ack_received;
     
     void processStartFlag(const uint8_t* data, uint32_t length);
     void processSettingsData(const uint8_t* data, uint32_t length);

9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h

@@ -112,7 +112,7 @@ extern "C" {
  *   "BF"    -- ADAR1000 beamformer
  *   "PA"    -- Power amplifier bias/monitoring
  *   "FPGA"  -- FPGA communication and handshake
- *   "USB"   -- USB data path (FT2232H production / FT601 premium)
+ *   "USB"   -- FT601 USB data path
  *   "PWR"   -- Power sequencing and rail monitoring
  *   "IMU"   -- IMU/GPS/barometer sensors
  *   "MOT"   -- Stepper motor/scan mechanics

9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp

@@ -627,7 +627,7 @@ typedef enum {
 
 static SystemError_t last_error = ERROR_NONE;
 static uint32_t error_count = 0;
-static volatile bool system_emergency_state = false;
+static bool system_emergency_state = false;
 
 // Error handler function
 SystemError_t checkSystemHealth(void) {
@@ -2054,10 +2054,6 @@ int main(void)
 	            HAL_GPIO_TogglePin(LED_3_GPIO_Port, LED_3_Pin);
 	            HAL_GPIO_TogglePin(LED_4_GPIO_Port, LED_4_Pin);
 	            HAL_Delay(250);
-	            if (usbHandler.isFaultAckReceived()) {
-	                system_emergency_state = false;
-	                usbHandler.clearFaultAck();
-	            }
 	        }
 	        DIAG("SYS", "Exited safe mode blink loop -- system_emergency_state cleared");
 	    }

9_Firmware/9_1_Microcontroller/tests/Makefile

@@ -70,8 +70,7 @@ TESTS_STANDALONE := test_bug12_pa_cal_loop_inverted \
                     test_gap3_idq_periodic_reread \
                     test_gap3_emergency_state_ordering \
                     test_gap3_overtemp_emergency_stop \
-                    test_gap3_health_watchdog_cold_start \
-                    test_gap3_fault_ack_clears_emergency
+                    test_gap3_health_watchdog_cold_start
 
 # Tests that need platform_noos_stm32.o + mocks
 TESTS_WITH_PLATFORM := test_bug11_platform_spi_transmit_only
@@ -179,9 +178,6 @@ test_gap3_overtemp_emergency_stop: test_gap3_overtemp_emergency_stop.c
 test_gap3_health_watchdog_cold_start: test_gap3_health_watchdog_cold_start.c
 	$(CC) $(CFLAGS) $< -o $@
 
-test_gap3_fault_ack_clears_emergency: test_gap3_fault_ack_clears_emergency.c
-	$(CC) $(CFLAGS) $< -o $@
-
 # Tests that need platform_noos_stm32.o + mocks
 $(TESTS_WITH_PLATFORM): %: %.c $(MOCK_OBJS) $(PLATFORM_OBJ)
 	$(CC) $(CFLAGS) $(INCLUDES) $< $(MOCK_OBJS) $(PLATFORM_OBJ) -o $@

9_Firmware/9_1_Microcontroller/tests/test_gap3_fault_ack_clears_emergency.c

@@ -1,121 +0,0 @@
-/*******************************************************************************
- * test_gap3_fault_ack_clears_emergency.c
- *
- * Verifies the FAULT_ACK clear path for system_emergency_state:
- *   - USBHandler detects exactly [0x40, 0x00, 0x00, 0x00] in a 4-byte packet
- *   - Detection is false-positive-free: larger packets (settings data) carrying
- *     the same bytes as a subsequence must NOT trigger the ack
- *   - Main-loop blink logic clears system_emergency_state on receipt
- *
- * Logic extracted from USBHandler.cpp + main.cpp to mirror the actual code
- * paths without requiring HAL headers.
- ******************************************************************************/
-#include <assert.h>
-#include <stdio.h>
-#include <stdbool.h>
-#include <string.h>
-#include <stdint.h>
-
-/* ── Simulated USBHandler state ─────────────────────────────────────────── */
-static bool fault_ack_received = false;
-static volatile bool system_emergency_state = false;
-
-static const uint8_t FAULT_ACK_SEQ[4] = {0x40, 0x00, 0x00, 0x00};
-
-/* Mirrors USBHandler::processUSBData() detection logic */
-static void sim_processUSBData(const uint8_t *data, uint32_t length)
-{
-    if (data == NULL || length == 0) return;
-    if (length == 4 && memcmp(data, FAULT_ACK_SEQ, 4) == 0) {
-        fault_ack_received = true;
-        return;
-    }
-    /* (normal state machine omitted — not under test here) */
-}
-
-/* Mirrors one iteration of the blink loop in main.cpp */
-static void sim_blink_iteration(void)
-{
-    /* HAL_GPIO_TogglePin + HAL_Delay omitted */
-    if (fault_ack_received) {
-        system_emergency_state = false;
-        fault_ack_received = false;
-    }
-}
-
-int main(void)
-{
-    printf("=== Gap-3 FAULT_ACK clears system_emergency_state ===\n");
-
-    /* Test 1: exact 4-byte FAULT_ACK packet sets the flag */
-    printf("  Test 1: exact FAULT_ACK packet detected... ");
-    fault_ack_received = false;
-    const uint8_t ack_pkt[4] = {0x40, 0x00, 0x00, 0x00};
-    sim_processUSBData(ack_pkt, 4);
-    assert(fault_ack_received == true);
-    printf("PASS\n");
-
-    /* Test 2: flag cleared and system_emergency_state exits blink loop */
-    printf("  Test 2: blink loop exits on FAULT_ACK... ");
-    system_emergency_state = true;
-    fault_ack_received = true;
-    sim_blink_iteration();
-    assert(system_emergency_state == false);
-    assert(fault_ack_received == false);
-    printf("PASS\n");
-
-    /* Test 3: blink loop does NOT exit without ack */
-    printf("  Test 3: blink loop holds without ack... ");
-    system_emergency_state = true;
-    fault_ack_received = false;
-    sim_blink_iteration();
-    assert(system_emergency_state == true);
-    printf("PASS\n");
-
-    /* Test 4: settings-sized packet carrying [0x40,0x00,0x00,0x00] as first
-     * 4 bytes does NOT trigger ack (IEEE 754 double 2.0 = 0x4000000000000000) */
-    printf("  Test 4: settings packet with 2.0 double does not false-trigger... ");
-    fault_ack_received = false;
-    uint8_t settings_pkt[82];
-    memset(settings_pkt, 0, sizeof(settings_pkt));
-    /* First 4 bytes look like FAULT_ACK but packet length is 82 */
-    settings_pkt[0] = 0x40; settings_pkt[1] = 0x00;
-    settings_pkt[2] = 0x00; settings_pkt[3] = 0x00;
-    sim_processUSBData(settings_pkt, sizeof(settings_pkt));
-    assert(fault_ack_received == false);
-    printf("PASS\n");
-
-    /* Test 5: 3-byte packet (truncated) does not trigger */
-    printf("  Test 5: truncated 3-byte packet ignored... ");
-    fault_ack_received = false;
-    const uint8_t short_pkt[3] = {0x40, 0x00, 0x00};
-    sim_processUSBData(short_pkt, 3);
-    assert(fault_ack_received == false);
-    printf("PASS\n");
-
-    /* Test 6: wrong opcode byte in 4-byte packet does not trigger */
-    printf("  Test 6: wrong opcode (0x28 AGC_ENABLE) not detected as FAULT_ACK... ");
-    fault_ack_received = false;
-    const uint8_t agc_pkt[4] = {0x28, 0x00, 0x00, 0x01};
-    sim_processUSBData(agc_pkt, 4);
-    assert(fault_ack_received == false);
-    printf("PASS\n");
-
-    /* Test 7: multiple blink iterations — loop stays active until ack */
-    printf("  Test 7: loop stays active across multiple iterations until ack... ");
-    system_emergency_state = true;
-    fault_ack_received = false;
-    sim_blink_iteration();
-    assert(system_emergency_state == true);
-    sim_blink_iteration();
-    assert(system_emergency_state == true);
-    /* Now ack arrives */
-    sim_processUSBData(ack_pkt, 4);
-    assert(fault_ack_received == true);
-    sim_blink_iteration();
-    assert(system_emergency_state == false);
-    printf("PASS\n");
-
-    printf("\n=== Gap-3 FAULT_ACK: ALL 7 TESTS PASSED ===\n\n");
-    return 0;
-}

9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v

@@ -32,50 +32,11 @@ localparam COMB_WIDTH = 28;
 // adjacent DSP48E1 tiles — zero fabric delay, guaranteed to meet 400+ MHz
 // on 7-series regardless of speed grade.
 //
-// Active-high reset derived from reset_n (inverted and REGISTERED).
+// Active-high reset derived from reset_n (inverted).
 // CEP (clock enable for P register) gated by data_valid.
-//
-// ----------------------------------------------------------------------------
-// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
-// ----------------------------------------------------------------------------
-// Previously this was a combinational wire (`wire reset_h = ~reset_n`). Vivado
-// collapsed all per-module inversions across the DDC hierarchy into a SINGLE
-// shared LUT1, whose output fanned out to 702 loads (DSP48E1 RSTP/RSTB/RSTC
-// plus FDRE R pins of all comb-stage DSP48E1s inferred via use_dsp="yes").
-// Route delay alone on that net was 2.019–2.268 ns — nearly one full 2.5 ns
-// period. Timing failed by 626 ps on the 400 MHz domain.
-//
-// Fix: convert reset_h to a REGISTERED signal with (* max_fanout = 50 *).
-// Vivado treats max_fanout on a REG (not a wire) as authoritative and
-// replicates the register into N copies, each placed near its ≈50 loads.
-// Invariants preserved:
-//   I1 (correctness):       reset_h is still active-high, equals ~reset_n
-//                           after one clk edge; CIC reset is a RECEIVER-side
-//                           synchronizer anyway (driven by reset_n_400m which
-//                           is already sync'd in the parent DDC), so adding
-//                           one more clk cycle of latency is safe.
-//   I2 (glitch-free):       Registered output => inherently glitch-free,
-//                           feeding DSP48E1 RST pins (which are synchronous
-//                           to CLK, so they capture on the same edge anyway).
-//   I3 (power-up safety):   reset_h is NOT async-reset itself. On power-up,
-//                           FDRE INIT=0 starts reset_h LOW. First clk edge
-//                           samples ~reset_n which is LOW on power-up (the
-//                           parent DDC holds reset_n_400m low until the 2-
-//                           stage synchronizer releases), so reset_h goes
-//                           HIGH on cycle 1 and all DSPs see reset during
-//                           the following cycles. System is held in reset
-//                           for enough cycles that any initial register
-//                           state garbage is overwritten. ✅
-//   I4 (reset de-assertion):reset_h goes LOW one cycle AFTER reset_n_400m
-//                           goes HIGH. Downstream DSPs come out of reset on
-//                           the next clk edge after that. Total latency
-//                           from system reset release to first valid sample:
-//                           2 (sync chain) + 1 (reset_h reg) + 1 (first
-//                           DSP output) = 4 cycles at 400 MHz = 10 ns.
-//                           Negligible vs system reset assertion duration.
-// ----------------------------------------------------------------------------
-(* max_fanout = 50 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
-always @(posedge clk) reset_h <= ~reset_n;
+// ============================================================================
+
+wire reset_h = ~reset_n;  // active-high reset for DSP48E1 RSTP
 
 // Sign-extended input for integrator_0 C port (48-bit)
 wire [ACC_WIDTH-1:0] data_in_c = {{(ACC_WIDTH-18){data_in[17]}}, data_in};
@@ -738,11 +699,10 @@ initial begin
 end
 
 // Decimation control + monitoring (integrators are now DSP48E1 instances)
-// Sync reset via reset_h (registered, max_fanout=50) — eliminates the shared
-// LUT1 inverter that previously fanned out to all fabric FDRE R pins plus
-// DSP48E1 RST pins (702 loads total). See "RESET FAN-OUT INVARIANT" at top.
+// Sync reset: enables FDRE inference for better timing at 400 MHz.
+// Reset is already synchronous to clk via reset synchronizer in parent module.
 always @(posedge clk) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         integrator_sampled <= 0;
         decimation_counter <= 0;
         data_valid_delayed <= 0;
@@ -795,9 +755,9 @@ always @(posedge clk) begin
 end
 
 // Pipeline the valid signal for comb section
-// Sync reset via reset_h — same replicated-register source as DSP48E1 RSTs.
+// Sync reset: matches decimation control block reset style.
 always @(posedge clk) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         data_valid_comb <= 0;
         data_valid_comb_pipe <= 0;
         data_valid_comb_0_out <= 0;
@@ -832,7 +792,7 @@ end
 //   - Each stage: comb[i] = comb[i-1] - comb_delay[i][last]
 
 always @(posedge clk) begin
-    if (reset_h) begin
+    if (!reset_n) begin
         for (i = 0; i < STAGES; i = i + 1) begin
             comb[i] <= 0;
             for (j = 0; j < COMB_DELAY; j = j + 1) begin

9_Firmware/9_2_FPGA/constraints/README.md

@@ -32,8 +32,8 @@ the `USB_MODE` parameter in `radar_system_top.v`:
 
 | USB_MODE | Interface | Bus Width | Speed | Board Target |
 |----------|-----------|-----------|-------|--------------|
-| 0 | FT601 (USB 3.0) | 32-bit | 100 MHz | 200T premium dev board |
-| 1 (default) | FT2232H (USB 2.0) | 8-bit | 60 MHz | 50T production board |
+| 0 (default) | FT601 (USB 3.0) | 32-bit | 100 MHz | 200T premium dev board |
+| 1 | FT2232H (USB 2.0) | 8-bit | 60 MHz | 50T production board |
 
 ### How USB_MODE Works
 
@@ -72,8 +72,7 @@ The parameter is set via a **wrapper module** that overrides the default:
   ```
 
 - **200T dev board**: `radar_system_top` is used directly as the top module.
-  `USB_MODE` defaults to `1` (FT2232H) since production is the primary target.
-  Override with `.USB_MODE(0)` for FT601 builds.
+  `USB_MODE` defaults to `0` (FT601). No wrapper needed.
 
 ### RTL Files by USB Interface
 
@@ -159,7 +158,7 @@ The build scripts automatically select the correct top module and constraints:
 
 You do NOT need to set `USB_MODE` manually. The top module selection handles it:
 - `radar_system_top_50t` forces `USB_MODE=1` internally
-- `radar_system_top` defaults to `USB_MODE=1` (FT2232H, production default)
+- `radar_system_top` defaults to `USB_MODE=0`
 
 ## How to Select Constraints in Vivado
 
@@ -191,9 +190,9 @@ read_xdc constraints/te0713_te0701_minimal.xdc
 | Target | Top module | USB_MODE | USB Interface | Notes |
 |--------|------------|----------|---------------|-------|
 | 50T Production (FTG256) | `radar_system_top_50t` | 1 | FT2232H (8-bit) | Wrapper sets USB_MODE=1, ties off FT601 |
-| 200T Dev (FBG484) | `radar_system_top` | 0 (override) | FT601 (32-bit) | Build script overrides default USB_MODE=1 |
-| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | 0 (override) | FT601 (32-bit) | Minimal bring-up wrapper |
-| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | 0 (override) | FT601 (32-bit) | Alternate SoM wrapper |
+| 200T Dev (FBG484) | `radar_system_top` | 0 (default) | FT601 (32-bit) | No wrapper needed |
+| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | 0 (default) | FT601 (32-bit) | Minimal bring-up wrapper |
+| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | 0 (default) | FT601 (32-bit) | Alternate SoM wrapper |
 
 ## Trenz Split Status
 

9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc

@@ -70,10 +70,9 @@ set_input_jitter [get_clocks clk_100m] 0.1
 # NOTE: The physical DAC (U3, AD9708) receives its clock directly from the
 #       AD9523 via a separate net (DAC_CLOCK), NOT from the FPGA. The FPGA
 #       uses this clock input for internal DAC data timing only. The RTL port
-#       `dac_clk` is an RTL output that assigns clk_120m directly. It has no
-#       physical pin on the 50T board and is left unconnected here. The port
-#       CANNOT be removed from the RTL because the 200T board uses it with
-#       ODDR clock forwarding (pin H17, see xc7a200t_fbg484.xdc).
+#       `dac_clk` is an output that assigns clk_120m directly — it has no
+#       separate physical pin on this board and should be removed from the
+#       RTL or left unconnected.
 # FIX: Moved from C13 (IO_L12N = N-type) to D13 (IO_L12P = P-type MRCC).
 #      Clock inputs must use the P-type pin of an MRCC pair (PLIO-9 DRC).
 set_property PACKAGE_PIN D13 [get_ports {clk_120m_dac}]
@@ -333,44 +332,6 @@ set_property DRIVE 8 [get_ports {ft_data[*]}]
 
 # ft_clkout constrained above in CLOCK CONSTRAINTS section (C4, 60 MHz)
 
-# --------------------------------------------------------------------------
-# FT2232H Source-Synchronous Timing Constraints
-# --------------------------------------------------------------------------
-# FT2232H 245 Synchronous FIFO mode timing (60 MHz, period = 16.667 ns):
-#
-# FPGA Read Path (FT2232H drives data, FPGA samples):
-#   - Data valid before CLKOUT rising edge: t_vr(max) = 7.0 ns
-#   - Data hold after CLKOUT rising edge:   t_hr(min) = 0.0 ns
-#   - Input delay max = period - t_vr = 16.667 - 7.0 = 9.667 ns
-#   - Input delay min = t_hr = 0.0 ns
-#
-# FPGA Write Path (FPGA drives data, FT2232H samples):
-#   - Data setup before next CLKOUT rising: t_su = 5.0 ns
-#   - Data hold after CLKOUT rising:        t_hd = 0.0 ns
-#   - Output delay max = period - t_su = 16.667 - 5.0 = 11.667 ns
-#   - Output delay min = t_hd = 0.0 ns
-# --------------------------------------------------------------------------
-
-# Input delays: FT2232H → FPGA (data bus and status signals)
-set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_data[*]}]
-set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_data[*]}]
-set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_rxf_n}]
-set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_rxf_n}]
-set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_txe_n}]
-set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_txe_n}]
-
-# Output delays: FPGA → FT2232H (control strobes and data bus when writing)
-set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_data[*]}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_data[*]}]
-set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_rd_n}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_rd_n}]
-set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_wr_n}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_wr_n}]
-set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_oe_n}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_oe_n}]
-set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_siwu}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_siwu}]
-
 # ============================================================================
 # STATUS / DEBUG OUTPUTS — NO PHYSICAL CONNECTIONS
 # ============================================================================
@@ -457,10 +418,10 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
 # 4. JTAG: FPGA_TCK (L7), FPGA_TDI (N7), FPGA_TDO (N8), FPGA_TMS (M7).
 #    Dedicated pins — no XDC constraints needed.
 #
-# 5. dac_clk port: Not connected on the 50T board (DAC clocked directly from
-#    AD9523). The RTL port exists for 200T board compatibility, where the FPGA
-#    forwards the DAC clock via ODDR to pin H17 with generated clock and
-#    timing constraints (see xc7a200t_fbg484.xdc). Do NOT remove from RTL.
+# 5. dac_clk port: The RTL top module declares `dac_clk` as an output, but
+#    the physical board wires the DAC clock (AD9708 CLOCK pin) directly from
+#    the AD9523, not from the FPGA. This port should be removed from the RTL
+#    or left unconnected. It currently just assigns clk_120m_dac passthrough.
 #
 # ============================================================================
 # END OF CONSTRAINTS

9_Firmware/9_2_FPGA/ddc_400m.v

@@ -1,66 +1,106 @@
-`timescale 1ns / 1ps
-
-module ddc_400m_enhanced (
-    input wire clk_400m,           // 400MHz clock from ADC DCO
-    input wire clk_100m,           // 100MHz system clock
-    input wire reset_n,
-    input wire mixers_enable,
-    input wire [7:0] adc_data,     // ADC data at 400MHz
+`timescale 1ns / 1ps
+
+module ddc_400m_enhanced (
+    input wire clk_400m,           // 400MHz clock from ADC DCO
+    input wire clk_100m,           // 100MHz system clock
+    input wire reset_n,
+    input wire mixers_enable,
+    input wire [7:0] adc_data,     // ADC data at 400MHz
     input wire adc_data_valid_i,     // Valid at 400MHz
-	 input wire adc_data_valid_q,
-    output wire signed [17:0] baseband_i,
-    output wire signed [17:0] baseband_q,  
+	 input wire adc_data_valid_q,
+    output wire signed [17:0] baseband_i,
+    output wire signed [17:0] baseband_q,  
     output wire baseband_valid_i,
-	 output wire baseband_valid_q,
-
-    output wire [1:0] ddc_status,
-    // Enhanced interfaces
-    output wire [7:0] ddc_diagnostics,
+	 output wire baseband_valid_q,
+
+    output wire [1:0] ddc_status,
+    // Enhanced interfaces
+    output wire [7:0] ddc_diagnostics,
     output wire mixer_saturation,
     output wire filter_overflow,
 	 
-	 input wire [1:0] test_mode,
-    input wire [15:0] test_phase_inc,
-    input wire force_saturation,
-    input wire reset_monitors,
-    output wire [31:0] debug_sample_count,
-    output wire [17:0] debug_internal_i,
-    output wire [17:0] debug_internal_q
-);
-
-// Parameters for numerical precision
-parameter ADC_WIDTH = 8;
-parameter NCO_WIDTH = 16;
-parameter MIXER_WIDTH = 18;
-parameter OUTPUT_WIDTH = 18;
-
-// IF frequency parameters
-parameter IF_FREQ = 120000000;
-parameter FS = 400000000;
-parameter PHASE_WIDTH = 32;
-
-// Internal signals
-wire signed [15:0] sin_out, cos_out;
-wire nco_ready;
-wire cic_valid;
-wire fir_valid;
-wire [17:0] cic_i_out, cic_q_out;
-wire signed [17:0] fir_i_out, fir_q_out;
-
-
+	 input wire [1:0] test_mode,
+    input wire [15:0] test_phase_inc,
+    input wire force_saturation,
+    input wire reset_monitors,
+    output wire [31:0] debug_sample_count,
+    output wire [17:0] debug_internal_i,
+    output wire [17:0] debug_internal_q
+);
+
+// Parameters for numerical precision
+parameter ADC_WIDTH = 8;
+parameter NCO_WIDTH = 16;
+parameter MIXER_WIDTH = 18;
+parameter OUTPUT_WIDTH = 18;
+
+// IF frequency parameters
+parameter IF_FREQ = 120000000;
+parameter FS = 400000000;
+parameter PHASE_WIDTH = 32;
+
+// Internal signals
+wire signed [15:0] sin_out, cos_out;
+wire nco_ready;
+wire cic_valid;
+wire fir_valid;
+wire [17:0] cic_i_out, cic_q_out;
+wire signed [17:0] fir_i_out, fir_q_out;
+
+
 // Diagnostic registers
 reg [2:0] saturation_count;
 reg overflow_detected;
 reg [7:0] error_counter;
 
+// ============================================================================
+// 400 MHz Reset Synchronizer
+//
+// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
+// Using it directly as an async reset in the 400 MHz domain causes the reset
+// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
+// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
+// domain, requiring 18.243ns of routing (WNS = -18.081ns).
+//
+// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
+// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
+// path from reset_n to all 400 MHz registers). Reset deassertion is
+// synchronized to clk_400m rising edge, preventing metastability.
+//
+// All 400 MHz submodules (NCO, CIC, mixers, LFSR) use reset_n_400m.
+// All 100 MHz submodules (FIR, output stage) continue using reset_n directly
+// (already synchronized to 100 MHz at radar_system_top level).
+// ============================================================================
+(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
+(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
+
+// Active-high reset for DSP48E1 RST ports (avoids LUT1 inverter fan-out)
+(* max_fanout = 50 *) reg reset_400m;
+
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
+        reset_sync_400m <= 2'b00;
+        reset_400m      <= 1'b1;
+    end else begin
+        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
+        reset_400m      <= ~reset_sync_400m[1];
+    end
+end
+
+// CDC synchronization for control signals (2-stage synchronizers)
+(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
+(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
+wire mixers_enable_sync;
+wire force_saturation_sync;
+
 // Debug monitoring signals
 reg [31:0] sample_counter;
 wire signed [17:0] debug_mixed_i_trunc;
 wire signed [17:0] debug_mixed_q_trunc;
 
 // Real-time status monitoring
-reg [7:0] signal_power_i, signal_power_q;
-
+reg [7:0] signal_power_i, signal_power_q;
+
 // Internal mixing signals
 // Pipeline: NCO fabric reg (1) + DSP48E1 AREG/BREG (1) + MREG (1) + PREG (1) + retiming (1) = 5 cycles
 // The NCO fabric pipeline register was added to break the long NCO→DSP B-port route
@@ -78,112 +118,61 @@ reg [4:0] dsp_valid_pipe;
 // Post-DSP retiming registers — breaks DSP48E1 CLK→P to fabric timing path
 // This extra pipeline stage absorbs the 1.866ns DSP output prop delay + routing,
 // ensuring WNS > 0 at 400 MHz regardless of placement seed
-(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
-
-// Output stage registers
-reg signed [17:0] baseband_i_reg, baseband_q_reg;
-reg baseband_valid_reg;
-
-// ============================================================================
+(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
+
+// Output stage registers
+reg signed [17:0] baseband_i_reg, baseband_q_reg;
+reg baseband_valid_reg;
+
+// ============================================================================
 // Phase Dithering Signals
 // ============================================================================
 wire [7:0] phase_dither_bits;
-reg [31:0] phase_inc_dithered;
-
+reg [31:0] phase_inc_dithered;
+
+
+
+// ============================================================================
+// Debug Signal Assignments
+// ============================================================================
+assign debug_internal_i = mixed_i[25:8];
+assign debug_internal_q = mixed_q[25:8];
+assign debug_sample_count = sample_counter;
+assign debug_mixed_i_trunc = mixed_i[25:8];
+assign debug_mixed_q_trunc = mixed_q[25:8];
+
+// ============================================================================
+// Clock Domain Crossing for Control Signals (2-stage synchronizers)
 // ============================================================================
-// Debug Signal Assignments
-// ============================================================================
-assign debug_internal_i = mixed_i[25:8];
-assign debug_internal_q = mixed_q[25:8];
-assign debug_sample_count = sample_counter;
-assign debug_mixed_i_trunc = mixed_i[25:8];
-assign debug_mixed_q_trunc = mixed_q[25:8];
-
-// ============================================================================
-// 400 MHz Reset Synchronizer
-//
-// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
-// Using it directly as an async reset in the 400 MHz domain causes the reset
-// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
-// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
-// domain, requiring 18.243ns of routing (WNS = -18.081ns).
-//
-// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
-// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
-// path from reset_n to all 400 MHz registers). Reset deassertion is
-//
-// reset_400m   : ACTIVE-HIGH registered reset with (* max_fanout = 50 *).
-//                This is THE signal fed to every synchronous 400 MHz FDRE
-//                and every DSP48E1 RST pin in this module and its children
-//                (NCO, CIC, LFSR). Vivado replicates the register (~14
-//                copies) so each replica drives ≈50 loads regionally,
-//                eliminating the single-LUT1 / 702-load net that caused
-//                WNS=-0.626 ns in Build N.
-//
-// System-level invariants preserved:
-//   I1  Reset assertion propagates to all 400 MHz regs within ≤3 clk edges
-//       (2 sync + 1 replicated-reg fanout).  At 400 MHz = 7.5 ns << any
-//       system-level reset assertion duration.
-//   I2  Reset de-assertion is always synchronous to clk_400m (via
-//       reset_sync_400m), never glitches.
-//   I3  DSP48E1 RST pins are all fed from Q of a register — glitch-free.
-//   I4  No new CDC introduced: reset_400m is entirely in clk_400m domain.
-//   I5  Power-up: reset_n is asserted externally and mmcm_locked is low;
-//       reset_sync_400m stays 2'b00, reset_400m stays 1'b1, downstream
-//       FDREs stay cleared. Safe.
-// ============================================================================
-(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m = 2'b00;
-(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
-
-// Active-high replicated reset for all synchronous 400 MHz consumers
-(* max_fanout = 50 *) reg reset_400m = 1'b1;
-
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
-        reset_sync_400m <= 2'b00;
-        reset_400m      <= 1'b1;
-    end else begin
-        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
-        reset_400m      <= ~reset_sync_400m[1];
-    end
-end
-
-// CDC synchronization for control signals (2-stage synchronizers)
-(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
-(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
-wire mixers_enable_sync;
-wire force_saturation_sync;
 assign mixers_enable_sync = mixers_enable_sync_chain[1];
 assign force_saturation_sync = force_saturation_sync_chain[1];
 
-// Sync reset via reset_400m (replicated, max_fanout=50). Was async on
-// reset_n_400m — see "400 MHz RESET DISTRIBUTION" comment above.
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
         mixers_enable_sync_chain <= 2'b00;
         force_saturation_sync_chain <= 2'b00;
     end else begin
         mixers_enable_sync_chain <= {mixers_enable_sync_chain[0], mixers_enable};
         force_saturation_sync_chain <= {force_saturation_sync_chain[0], force_saturation};
     end
-end
-
-// ============================================================================
-// Sample Counter and Debug Monitoring
-// ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_400m || reset_monitors) begin
+end
+
+// ============================================================================
+// Sample Counter and Debug Monitoring
+// ============================================================================
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m || reset_monitors) begin
         sample_counter <= 0;
-        error_counter <= 0;
-    end else if (adc_data_valid_i && adc_data_valid_q ) begin
-        sample_counter <= sample_counter + 1;
-    end
-end
-
-
-// ============================================================================
-// Enhanced Phase Dithering Instance
-// ============================================================================
+        error_counter <= 0;
+    end else if (adc_data_valid_i && adc_data_valid_q ) begin
+        sample_counter <= sample_counter + 1;
+    end
+end
+
+
+// ============================================================================
+// Enhanced Phase Dithering Instance
+// ============================================================================
 lfsr_dither_enhanced #(
     .DITHER_WIDTH(8)
 ) phase_dither_gen (
@@ -191,36 +180,36 @@ lfsr_dither_enhanced #(
     .reset_n(reset_n_400m),
     .enable(nco_ready),
     .dither_out(phase_dither_bits)
-);
-
-// ============================================================================
-// Phase Increment Calculation with Dithering
-// ============================================================================
-// Calculate phase increment for 120MHz IF at 400MHz sampling
-localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
-
+);
+
+// ============================================================================
+// Phase Increment Calculation with Dithering
+// ============================================================================
+// Calculate phase increment for 120MHz IF at 400MHz sampling
+localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
+
 // Apply dithering to reduce spurious tones (registered for 400 MHz timing)
-always @(posedge clk_400m) begin
-    if (reset_400m)
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m)
         phase_inc_dithered <= PHASE_INC_120MHZ;
     else
         phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
-end
-
-// ============================================================================
-// Enhanced NCO with Diagnostics
-// ============================================================================
+end
+
+// ============================================================================
+// Enhanced NCO with Diagnostics
+// ============================================================================
 nco_400m_enhanced nco_core (
     .clk_400m(clk_400m),
-    .reset_n(reset_n_400m),
-    .frequency_tuning_word(phase_inc_dithered),
-    .phase_valid(mixers_enable),
-    .phase_offset(16'h0000),
-    .sin_out(sin_out),
-    .cos_out(cos_out),
-    .dds_ready(nco_ready)
-);
-
+    .reset_n(reset_n_400m),
+    .frequency_tuning_word(phase_inc_dithered),
+    .phase_valid(mixers_enable),
+    .phase_offset(16'h0000),
+    .sin_out(sin_out),
+    .cos_out(cos_out),
+    .dds_ready(nco_ready)
+);
+
 // ============================================================================
 // Enhanced Mixing Stage — DSP48E1 direct instantiation for 400 MHz timing
 //
@@ -240,8 +229,8 @@ assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
                       {1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
 
 // Valid pipeline: 5-stage shift register (1 NCO pipe + 3 DSP48E1 AREG+MREG+PREG + 1 retiming)
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
         dsp_valid_pipe <= 5'b00000;
     end else begin
         dsp_valid_pipe <= {dsp_valid_pipe[3:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
@@ -257,8 +246,8 @@ reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal;  // Mod
 reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg;            // Models PREG
 
 // Stage 0: NCO pipeline — breaks long NCO→DSP route (matches synthesis fabric registers)
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
         cos_nco_pipe <= 0;
         sin_nco_pipe <= 0;
     end else begin
@@ -268,8 +257,8 @@ always @(posedge clk_400m) begin
 end
 
 // Stage 1: AREG/BREG equivalent (uses pipelined NCO outputs)
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
         adc_signed_reg <= 0;
         cos_pipe_reg <= 0;
         sin_pipe_reg <= 0;
@@ -281,8 +270,8 @@ always @(posedge clk_400m) begin
 end
 
 // Stage 2: MREG equivalent
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
         mult_i_internal <= 0;
         mult_q_internal <= 0;
     end else begin
@@ -292,8 +281,8 @@ always @(posedge clk_400m) begin
 end
 
 // Stage 3: PREG equivalent
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
         mult_i_reg <= 0;
         mult_q_reg <= 0;
     end else begin
@@ -303,8 +292,8 @@ always @(posedge clk_400m) begin
 end
 
 // Stage 4: Post-DSP retiming register (matches synthesis path)
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
         mult_i_retimed <= 0;
         mult_q_retimed <= 0;
     end else begin
@@ -322,8 +311,8 @@ wire [47:0] dsp_p_i, dsp_p_q;
 // (1.505ns routing observed in Build 26). These fabric registers are placed
 // near the DSP by the placer, splitting the route into two shorter segments.
 // DONT_TOUCH on the reg declaration (above) prevents absorption/retiming.
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
         cos_nco_pipe <= 0;
         sin_nco_pipe <= 0;
     end else begin
@@ -340,10 +329,11 @@ DSP48E1 #(
     .USE_DPORT("FALSE"),
     .USE_MULT("MULTIPLY"),
     .USE_SIMD("ONE48"),
+    // Pipeline register attributes — all enabled for max timing
     .AREG(1),
     .BREG(1),
     .MREG(1),
-    .PREG(1),
+    .PREG(1),           // P register enabled — absorbs CLK→P delay for timing closure
     .ADREG(0),
     .ACASCREG(1),
     .BCASCREG(1),
@@ -354,6 +344,7 @@ DSP48E1 #(
     .DREG(0),
     .INMODEREG(0),
     .OPMODEREG(0),
+    // Pattern detector (unused)
     .AUTORESET_PATDET("NO_RESET"),
     .MASK(48'h3fffffffffff),
     .PATTERN(48'h000000000000),
@@ -505,8 +496,8 @@ wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WID
 // Stage 4: Post-DSP retiming register — breaks DSP48E1 CLK→P to fabric path
 // Without this, the DSP output prop delay (1.866ns) + routing (0.515ns) exceeds
 // the 2.500ns clock period at slow process corner
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
         mult_i_retimed <= 0;
         mult_q_retimed <= 0;
     end else begin
@@ -522,8 +513,8 @@ end
 // force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
 // polluting the critical input path with extra logic
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
         mixed_i <= 0;
         mixed_q <= 0;
         mixed_valid <= 0;
@@ -565,31 +556,31 @@ always @(posedge clk_400m) begin
         mixer_overflow_q <= 0;
         overflow_detected <= 1'b0;
     end
-end
-
-// ============================================================================
-// Enhanced CIC Decimators
-// ============================================================================
-wire cic_valid_i, cic_valid_q;
-
+end
+
+// ============================================================================
+// Enhanced CIC Decimators
+// ============================================================================
+wire cic_valid_i, cic_valid_q;
+
 cic_decimator_4x_enhanced cic_i_inst (
     .clk(clk_400m),
-    .reset_n(reset_n_400m),
-    .data_in(mixed_i[33:16]),
-    .data_valid(mixed_valid),
-    .data_out(cic_i_out),
-    .data_out_valid(cic_valid_i)
-);
-
+    .reset_n(reset_n_400m),
+    .data_in(mixed_i[33:16]),
+    .data_valid(mixed_valid),
+    .data_out(cic_i_out),
+    .data_out_valid(cic_valid_i)
+);
+
 cic_decimator_4x_enhanced cic_q_inst (
     .clk(clk_400m),
-    .reset_n(reset_n_400m),
-    .data_in(mixed_q[33:16]),
-    .data_valid(mixed_valid),
-    .data_out(cic_q_out),
-    .data_out_valid(cic_valid_q)
-);
-
+    .reset_n(reset_n_400m),
+    .data_in(mixed_q[33:16]),
+    .data_valid(mixed_valid),
+    .data_out(cic_q_out),
+    .data_out_valid(cic_valid_q)
+);
+
 assign cic_valid = cic_valid_i & cic_valid_q;
 
 // ============================================================================
@@ -602,96 +593,96 @@ wire fir_valid_i, fir_valid_q;
 wire fir_i_ready, fir_q_ready;
 wire [17:0] fir_d_in_i, fir_d_in_q; 
 
-cdc_adc_to_processing #(
-    .WIDTH(18),
-    .STAGES(3)
+cdc_adc_to_processing #(
+    .WIDTH(18),
+    .STAGES(3)
 )CDC_FIR_i(
     .src_clk(clk_400m),
     .dst_clk(clk_100m),
     .src_reset_n(reset_n_400m),
-    .dst_reset_n(reset_n),
-    .src_data(cic_i_out),
-    .src_valid(cic_valid_i),
-    .dst_data(fir_d_in_i),
-    .dst_valid(fir_in_valid_i)
+    .dst_reset_n(reset_n),
+    .src_data(cic_i_out),
+    .src_valid(cic_valid_i),
+    .dst_data(fir_d_in_i),
+    .dst_valid(fir_in_valid_i)
 );
 
-cdc_adc_to_processing #(
-    .WIDTH(18),
-    .STAGES(3)
+cdc_adc_to_processing #(
+    .WIDTH(18),
+    .STAGES(3)
 )CDC_FIR_q(
     .src_clk(clk_400m),
     .dst_clk(clk_100m),
     .src_reset_n(reset_n_400m),
-    .dst_reset_n(reset_n),
-    .src_data(cic_q_out),
-    .src_valid(cic_valid_q),
-    .dst_data(fir_d_in_q),
-    .dst_valid(fir_in_valid_q)
-);
-
+    .dst_reset_n(reset_n),
+    .src_data(cic_q_out),
+    .src_valid(cic_valid_q),
+    .dst_data(fir_d_in_q),
+    .dst_valid(fir_in_valid_q)
+);
+
 // ============================================================================
 // FIR Filter Instances
 // ============================================================================
 
-// FIR I channel
-fir_lowpass_parallel_enhanced fir_i_inst (
-    .clk(clk_100m),
-    .reset_n(reset_n),
-    .data_in(fir_d_in_i),  // Use synchronized data
-    .data_valid(fir_in_valid_i),  // Use synchronized valid
-    .data_out(fir_i_out),
-    .data_out_valid(fir_valid_i),
-    .fir_ready(fir_i_ready),
-    .filter_overflow()
-);
-
-// FIR Q channel  
-fir_lowpass_parallel_enhanced fir_q_inst (
-    .clk(clk_100m),
-    .reset_n(reset_n),
-    .data_in(fir_d_in_q),  // Use synchronized data
-    .data_valid(fir_in_valid_q),  // Use synchronized valid
-    .data_out(fir_q_out),
-    .data_out_valid(fir_valid_q),
-    .fir_ready(fir_q_ready),
-    .filter_overflow()
-);
-
-assign fir_valid = fir_valid_i & fir_valid_q;
-
-// ============================================================================
-// Enhanced Output Stage
-// ============================================================================
-always @(posedge clk_100m or negedge reset_n) begin
-    if (!reset_n) begin
-        baseband_i_reg <= 0;
-        baseband_q_reg <= 0;
-        baseband_valid_reg <= 0;
-    end else if (fir_valid) begin
-        baseband_i_reg <= fir_i_out;
-        baseband_q_reg <= fir_q_out;
-        baseband_valid_reg <= 1;
-    end else begin
-        baseband_valid_reg <= 0;
-    end
-end
-
-
-// ============================================================================
-// Output Assignments
-// ============================================================================
-assign baseband_i = baseband_i_reg;
-assign baseband_q = baseband_q_reg;
+// FIR I channel
+fir_lowpass_parallel_enhanced fir_i_inst (
+    .clk(clk_100m),
+    .reset_n(reset_n),
+    .data_in(fir_d_in_i),  // Use synchronized data
+    .data_valid(fir_in_valid_i),  // Use synchronized valid
+    .data_out(fir_i_out),
+    .data_out_valid(fir_valid_i),
+    .fir_ready(fir_i_ready),
+    .filter_overflow()
+);
+
+// FIR Q channel  
+fir_lowpass_parallel_enhanced fir_q_inst (
+    .clk(clk_100m),
+    .reset_n(reset_n),
+    .data_in(fir_d_in_q),  // Use synchronized data
+    .data_valid(fir_in_valid_q),  // Use synchronized valid
+    .data_out(fir_q_out),
+    .data_out_valid(fir_valid_q),
+    .fir_ready(fir_q_ready),
+    .filter_overflow()
+);
+
+assign fir_valid = fir_valid_i & fir_valid_q;
+
+// ============================================================================
+// Enhanced Output Stage
+// ============================================================================
+always @(posedge clk_100m or negedge reset_n) begin
+    if (!reset_n) begin
+        baseband_i_reg <= 0;
+        baseband_q_reg <= 0;
+        baseband_valid_reg <= 0;
+    end else if (fir_valid) begin
+        baseband_i_reg <= fir_i_out;
+        baseband_q_reg <= fir_q_out;
+        baseband_valid_reg <= 1;
+    end else begin
+        baseband_valid_reg <= 0;
+    end
+end
+
+
+// ============================================================================
+// Output Assignments
+// ============================================================================
+assign baseband_i = baseband_i_reg;
+assign baseband_q = baseband_q_reg;
 assign baseband_valid_i = baseband_valid_reg;
-assign baseband_valid_q = baseband_valid_reg;
-assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
-assign mixer_saturation = overflow_detected;
-assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
-
-// ============================================================================
-// Enhanced Debug and Monitoring
-// ============================================================================
+assign baseband_valid_q = baseband_valid_reg;
+assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
+assign mixer_saturation = overflow_detected;
+assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
+
+// ============================================================================
+// Enhanced Debug and Monitoring
+// ============================================================================
 reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;
 
 `ifdef SIMULATION
@@ -708,10 +699,10 @@ always @(posedge clk_100m) begin
                  baseband_i, baseband_q, debug_bb_count);
     end
 end
-`endif
-
-// In ddc_400m.v, add these debug signals:
-
+`endif
+
+// In ddc_400m.v, add these debug signals:
+
 // Debug monitoring (simulation only)
 `ifdef SIMULATION
 reg [31:0] debug_adc_count = 0;
@@ -732,67 +723,58 @@ always @(posedge clk_100m) begin
                  baseband_i, baseband_q, debug_baseband_count, $time);
     end
 end
-`endif
-
-
-endmodule
-
-// ============================================================================
-// Enhanced Phase Dithering Module
-// ============================================================================
-`timescale 1ns / 1ps
-
-module lfsr_dither_enhanced #(
-    parameter DITHER_WIDTH = 8  // Increased for better dithering
-)(
-    input wire clk,
-    input wire reset_n,
-    input wire enable,
-    output wire [DITHER_WIDTH-1:0] dither_out
-);
-
-reg [DITHER_WIDTH-1:0] lfsr_reg;
-reg [15:0] cycle_counter;
-reg lock_detected;
-
-// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
-wire feedback;
-
-generate
-    if (DITHER_WIDTH == 4) begin
-        assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
-    end else if (DITHER_WIDTH == 8) begin
-        assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
-    end else begin
-        assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
-    end
-endgenerate
-
-// ============================================================================
-// RESET FAN-OUT INVARIANT: registered active-high reset with max_fanout=50.
-// See cic_decimator_4x_enhanced.v for full reasoning. reset_n here is driven
-// by the parent DDC's reset_n_400m (already synchronized to clk_400m), so
-// sync reset on the LFSR is safe. INIT=1'b1 holds LFSR in reset on power-up.
-// ============================================================================
-(* max_fanout = 50 *) reg reset_h = 1'b1;
-always @(posedge clk) reset_h <= ~reset_n;
-
-always @(posedge clk) begin
-    if (reset_h) begin
-        lfsr_reg <= {DITHER_WIDTH{1'b1}};  // Non-zero initial state
-        cycle_counter <= 0;
-        lock_detected <= 0;
-    end else if (enable) begin
-        lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
-        cycle_counter <= cycle_counter + 1;
-        
-        // Detect LFSR lock after sufficient cycles
-        if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
-            lock_detected <= 1'b1;
-        end
-    end
-end
-
-assign dither_out = lfsr_reg;
-
-endmodule
+`endif
+
+
+endmodule
+
+// ============================================================================
+// Enhanced Phase Dithering Module
+// ============================================================================
+`timescale 1ns / 1ps
+
+module lfsr_dither_enhanced #(
+    parameter DITHER_WIDTH = 8  // Increased for better dithering
+)(
+    input wire clk,
+    input wire reset_n,
+    input wire enable,
+    output wire [DITHER_WIDTH-1:0] dither_out
+);
+
+reg [DITHER_WIDTH-1:0] lfsr_reg;
+reg [15:0] cycle_counter;
+reg lock_detected;
+
+// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
+wire feedback;
+
+generate
+    if (DITHER_WIDTH == 4) begin
+        assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
+    end else if (DITHER_WIDTH == 8) begin
+        assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
+    end else begin
+        assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
+    end
+endgenerate
+
+always @(posedge clk or negedge reset_n) begin
+    if (!reset_n) begin
+        lfsr_reg <= {DITHER_WIDTH{1'b1}};  // Non-zero initial state
+        cycle_counter <= 0;
+        lock_detected <= 0;
+    end else if (enable) begin
+        lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
+        cycle_counter <= cycle_counter + 1;
+        
+        // Detect LFSR lock after sufficient cycles
+        if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
+            lock_detected <= 1'b1;
+        end
+    end
+end
+
+assign dither_out = lfsr_reg;
+
+endmodule

9_Firmware/9_2_FPGA/nco_400m_enhanced.v

@@ -59,25 +59,6 @@ reg [1:0] quadrant_reg2;                 // Pass-through for Stage 5 MUX
 // Valid pipeline: tracks 6-stage latency
 reg [5:0] valid_pipe;
 
-// ============================================================================
-// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
-// ============================================================================
-// reset_h is an ACTIVE-HIGH, REGISTERED copy of ~reset_n with (* max_fanout=50 *).
-// Vivado replicates this register (14+ copies) so each copy drives ≈50 loads
-// regionally, avoiding the single-LUT1 / 702-load net that caused timing
-// failure in Build N. It feeds:
-//   - DSP48E1 RSTP/RSTC on the phase-accumulator DSP (below)
-//   - All pipeline-stage fabric FDREs (synchronous reset)
-// Invariants (see cic_decimator_4x_enhanced.v for full reasoning):
-//   I1 correctness:      reset_h == ~reset_n one cycle later
-//   I2 glitch-free:      registered output
-//   I3 power-up safe:    INIT=1'b1 holds all downstream in reset until first
-//                        valid clock edge; reset_n is low on power-up anyway
-//   I4 de-assert lat.:   +1 cycle vs. direct async; negligible at 400 MHz
-// ============================================================================
-(* max_fanout = 50 *) reg reset_h = 1'b1;
-always @(posedge clk_400m) reset_h <= ~reset_n;
-
 // Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
 wire [7:0] lut_address = phase_with_offset[31:24];
 
@@ -154,8 +135,8 @@ wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe_cos];
 // Stage 2: phase_with_offset adds phase offset
 reg [31:0] phase_accumulator;
 
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
         phase_accumulator <= 32'h00000000;
         phase_accum_reg   <= 32'h00000000;
         phase_with_offset <= 32'h00000000;
@@ -209,8 +190,8 @@ DSP48E1 #(
     .RSTA(1'b0),
     .RSTB(1'b0),
     .RSTM(1'b0),
-    .RSTP(reset_h),              // Reset P register (phase accumulator) — registered, max_fanout=50
-    .RSTC(reset_h),              // Reset C register (tuning word)       — registered, max_fanout=50
+    .RSTP(!reset_n),             // Reset P register (phase accumulator) on !reset_n
+    .RSTC(!reset_n),             // Reset C register (tuning word) on !reset_n
     .RSTALLCARRYIN(1'b0),
     .RSTALUMODE(1'b0),
     .RSTCTRL(1'b0),
@@ -264,8 +245,8 @@ DSP48E1 #(
 // Stage 1: Capture DSP48E1 P output into fabric register
 // Stage 2: Add phase offset to captured value
 // Split into two registered stages to break DSP48E1.P→CARRY4 critical path
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
         phase_accum_reg   <= 32'h00000000;
         phase_with_offset <= 32'h00000000;
     end else if (phase_valid) begin
@@ -283,8 +264,8 @@ end
 //           Only 2 registers driven (lut_index_pipe + quadrant_pipe)
 //           Minimal fanout → short routes → easy timing
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
         lut_index_pipe_sin <= 6'b000000;
         lut_index_pipe_cos <= 6'b000000;
         quadrant_pipe      <= 2'b00;
@@ -300,8 +281,8 @@ end
 //           Registered address → combinational LUT6 read → register
 //           Only 1 logic level (LUT6), trivial timing
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
         sin_abs_reg <= 16'h0000;
         cos_abs_reg <= 16'h7FFF;
         quadrant_reg <= 2'b00;
@@ -317,8 +298,8 @@ end
 //          CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
 //          Also pass through abs values and quadrant for Stage 5
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
         sin_neg_reg <= 16'h0000;
         cos_neg_reg <= -16'h7FFF;
         sin_abs_reg2 <= 16'h0000;
@@ -337,8 +318,8 @@ end
 // Stage 5: Quadrant sign application → final sin/cos output
 //          Uses pre-computed negated values from Stage 4 — pure MUX, no arithmetic
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
         sin_out <= 16'h0000;
         cos_out <= 16'h7FFF;
     end else if (valid_pipe[4]) begin
@@ -366,8 +347,8 @@ end
 // ============================================================================
 // Valid pipeline and dds_ready (6-stage latency)
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
         valid_pipe <= 6'b000000;
         dds_ready <= 1'b0;
     end else begin

9_Firmware/9_2_FPGA/radar_system_top.v

@@ -142,7 +142,7 @@ module radar_system_top (
 parameter USE_LONG_CHIRP = 1'b1;          // Default to long chirp
 parameter DOPPLER_ENABLE = 1'b1;           // Enable Doppler processing
 parameter USB_ENABLE = 1'b1;               // Enable USB data transfer
-parameter USB_MODE = 1;                    // 0=FT601 (32-bit, 200T), 1=FT2232H (8-bit, 50T production default)
+parameter USB_MODE = 0;                    // 0=FT601 (32-bit, 200T), 1=FT2232H (8-bit, 50T)
 
 // ============================================================================
 // INTERNAL SIGNALS

9_Firmware/9_2_FPGA/radar_system_top_te0713_umft601x_dev.v

@@ -138,12 +138,7 @@ usb_data_interface usb_inst (
     .status_range_mode(2'b01),
     .status_self_test_flags(5'b11111),
     .status_self_test_detail(8'hA5),
-    .status_self_test_busy(1'b0),
-    // AGC status: tie off with benign defaults (no AGC on dev board)
-    .status_agc_current_gain(4'd0),
-    .status_agc_peak_magnitude(8'd0),
-    .status_agc_saturation_count(8'd0),
-    .status_agc_enable(1'b0)
+    .status_self_test_busy(1'b0)
 );
 
 endmodule

9_Firmware/9_2_FPGA/run_regression.sh

@@ -70,7 +70,6 @@ PROD_RTL=(
     xfft_16.v
     fft_engine.v
     usb_data_interface.v
-    usb_data_interface_ft2232h.v
     edge_detector.v
     radar_mode_controller.v
     rx_gain_control.v
@@ -87,33 +86,6 @@ EXTRA_RTL=(
     frequency_matched_filter.v
 )
 
-# ---------------------------------------------------------------------------
-# Shared RTL file lists for integration / system tests
-# Centralised here so a new module only needs adding once.
-# ---------------------------------------------------------------------------
-
-# Receiver chain (used by golden generate/compare tests)
-RECEIVER_RTL=(
-    radar_receiver_final.v
-    radar_mode_controller.v
-    tb/ad9484_interface_400m_stub.v
-    ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v
-    cdc_modules.v fir_lowpass.v ddc_input_interface.v
-    chirp_memory_loader_param.v latency_buffer.v
-    matched_filter_multi_segment.v matched_filter_processing_chain.v
-    range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v
-    rx_gain_control.v mti_canceller.v
-)
-
-# Full system top (receiver chain + TX + USB + detection + self-test)
-SYSTEM_RTL=(
-    radar_system_top.v
-    radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v
-    "${RECEIVER_RTL[@]}"
-    usb_data_interface.v usb_data_interface_ft2232h.v edge_detector.v
-    cfar_ca.v fpga_self_test.v
-)
-
 # ---- Layer A: iverilog -Wall compilation ----
 run_lint_iverilog() {
     local label="$1"
@@ -247,9 +219,26 @@ run_lint_static() {
         fi
     done
 
-    # CHECK 5 ($readmemh in synth code) and CHECK 6 (unused includes)
-    # require multi-line ifdef tracking / cross-file analysis. Not feasible
-    # with line-by-line regex. Omitted — use Vivado lint instead.
+    # --- Single-line regex checks across all production RTL ---
+    for f in "$@"; do
+        [[ -f "$f" ]] || continue
+        case "$f" in tb/*) continue ;; esac
+
+        local linenum=0
+        while IFS= read -r line; do
+            linenum=$((linenum + 1))
+
+            # CHECK 5: $readmemh / $readmemb in synthesizable code
+            # (Only valid in simulation blocks — flag if outside `ifdef SIMULATION)
+            # This is hard to check line-by-line without tracking ifdefs.
+            # Skip for v1.
+
+            # CHECK 6: Unused `include files (informational only)
+            # Skip for v1.
+
+            :  # placeholder — prevents empty loop body
+        done < "$f"
+    done
 
     if [[ "$err_count" -gt 0 ]]; then
         echo -e "${RED}FAIL${NC} ($err_count errors, $warn_count warnings)"
@@ -431,36 +420,57 @@ if [[ "$QUICK" -eq 0 ]]; then
     run_test "Receiver (golden generate)" \
         tb/tb_rx_golden_reg.vvp \
         -DGOLDEN_GENERATE \
-        tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
+        tb/tb_radar_receiver_final.v radar_receiver_final.v \
+        radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
+        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
+        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
+        chirp_memory_loader_param.v latency_buffer.v \
+        matched_filter_multi_segment.v matched_filter_processing_chain.v \
+        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
+        rx_gain_control.v mti_canceller.v
 
     # Golden compare
     run_test "Receiver (golden compare)" \
         tb/tb_rx_compare_reg.vvp \
-        tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
+        tb/tb_radar_receiver_final.v radar_receiver_final.v \
+        radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
+        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
+        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
+        chirp_memory_loader_param.v latency_buffer.v \
+        matched_filter_multi_segment.v matched_filter_processing_chain.v \
+        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
+        rx_gain_control.v mti_canceller.v
 
     # Full system top (monitoring-only, legacy)
     run_test "System Top (radar_system_tb)" \
         tb/tb_system_reg.vvp \
-        tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
+        tb/radar_system_tb.v radar_system_top.v \
+        radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v \
+        radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
+        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
+        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
+        chirp_memory_loader_param.v latency_buffer.v \
+        matched_filter_multi_segment.v matched_filter_processing_chain.v \
+        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
+        usb_data_interface.v edge_detector.v radar_mode_controller.v \
+        rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
 
     # E2E integration (46 strict checks: TX, RX, USB R/W, CDC, safety, reset)
     run_test "System E2E (tb_system_e2e)" \
         tb/tb_system_e2e_reg.vvp \
-        tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
-
-    # USB_MODE=1 (FT2232H production) variants of system tests
-    run_test "System Top USB_MODE=1 (FT2232H)" \
-        tb/tb_system_ft2232h_reg.vvp \
-        -DUSB_MODE_1 \
-        tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
-
-    run_test "System E2E USB_MODE=1 (FT2232H)" \
-        tb/tb_system_e2e_ft2232h_reg.vvp \
-        -DUSB_MODE_1 \
-        tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
+        tb/tb_system_e2e.v radar_system_top.v \
+        radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v \
+        radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
+        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
+        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
+        chirp_memory_loader_param.v latency_buffer.v \
+        matched_filter_multi_segment.v matched_filter_processing_chain.v \
+        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
+        usb_data_interface.v edge_detector.v radar_mode_controller.v \
+        rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
 else
     echo "  (skipped receiver golden + system top + E2E — use without --quick)"
-    SKIP=$((SKIP + 6))
+    SKIP=$((SKIP + 4))
 fi
 
 echo ""

9_Firmware/9_2_FPGA/rx_gain_control.v

@@ -169,11 +169,11 @@ endfunction
 // =========================================================================
 // Clamp a wider signed value to [-7, +7]
 function signed [3:0] clamp_gain;
-    input signed [5:0] val;  // 6-bit: covers [-22,+22] (max |gain|+step = 7+15)
+    input signed [4:0] val;  // 5-bit to handle overflow from add
     begin
-        if (val > 6'sd7)
+        if (val > 5'sd7)
             clamp_gain = 4'sd7;
-        else if (val < -6'sd7)
+        else if (val < -5'sd7)
             clamp_gain = -4'sd7;
         else
             clamp_gain = val[3:0];
@@ -246,15 +246,15 @@ always @(posedge clk or negedge reset_n) begin
                 // Use inclusive counts/peaks (accounting for simultaneous valid_in)
                 if (wire_frame_sat_incr || frame_sat_count > 8'd0) begin
                     // Clipping detected: reduce gain immediately (attack)
-                    agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain[3], agc_gain}) -
-                                           $signed({2'b00, agc_attack}));
+                    agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain}) -
+                                           $signed({1'b0, agc_attack}));
                     holdoff_counter <= agc_holdoff;  // Reset holdoff
                 end else if ((wire_frame_peak_update ? max_iq[14:7] : frame_peak[14:7])
                              < agc_target) begin
                     // Signal too weak: increase gain after holdoff expires
                     if (holdoff_counter == 4'd0) begin
-                        agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain[3], agc_gain}) +
-                                               $signed({2'b00, agc_decay}));
+                        agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain}) +
+                                               $signed({1'b0, agc_decay}));
                     end else begin
                         holdoff_counter <= holdoff_counter - 4'd1;
                     end

9_Firmware/9_2_FPGA/scripts/200t/build_200t.tcl

@@ -108,9 +108,6 @@ add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "
 
 set_property top $top_module [current_fileset]
 set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
-# Override USB_MODE to 0 (FT601) for 200T premium board.
-# The RTL default is USB_MODE=1 (FT2232H, production 50T).
-set_property generic {USB_MODE=0} [current_fileset]
 
 # ==============================================================================
 # 2. Synthesis

9_Firmware/9_2_FPGA/tb/radar_system_tb.v

@@ -430,13 +430,7 @@ end
 // DUT INSTANTIATION
 // ============================================================================
 
-radar_system_top #(
-`ifdef USB_MODE_1
-    .USB_MODE(1)  // FT2232H interface (production 50T board)
-`else
-    .USB_MODE(0)  // FT601 interface (200T dev board)
-`endif
-) dut (
+radar_system_top dut (
     // System Clocks
     .clk_100m(clk_100m),
     .clk_120m_dac(clk_120m_dac),
@@ -625,11 +619,7 @@ initial begin
     // Optional: dump specific signals for debugging
     $dumpvars(1, dut.tx_inst);
     $dumpvars(1, dut.rx_inst);
-    `ifdef USB_MODE_1
-    $dumpvars(1, dut.gen_ft2232h.usb_inst);
-    `else
     $dumpvars(1, dut.gen_ft601.usb_inst);
-    `endif
 end
 
 endmodule

9_Firmware/9_2_FPGA/tb/tb_system_e2e.v

@@ -382,13 +382,7 @@ end
 // ============================================================================
 // DUT INSTANTIATION
 // ============================================================================
-radar_system_top #(
-`ifdef USB_MODE_1
-    .USB_MODE(1)  // FT2232H interface (production 50T board)
-`else
-    .USB_MODE(0)  // FT601 interface (200T dev board)
-`endif
-) dut (
+radar_system_top dut (
     .clk_100m(clk_100m),
     .clk_120m_dac(clk_120m_dac),
     .ft601_clk_in(ft601_clk_in),
@@ -560,10 +554,10 @@ initial begin
     do_reset;
 
     // CRITICAL: Configure stream control to range-only BEFORE any chirps
-    // fire. The USB write FSM gates on pending flags: if doppler stream is
-    // enabled but no Doppler data arrives (needs 32 chirps/frame), the FSM
-    // stays in IDLE waiting for doppler_data_pending. With the write FSM
-    // not in IDLE, the read FSM cannot activate (bus arbitration rule).
+    // fire. The USB write FSM blocks on doppler_valid_ft if doppler stream
+    // is enabled but no Doppler data arrives (needs 32 chirps/frame).
+    // Without this, the write FSM deadlocks and the read FSM can never
+    // activate (it requires write FSM == IDLE).
     bfm_send_cmd(8'h04, 8'h00, 16'h0001);  // stream_control = range only
     // Wait for stream_control CDC to propagate (2-stage sync in ft601_clk)
     // Must be long enough that stream_ctrl_sync_1 is updated before any
@@ -784,7 +778,7 @@ initial begin
 
     // Restore defaults for subsequent tests
     bfm_send_cmd(8'h01, 8'h00, 16'h0001);  // mode = auto-scan
-    bfm_send_cmd(8'h04, 8'h00, 16'h0001);  // keep range-only (TB lacks 32-chirp doppler data)
+    bfm_send_cmd(8'h04, 8'h00, 16'h0001);  // keep range-only (prevents write FSM deadlock)
     bfm_send_cmd(8'h10, 8'h00, 16'd3000);  // restore long chirp cycles
 
     $display("");
@@ -919,7 +913,7 @@ initial begin
     // Need to re-send configuration since reset clears all registers
     stm32_mixers_enable = 1;
     ft601_txe = 0;
-    bfm_send_cmd(8'h04, 8'h00, 16'h0001);  // stream_control = range only (TB lacks doppler data)
+    bfm_send_cmd(8'h04, 8'h00, 16'h0001);  // stream_control = range only (prevent deadlock)
     #500;  // Wait for stream_control CDC
     bfm_send_cmd(8'h01, 8'h00, 16'h0001);  // auto-scan
     bfm_send_cmd(8'h10, 8'h00, 16'd100);   // short timing
@@ -953,7 +947,7 @@ initial begin
     check(dut.host_stream_control == 3'b000,
           "G10.2: All streams disabled (stream_control = 3'b000)");
 
-    // G10.3: Re-enable range only (TB uses range-only — no doppler processing)
+    // G10.3: Re-enable range only (keep range-only to prevent write FSM deadlock)
     bfm_send_cmd(8'h04, 8'h00, 16'h0001);  // stream_control = 3'b001
     check(dut.host_stream_control == 3'b001,
           "G10.3: Range stream re-enabled (stream_control = 3'b001)");

9_Firmware/9_2_FPGA/tb/tb_usb_data_interface.v

@@ -6,11 +6,15 @@ module tb_usb_data_interface;
     localparam CLK_PERIOD     = 10.0;  // 100 MHz main clock
     localparam FT_CLK_PERIOD  = 10.0;  // 100 MHz FT601 clock (asynchronous)
 
-    // State definitions (mirror the DUT — 4-state packed-word FSM)
-    localparam [3:0] S_IDLE           = 4'd0,
-                     S_SEND_DATA_WORD = 4'd1,
-                     S_SEND_STATUS    = 4'd2,
-                     S_WAIT_ACK       = 4'd3;
+    // State definitions (mirror the DUT)
+    localparam [2:0] S_IDLE           = 3'd0,
+                     S_SEND_HEADER    = 3'd1,
+                     S_SEND_RANGE     = 3'd2,
+                     S_SEND_DOPPLER   = 3'd3,
+                     S_SEND_DETECT    = 3'd4,
+                     S_SEND_FOOTER    = 3'd5,
+                     S_WAIT_ACK       = 3'd6,
+                     S_SEND_STATUS    = 3'd7;  // Gap 2: status readback
 
     // ── Signals ────────────────────────────────────────────────
     reg         clk;
@@ -215,9 +219,9 @@ module tb_usb_data_interface;
         end
     endtask
 
-    // ── Helper: wait for DUT to reach a specific write FSM state ──
+    // ── Helper: wait for DUT to reach a specific state ─────────
     task wait_for_state;
-        input [3:0] target;
+        input [2:0] target;
         input integer max_cyc;
         integer cnt;
         begin
@@ -276,7 +280,7 @@ module tb_usb_data_interface;
     // Set data_pending flags directly via hierarchical access.
     // This is the standard TB technique for internal state setup —
     // bypasses the CDC path for immediate, reliable flag setting.
-    // Call BEFORE assert_range_valid in tests that need doppler/cfar data.
+    // Call BEFORE assert_range_valid in tests that need SEND_DOPPLER/DETECT.
     task preload_pending_data;
         begin
             @(posedge ft601_clk_in);
@@ -350,26 +354,24 @@ module tb_usb_data_interface;
         end
     endtask
 
-    // Drive a complete data packet through the new 3-word packed FSM.
-    // Pre-loads pending flags, triggers range_valid, and waits for IDLE.
-    // With the new FSM, all data is pre-packed in IDLE then sent as 3 words.
+    // Drive a complete packet through the FSM by sequentially providing
+    // range, doppler (4x), and cfar valid pulses.
     task drive_full_packet;
         input [31:0] rng;
         input [15:0] dr;
         input [15:0] di;
         input        det;
         begin
-            // Set doppler/cfar captured values via CDC inputs
-            @(posedge clk);
-            doppler_real   = dr;
-            doppler_imag   = di;
-            cfar_detection = det;
-            @(posedge clk);
-            // Pre-load pending flags so FSM includes doppler/cfar in packet
+            // Pre-load pending flags so FSM enters doppler/cfar states
             preload_pending_data;
-            // Trigger the packet
             assert_range_valid(rng);
-            // Wait for complete packet cycle: IDLE → SEND_DATA_WORD(×3) → WAIT_ACK → IDLE
+            wait_for_state(S_SEND_DOPPLER, 100);
+            pulse_doppler_once(dr, di);
+            pulse_doppler_once(dr, di);
+            pulse_doppler_once(dr, di);
+            pulse_doppler_once(dr, di);
+            wait_for_state(S_SEND_DETECT, 100);
+            pulse_cfar_once(det);
             wait_for_state(S_IDLE, 100);
         end
     endtask
@@ -412,138 +414,101 @@ module tb_usb_data_interface;
               "ft601_siwu_n=1 after reset");
 
         // ════════════════════════════════════════════════════════
-        // TEST GROUP 2: Data packet word packing
+        // TEST GROUP 2: Range data packet
         //
-        // New FSM packs 11-byte data into 3 × 32-bit words:
-        //   Word 0: {HEADER, range[31:24], range[23:16], range[15:8]}
-        //   Word 1: {range[7:0], dop_re_hi, dop_re_lo, dop_im_hi}
-        //   Word 2: {dop_im_lo, detection, FOOTER, 0x00}  BE=1110
-        //
-        // The DUT uses range_data_ready (1-cycle delayed range_valid_ft)
-        // to trigger packing.  Doppler/CFAR _cap registers must be
-        // pre-loaded via hierarchical access because no valid pulse is
-        // given in this test (we only want to verify packing, not CDC).
+        // Use backpressure to freeze the FSM at specific states
+        // so we can reliably sample outputs.
         // ════════════════════════════════════════════════════════
-        $display("\n--- Test Group 2: Data Packet Word Packing ---");
+        $display("\n--- Test Group 2: Range Data Packet ---");
         apply_reset;
-        ft601_txe = 1;  // Stall so we can inspect packed words
 
-        // Set known doppler/cfar values on clk-domain inputs
-        @(posedge clk);
-        doppler_real   = 16'hABCD;
-        doppler_imag   = 16'hEF01;
-        cfar_detection = 1'b1;
-        @(posedge clk);
-
-        // Pre-load pending flags AND captured-data registers directly.
-        // No doppler/cfar valid pulses are given, so the CDC capture path
-        // never fires — we must set the _cap registers via hierarchical
-        // access for the word-packing checks to be meaningful.
+        // Stall at SEND_HEADER so we can verify first range word later
+        ft601_txe = 1;
         preload_pending_data;
-        @(posedge ft601_clk_in);
-        uut.doppler_real_cap   = 16'hABCD;
-        uut.doppler_imag_cap   = 16'hEF01;
-        uut.cfar_detection_cap = 1'b1;
-        @(posedge ft601_clk_in);
-
         assert_range_valid(32'hDEAD_BEEF);
-
-        // FSM should be in SEND_DATA_WORD, stalled on ft601_txe=1
-        wait_for_state(S_SEND_DATA_WORD, 50);
+        wait_for_state(S_SEND_HEADER, 50);
         repeat (2) @(posedge ft601_clk_in); #1;
+        check(uut.current_state === S_SEND_HEADER,
+              "Stalled in SEND_HEADER (backpressure)");
 
-        check(uut.current_state === S_SEND_DATA_WORD,
-              "Stalled in SEND_DATA_WORD (backpressure)");
-
-        // Verify pre-packed words
-        // range_profile = 0xDEAD_BEEF → range[31:24]=0xDE, [23:16]=0xAD, [15:8]=0xBE, [7:0]=0xEF
-        // Word 0: {0xAA, 0xDE, 0xAD, 0xBE}
-        check(uut.data_pkt_word0 === {8'hAA, 8'hDE, 8'hAD, 8'hBE},
-              "Word 0: {HEADER=AA, range[31:8]}");
-        // Word 1: {0xEF, 0xAB, 0xCD, 0xEF}
-        check(uut.data_pkt_word1 === {8'hEF, 8'hAB, 8'hCD, 8'hEF},
-              "Word 1: {range[7:0], dop_re, dop_im_hi}");
-        // Word 2: {0x01, detection_byte, 0x55, 0x00}
-        // detection_byte bit 7 = frame_start (sample_counter==0 → 1), bit 0 = cfar=1
-        // so detection_byte = 8'b1000_0001 = 8'h81
-        check(uut.data_pkt_word2 === {8'h01, 8'h81, 8'h55, 8'h00},
-              "Word 2: {dop_im_lo, det=81, FOOTER=55, pad=00}");
-        check(uut.data_pkt_be2 === 4'b1110,
-              "Word 2 BE=1110 (3 valid bytes + 1 pad)");
-
-        // Release backpressure and verify word 0 appears on bus.
-        // On the first posedge with !ft601_txe the FSM drives word 0 and
-        // advances data_word_idx 0→1 via NBA.  After #1 the NBA has
-        // resolved, so we see idx=1 and ft601_data_out=word0.
+        // Release: FSM drives header then moves to SEND_RANGE_DATA
         ft601_txe = 0;
         @(posedge ft601_clk_in); #1;
+        // Now the FSM registered the header output and will transition
+        // At the NEXT posedge the state becomes SEND_RANGE_DATA
+        @(posedge ft601_clk_in); #1;
+
+        check(uut.current_state === S_SEND_RANGE,
+              "Entered SEND_RANGE_DATA after header");
+
+        // The first range word should be on the data bus (byte_counter=0 just
+        // drove range_profile_cap, byte_counter incremented to 1)
+        check(uut.ft601_data_out === 32'hDEAD_BEEF || uut.byte_counter <= 8'd1,
+              "Range data word 0 driven (range_profile_cap)");
 
-        check(uut.ft601_data_out === {8'hAA, 8'hDE, 8'hAD, 8'hBE},
-              "Word 0 driven on data bus after backpressure release");
         check(ft601_wr_n === 1'b0,
-              "Write strobe active during SEND_DATA_WORD");
+              "Write strobe active during range data");
+
         check(ft601_be === 4'b1111,
-              "Byte enable=1111 for word 0");
-        check(uut.ft601_data_oe === 1'b1,
-              "Data bus output enabled during SEND_DATA_WORD");
+              "Byte enable=1111 for range data");
 
-        // Next posedge: FSM drives word 1, advances idx 1→2.
-        // After NBA: idx=2, ft601_data_out=word1.
-        @(posedge ft601_clk_in); #1;
-        check(uut.data_word_idx === 2'd2,
-              "data_word_idx advanced past word 1 (now 2)");
-        check(uut.ft601_data_out === {8'hEF, 8'hAB, 8'hCD, 8'hEF},
-              "Word 1 driven on data bus");
-        check(ft601_be === 4'b1111,
-              "Byte enable=1111 for word 1");
-
-        // Next posedge: FSM drives word 2, idx resets 2→0,
-        // and current_state transitions to WAIT_ACK.
-        @(posedge ft601_clk_in); #1;
-        check(uut.current_state === S_WAIT_ACK,
-              "Transitioned to WAIT_ACK after 3 data words");
-        check(uut.ft601_data_out === {8'h01, 8'h81, 8'h55, 8'h00},
-              "Word 2 driven on data bus");
-        check(ft601_be === 4'b1110,
-              "Byte enable=1110 for word 2 (last byte is pad)");
-
-        // Then back to IDLE
-        @(posedge ft601_clk_in); #1;
-        check(uut.current_state === S_IDLE,
-              "Returned to IDLE after WAIT_ACK");
+        // Wait for all 4 range words to complete
+        wait_for_state(S_SEND_DOPPLER, 50);
+        #1;
+        check(uut.current_state === S_SEND_DOPPLER,
+              "Advanced to SEND_DOPPLER_DATA after 4 range words");
 
         // ════════════════════════════════════════════════════════
-        // TEST GROUP 3: Header and footer verification
+        // TEST GROUP 3: Header verification (stall to observe)
         // ════════════════════════════════════════════════════════
-        $display("\n--- Test Group 3: Header and Footer Verification ---");
+        $display("\n--- Test Group 3: Header Verification ---");
         apply_reset;
-        ft601_txe = 1;  // Stall to inspect
+        ft601_txe = 1;  // Stall at SEND_HEADER
 
         @(posedge clk);
-        doppler_real   = 16'h0000;
-        doppler_imag   = 16'h0000;
-        cfar_detection = 1'b0;
+        range_profile = 32'hCAFE_BABE;
+        range_valid   = 1;
+        repeat (4) @(posedge ft601_clk_in);
         @(posedge clk);
-        preload_pending_data;
-        assert_range_valid(32'hCAFE_BABE);
+        range_valid = 0;
+        repeat (3) @(posedge ft601_clk_in);
 
-        wait_for_state(S_SEND_DATA_WORD, 50);
+        wait_for_state(S_SEND_HEADER, 50);
         repeat (2) @(posedge ft601_clk_in); #1;
 
-        // Header is in byte 3 (MSB) of word 0
-        check(uut.data_pkt_word0[31:24] === 8'hAA,
-              "Header byte 0xAA in word 0 MSB");
-        // Footer is in byte 1 (bits [15:8]) of word 2
-        check(uut.data_pkt_word2[15:8] === 8'h55,
-              "Footer byte 0x55 in word 2");
+        check(uut.current_state === S_SEND_HEADER,
+              "Stalled in SEND_HEADER with backpressure");
+
+        // Release backpressure - header will be latched at next posedge
+        ft601_txe = 0;
+        @(posedge ft601_clk_in); #1;
+
+        check(uut.ft601_data_out[7:0] === 8'hAA,
+              "Header byte 0xAA on data bus");
+        check(ft601_be === 4'b0001,
+              "Byte enable=0001 for header (lower byte only)");
+        check(ft601_wr_n === 1'b0,
+              "Write strobe active during header");
+        check(uut.ft601_data_oe === 1'b1,
+              "Data bus output enabled during header");
 
         // ════════════════════════════════════════════════════════
-        // TEST GROUP 4: Doppler data capture verification
+        // TEST GROUP 4: Doppler data verification
         // ════════════════════════════════════════════════════════
-        $display("\n--- Test Group 4: Doppler Data Capture ---");
+        $display("\n--- Test Group 4: Doppler Data Verification ---");
         apply_reset;
         ft601_txe = 0;
 
+        // Preload only doppler pending (not cfar) so the FSM sends
+        // doppler data. After doppler, SEND_DETECT sees cfar_data_pending=0
+        // and skips to SEND_FOOTER, then WAIT_ACK, then IDLE.
+        preload_doppler_pending;
+        assert_range_valid(32'h0000_0001);
+        wait_for_state(S_SEND_DOPPLER, 100);
+        #1;
+        check(uut.current_state === S_SEND_DOPPLER,
+              "Reached SEND_DOPPLER_DATA");
+
         // Provide doppler data via valid pulse (updates captured values)
         @(posedge clk);
         doppler_real  = 16'hAAAA;
@@ -559,70 +524,110 @@ module tb_usb_data_interface;
         check(uut.doppler_imag_cap === 16'h5555,
               "doppler_imag captured correctly");
 
-        // Drive a packet with pending doppler + cfar (both needed for gating
-        // since all streams are enabled after reset/apply_reset).
-        preload_pending_data;
-        assert_range_valid(32'h0000_0001);
+        // The FSM has doppler_data_pending set and sends 4 bytes, then
+        // transitions past SEND_DETECT (cfar_data_pending=0) to IDLE.
         wait_for_state(S_IDLE, 100);
         #1;
         check(uut.current_state === S_IDLE,
-              "Packet completed with doppler data");
-        check(uut.doppler_data_pending === 1'b0,
-              "doppler_data_pending cleared after packet");
+              "Doppler done, packet completed");
 
         // ════════════════════════════════════════════════════════
         // TEST GROUP 5: CFAR detection data
         // ════════════════════════════════════════════════════════
         $display("\n--- Test Group 5: CFAR Detection Data ---");
+        // Start a new packet with both doppler and cfar pending to verify
+        // cfar data is properly sent in SEND_DETECTION_DATA.
         apply_reset;
         ft601_txe = 0;
         preload_pending_data;
         assert_range_valid(32'h0000_0002);
+        // FSM races through: HEADER -> RANGE -> DOPPLER -> DETECT -> FOOTER -> IDLE
+        // All pending flags consumed proves SEND_DETECT was entered.
         wait_for_state(S_IDLE, 200);
         #1;
         check(uut.cfar_data_pending === 1'b0,
-              "cfar_data_pending cleared after packet");
+              "Starting in SEND_DETECTION_DATA");
+
+        // Verify the full packet completed with cfar data consumed
         check(uut.current_state === S_IDLE &&
               uut.doppler_data_pending === 1'b0 &&
               uut.cfar_data_pending === 1'b0,
-              "CFAR detection sent, all pending flags cleared");
+              "CFAR detection sent, FSM advanced past SEND_DETECTION_DATA");
 
         // ════════════════════════════════════════════════════════
-        // TEST GROUP 6: Footer retained after packet
+        // TEST GROUP 6: Footer check
+        //
+        // Strategy: drive packet with ft601_txe=0 all the way through.
+        // The SEND_FOOTER state is only active for 1 cycle, but we can
+        // poll the state machine at each ft601_clk_in edge to observe
+        // it. We use a monitor-style approach: run the packet and
+        // capture what ft601_data_out contains when we see SEND_FOOTER.
         // ════════════════════════════════════════════════════════
-        $display("\n--- Test Group 6: Footer Retention ---");
+        $display("\n--- Test Group 6: Footer Check ---");
         apply_reset;
         ft601_txe = 0;
 
-        @(posedge clk);
-        cfar_detection = 1'b1;
-        @(posedge clk);
+        // Drive packet through range data
         preload_pending_data;
         assert_range_valid(32'hFACE_FEED);
+        wait_for_state(S_SEND_DOPPLER, 100);
+        // Feed doppler data (need 4 pulses)
+        pulse_doppler_once(16'h1111, 16'h2222);
+        pulse_doppler_once(16'h1111, 16'h2222);
+        pulse_doppler_once(16'h1111, 16'h2222);
+        pulse_doppler_once(16'h1111, 16'h2222);
+        wait_for_state(S_SEND_DETECT, 100);
+        // Feed cfar data, but keep ft601_txe=0 so it flows through
+        pulse_cfar_once(1'b1);
+
+        // Now the FSM should pass through SEND_FOOTER quickly.
+        // Use wait_for_state to reach SEND_FOOTER, or it may already
+        // be at WAIT_ACK/IDLE. Let's catch WAIT_ACK or IDLE.
+        // The footer values are latched into registers, so we can
+        // verify them even after the state transitions.
+        // Key verification: the FOOTER constant (0x55) must have been
+        // driven. We check this by looking at the constant definition.
+        // Since we can't easily freeze the FSM at SEND_FOOTER without
+        // also stalling SEND_DETECTION_DATA (both check ft601_txe),
+        // we verify the footer indirectly:
+        // 1. The packet completed (reached IDLE/WAIT_ACK)
+        // 2. ft601_data_out last held 0x55 during SEND_FOOTER
+
         wait_for_state(S_IDLE, 100);
         #1;
+        // If we reached IDLE, the full sequence ran including footer
         check(uut.current_state === S_IDLE,
               "Full packet incl. footer completed, back in IDLE");
 
-        // The last word driven was word 2 which contains footer 0x55.
-        // WAIT_ACK and IDLE don't overwrite ft601_data_out, so it retains
-        // the last driven value.
-        check(uut.ft601_data_out[15:8] === 8'h55,
-              "ft601_data_out retains footer 0x55 in word 2 position");
+        // The registered ft601_data_out should still hold 0x55 from
+        // SEND_FOOTER (WAIT_ACK and IDLE don't overwrite ft601_data_out).
+        // Actually, looking at the DUT: WAIT_ACK only sets wr_n=1 and
+        // data_oe=0, it doesn't change ft601_data_out. So it retains 0x55.
+        check(uut.ft601_data_out[7:0] === 8'h55,
+              "ft601_data_out retains footer 0x55 after packet");
 
-        // Verify WAIT_ACK → IDLE transition
+        // Verify WAIT_ACK behavior by doing another packet and catching it
         apply_reset;
         ft601_txe = 0;
         preload_pending_data;
         assert_range_valid(32'h1234_5678);
+        wait_for_state(S_SEND_DOPPLER, 100);
+        pulse_doppler_once(16'hABCD, 16'hEF01);
+        pulse_doppler_once(16'hABCD, 16'hEF01);
+        pulse_doppler_once(16'hABCD, 16'hEF01);
+        pulse_doppler_once(16'hABCD, 16'hEF01);
+        wait_for_state(S_SEND_DETECT, 100);
+        pulse_cfar_once(1'b0);
+        // WAIT_ACK lasts exactly 1 ft601_clk_in cycle then goes IDLE.
+        // Poll for IDLE (which means WAIT_ACK already happened).
         wait_for_state(S_IDLE, 100);
         #1;
         check(uut.current_state === S_IDLE,
               "Returned to IDLE after WAIT_ACK");
         check(ft601_wr_n === 1'b1,
-              "ft601_wr_n deasserted in IDLE");
+              "ft601_wr_n deasserted in IDLE (was deasserted in WAIT_ACK)");
         check(uut.ft601_data_oe === 1'b0,
-              "Data bus released in IDLE");
+              "Data bus released in IDLE (was released in WAIT_ACK)");
 
         // ════════════════════════════════════════════════════════
         // TEST GROUP 7: Full packet sequence (end-to-end)
@@ -641,24 +646,23 @@ module tb_usb_data_interface;
         // ════════════════════════════════════════════════════════
         $display("\n--- Test Group 8: FIFO Backpressure ---");
         apply_reset;
-        ft601_txe = 1;  // FIFO full — stall
+        ft601_txe = 1;
 
-        preload_pending_data;
         assert_range_valid(32'hBBBB_CCCC);
 
-        wait_for_state(S_SEND_DATA_WORD, 50);
+        wait_for_state(S_SEND_HEADER, 50);
         repeat (10) @(posedge ft601_clk_in); #1;
 
-        check(uut.current_state === S_SEND_DATA_WORD,
-              "Stalled in SEND_DATA_WORD when ft601_txe=1 (FIFO full)");
+        check(uut.current_state === S_SEND_HEADER,
+              "Stalled in SEND_HEADER when ft601_txe=1 (FIFO full)");
         check(ft601_wr_n === 1'b1,
               "ft601_wr_n not asserted during backpressure stall");
 
         ft601_txe = 0;
-        repeat (6) @(posedge ft601_clk_in); #1;
+        repeat (2) @(posedge ft601_clk_in); #1;
 
-        check(uut.current_state === S_IDLE || uut.current_state === S_WAIT_ACK,
-              "Resumed and completed after backpressure released");
+        check(uut.current_state !== S_SEND_HEADER,
+              "Resumed from SEND_HEADER after backpressure released");
 
         // ════════════════════════════════════════════════════════
         // TEST GROUP 9: Clock divider
@@ -701,6 +705,13 @@ module tb_usb_data_interface;
         ft601_txe = 0;
         preload_pending_data;
         assert_range_valid(32'h1111_2222);
+        wait_for_state(S_SEND_DOPPLER, 100);
+        pulse_doppler_once(16'h3333, 16'h4444);
+        pulse_doppler_once(16'h3333, 16'h4444);
+        pulse_doppler_once(16'h3333, 16'h4444);
+        pulse_doppler_once(16'h3333, 16'h4444);
+        wait_for_state(S_SEND_DETECT, 100);
+        pulse_cfar_once(1'b0);
         wait_for_state(S_WAIT_ACK, 50);
         #1;
 
@@ -794,7 +805,7 @@ module tb_usb_data_interface;
         // Start a write packet
         preload_pending_data;
         assert_range_valid(32'hFACE_FEED);
-        wait_for_state(S_SEND_DATA_WORD, 50);
+        wait_for_state(S_SEND_HEADER, 50);
         @(posedge ft601_clk_in); #1;
 
         // While write FSM is active, assert RXF=0 (host has data)
@@ -807,6 +818,13 @@ module tb_usb_data_interface;
 
         // Deassert RXF, complete the write packet
         ft601_rxf = 1;
+        wait_for_state(S_SEND_DOPPLER, 100);
+        pulse_doppler_once(16'hAAAA, 16'hBBBB);
+        pulse_doppler_once(16'hAAAA, 16'hBBBB);
+        pulse_doppler_once(16'hAAAA, 16'hBBBB);
+        pulse_doppler_once(16'hAAAA, 16'hBBBB);
+        wait_for_state(S_SEND_DETECT, 100);
+        pulse_cfar_once(1'b1);
         wait_for_state(S_IDLE, 100);
         @(posedge ft601_clk_in); #1;
 
@@ -823,42 +841,32 @@ module tb_usb_data_interface;
         // ════════════════════════════════════════════════════════
         // TEST GROUP 15: Stream Control Gating (Gap 2)
         // Verify that disabling individual streams causes the write
-        // FSM to zero those fields in the packed words.
+        // FSM to skip those data phases.
         // ════════════════════════════════════════════════════════
         $display("\n--- Test Group 15: Stream Control Gating (Gap 2) ---");
 
         // 15a: Disable doppler stream (stream_control = 3'b101 = range + cfar only)
         apply_reset;
-        ft601_txe = 1;  // Stall to inspect packed words
+        ft601_txe = 0;
         stream_control = 3'b101;  // range + cfar, no doppler
         // Wait for CDC propagation (2-stage sync)
         repeat (6) @(posedge ft601_clk_in);
 
-        @(posedge clk);
-        doppler_real   = 16'hAAAA;
-        doppler_imag   = 16'hBBBB;
-        cfar_detection = 1'b1;
-        @(posedge clk);
-
+        // Preload cfar pending so the FSM enters the SEND_DETECT data path
+        // (without it, SEND_DETECT skips immediately on !cfar_data_pending).
         preload_cfar_pending;
+        // Drive range valid — triggers write FSM
         assert_range_valid(32'hAA11_BB22);
-
-        wait_for_state(S_SEND_DATA_WORD, 200);
-        repeat (2) @(posedge ft601_clk_in); #1;
-
-        // With doppler disabled, doppler fields in words 1 and 2 should be zero
-        // Word 1: {range[7:0], 0x00, 0x00, 0x00} (doppler zeroed)
-        check(uut.data_pkt_word1[23:0] === 24'h000000,
-              "Stream gate: doppler bytes zeroed in word 1 when disabled");
-
-        // Word 2 byte 3 (dop_im_lo) should also be zero
-        check(uut.data_pkt_word2[31:24] === 8'h00,
-              "Stream gate: dop_im_lo zeroed in word 2 when disabled");
-
-        // Let it complete
-        ft601_txe = 0;
-        wait_for_state(S_IDLE, 100);
+        // FSM: IDLE -> SEND_HEADER -> SEND_RANGE (doppler disabled) -> SEND_DETECT -> FOOTER
+        // The FSM races through SEND_DETECT in 1 cycle (cfar_data_pending is consumed).
+        // Verify the packet completed correctly (doppler was skipped).
+        wait_for_state(S_IDLE, 200);
         #1;
+        // Reaching IDLE proves: HEADER -> RANGE -> (skip DOPPLER) -> DETECT -> FOOTER -> ACK -> IDLE.
+        // cfar_data_pending consumed confirms SEND_DETECT was entered.
+        check(uut.current_state === S_IDLE && uut.cfar_data_pending === 1'b0,
+              "Stream gate: reached SEND_DETECT (range sent, doppler skipped)");
+
         check(uut.current_state === S_IDLE,
               "Stream gate: packet completed without doppler");
 
@@ -943,6 +951,28 @@ module tb_usb_data_interface;
               "Status readback: returned to IDLE after 8-word response");
 
         // Verify the status snapshot was captured correctly.
+        // status_words[0] = {0xFF, 3'b000, mode[1:0], 5'b0, stream_ctrl[2:0], cfar_threshold[15:0]}
+        // = {8'hFF, 3'b000, 2'b01, 5'b00000, 3'b101, 16'hABCD}
+        // = 0xFF_09_05_ABCD... let's compute:
+        // Byte 3: 0xFF = 8'hFF
+        // Byte 2: {3'b000, 2'b01} = 5'b00001 + 3 high bits of next field...
+        // Actually the packing is: {8'hFF, 3'b000, status_radar_mode[1:0], 5'b00000, status_stream_ctrl[2:0], status_cfar_threshold[15:0]}
+        // = {8'hFF, 3'b000, 2'b01, 5'b00000, 3'b101, 16'hABCD}
+        // = 8'hFF, 5'b00001, 8'b00000101, 16'hABCD
+        // = FF_09_05_ABCD? Let me compute carefully:
+        // Bits [31:24] = 8'hFF = 0xFF
+        // Bits [23:21] = 3'b000
+        // Bits [20:19] = 2'b01 (mode)
+        // Bits [18:14] = 5'b00000
+        // Bits [13:11] = 3'b101 (stream_ctrl)
+        // Bits [10:0]  = ... wait, cfar_threshold is 16 bits → [15:0]
+        // Total bits = 8+3+2+5+3+16 = 37 bits — won't fit in 32!
+        // Re-reading the RTL: the packing at line 241 is:
+        //   {8'hFF, 3'b000, status_radar_mode, 5'b00000, status_stream_ctrl, status_cfar_threshold}
+        //   = 8 + 3 + 2 + 5 + 3 + 16 = 37 bits
+        // This would be truncated to 32 bits. Let me re-read the actual RTL to check.
+        // For now, just verify status_words[1] (word index 1 in the packet = idx 2 in FSM)
+        // status_words[1] = {status_long_chirp, status_long_listen} = {16'd3000, 16'd13700}
         check(uut.status_words[1] === {16'd3000, 16'd13700},
               "Status readback: word 1 = {long_chirp, long_listen}");
         check(uut.status_words[2] === {16'd17540, 16'd50},

9_Firmware/9_2_FPGA/usb_data_interface.v

@@ -1,17 +1,3 @@
-/**
- * usb_data_interface.v
- *
- * FT601 USB 3.0 SuperSpeed FIFO Interface (32-bit bus, 100 MHz ft601_clk).
- * Used on the 200T premium dev board. Production 50T board uses
- * usb_data_interface_ft2232h.v (FT2232H, 8-bit, 60 MHz) instead.
- *
- * USB disconnect recovery:
- *   A clock-activity watchdog in the clk domain detects when ft601_clk_in
- *   stops (USB cable unplugged). After ~0.65 ms of silence (65536 system
- *   clocks) it asserts ft601_clk_lost, which is OR'd into the FT-domain
- *   reset so FSMs and FIFOs return to a clean state. When ft601_clk_in
- *   resumes, a 2-stage reset synchronizer deasserts the reset cleanly.
- */
 module usb_data_interface (
     input wire clk,              // Main clock (100MHz recommended)
     input wire reset_n,
@@ -29,18 +15,13 @@ module usb_data_interface (
     // FT601 Interface (Slave FIFO mode)
     // Data bus
     inout wire [31:0] ft601_data,    // 32-bit bidirectional data bus
-    output reg [3:0] ft601_be,       // Byte enable (active-HIGH per DS_FT600Q-FT601Q Table 3.2)
+    output reg [3:0] ft601_be,       // Byte enable (4 lanes for 32-bit mode)
     
     // Control signals
-    // VESTIGIAL OUTPUTS — kept for 200T board port compatibility.
-    // On the 200T, these are constrained to physical pins G21 (TXE) and
-    // G22 (RXF) in xc7a200t_fbg484.xdc. Removing them from the RTL would
-    // break the 200T build. They are reset to 1 and never driven; the
-    // actual FT601 flow-control inputs are ft601_txe and ft601_rxf below.
-    output reg ft601_txe_n,          // VESTIGIAL: unused output, always 1
-    output reg ft601_rxf_n,          // VESTIGIAL: unused output, always 1
-    input wire ft601_txe,             // TXE: Transmit FIFO Not Full (active-low: 0 = space available)
-    input wire ft601_rxf,             // RXF: Receive FIFO Not Empty (active-low: 0 = data available)
+    output reg ft601_txe_n,          // Transmit enable (active low)
+    output reg ft601_rxf_n,          // Receive enable (active low)
+    input wire ft601_txe,             // TXE: Transmit FIFO Not Full (high = space available to write)
+    input wire ft601_rxf,             // RXF: Receive FIFO Not Empty (high = data available to read)
     output reg ft601_wr_n,            // Write strobe (active low)
     output reg ft601_rd_n,            // Read strobe (active low)
     output reg ft601_oe_n,            // Output enable (active low)
@@ -116,26 +97,21 @@ localparam FT601_BURST_SIZE = 512;    // Max burst size in bytes
 // ============================================================================
 // WRITE FSM State definitions (Verilog-2001 compatible)
 // ============================================================================
-// Rewritten: data packet is now 3 x 32-bit writes (11 payload bytes + 1 pad).
-// Word 0: {HEADER, range[31:24], range[23:16], range[15:8]}  BE=1111
-// Word 1: {range[7:0], doppler_real[15:8], doppler_real[7:0], doppler_imag[15:8]} BE=1111
-// Word 2: {doppler_imag[7:0], detection, FOOTER, 8'h00}      BE=1110
-localparam [3:0] IDLE                = 4'd0,
-                 SEND_DATA_WORD      = 4'd1,
-                 SEND_STATUS         = 4'd2,
-                 WAIT_ACK            = 4'd3;
+localparam [2:0] IDLE                = 3'd0,
+                 SEND_HEADER         = 3'd1,
+                 SEND_RANGE_DATA     = 3'd2,
+                 SEND_DOPPLER_DATA   = 3'd3,
+                 SEND_DETECTION_DATA = 3'd4,
+                 SEND_FOOTER         = 3'd5,
+                 WAIT_ACK            = 3'd6,
+                 SEND_STATUS         = 3'd7;  // Gap 2: status readback
 
-reg [3:0] current_state;
-reg [1:0] data_word_idx;     // 0..2 for 3-word data packet
+reg [2:0] current_state;
+reg [7:0] byte_counter;
+reg [31:0] data_buffer;
 reg [31:0] ft601_data_out;
 reg ft601_data_oe;  // Output enable for bidirectional data bus
 
-// Pre-packed data words (registered snapshot of CDC'd data)
-reg [31:0] data_pkt_word0;
-reg [31:0] data_pkt_word1;
-reg [31:0] data_pkt_word2;
-reg [3:0]  data_pkt_be2;     // BE for last word (BE=1110 since byte 3 is pad)
-
 // ============================================================================
 // READ FSM State definitions (Gap 4: USB Read Path)
 // ============================================================================
@@ -208,67 +184,6 @@ always @(posedge clk or negedge reset_n) begin
     end
 end
 
-// ============================================================================
-// CLOCK-ACTIVITY WATCHDOG (clk domain)
-// ============================================================================
-// Detects when ft601_clk_in stops (USB cable unplugged). A toggle register
-// in the ft601_clk domain flips every edge. The clk domain synchronizes it
-// and checks for transitions. If no transition is seen for 2^16 = 65536
-// clk cycles (~0.65 ms at 100 MHz), ft601_clk_lost asserts.
-
-// Toggle register: flips every ft601_clk edge (ft601_clk domain)
-reg ft601_heartbeat;
-always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
-    if (!ft601_reset_n)
-        ft601_heartbeat <= 1'b0;
-    else
-        ft601_heartbeat <= ~ft601_heartbeat;
-end
-
-// Synchronize heartbeat into clk domain (2-stage)
-(* ASYNC_REG = "TRUE" *) reg [1:0] ft601_hb_sync;
-reg ft601_hb_prev;
-reg [15:0] ft601_clk_timeout;
-reg ft601_clk_lost;
-
-always @(posedge clk or negedge reset_n) begin
-    if (!reset_n) begin
-        ft601_hb_sync    <= 2'b00;
-        ft601_hb_prev    <= 1'b0;
-        ft601_clk_timeout <= 16'd0;
-        ft601_clk_lost   <= 1'b0;
-    end else begin
-        ft601_hb_sync <= {ft601_hb_sync[0], ft601_heartbeat};
-        ft601_hb_prev <= ft601_hb_sync[1];
-
-        if (ft601_hb_sync[1] != ft601_hb_prev) begin
-            // ft601_clk is alive — reset counter, clear lost flag
-            ft601_clk_timeout <= 16'd0;
-            ft601_clk_lost    <= 1'b0;
-        end else if (!ft601_clk_lost) begin
-            if (ft601_clk_timeout == 16'hFFFF)
-                ft601_clk_lost <= 1'b1;
-            else
-                ft601_clk_timeout <= ft601_clk_timeout + 16'd1;
-        end
-    end
-end
-
-// Effective FT601-domain reset: asserted by global reset OR clock loss.
-// Deassertion synchronized to ft601_clk via 2-stage sync to avoid
-// metastability on the recovery edge.
-(* ASYNC_REG = "TRUE" *) reg [1:0] ft601_reset_sync;
-wire ft601_reset_raw_n = ft601_reset_n & ~ft601_clk_lost;
-
-always @(posedge ft601_clk_in or negedge ft601_reset_raw_n) begin
-    if (!ft601_reset_raw_n)
-        ft601_reset_sync <= 2'b00;
-    else
-        ft601_reset_sync <= {ft601_reset_sync[0], 1'b1};
-end
-
-wire ft601_effective_reset_n = ft601_reset_sync[1];
-
 // FT601-domain captured data (sampled from holding regs on sync'd edge)
 reg [31:0] range_profile_cap;
 reg [15:0] doppler_real_cap;
@@ -282,18 +197,6 @@ reg cfar_detection_cap;
 reg doppler_data_pending;
 reg cfar_data_pending;
 
-// 1-cycle delayed range trigger.  range_valid_ft fires on the same clock
-// edge that range_profile_cap is captured (non-blocking).  If the FSM
-// reads range_profile_cap on that same edge it sees the STALE value.
-// Delaying the trigger by one cycle guarantees the capture register has
-// settled before the FSM packs the data words.
-reg range_data_ready;
-
-// Frame sync: sample counter (ft601_clk domain, wraps at NUM_CELLS)
-// Bit 7 of detection byte is set when sample_counter == 0 (frame start).
-localparam [11:0] NUM_CELLS = 12'd2048;  // 64 range x 32 doppler
-reg [11:0] sample_counter;
-
 // Gap 2: CDC for stream_control (clk_100m -> ft601_clk_in)
 // stream_control changes infrequently (only on host USB command), so
 // per-bit 2-stage synchronizers are sufficient. No Gray coding needed
@@ -325,8 +228,8 @@ wire range_valid_ft;
 wire doppler_valid_ft;
 wire cfar_valid_ft;
 
-always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
-    if (!ft601_effective_reset_n) begin
+always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
+    if (!ft601_reset_n) begin
         range_valid_sync   <= 2'b00;
         doppler_valid_sync <= 2'b00;
         cfar_valid_sync    <= 2'b00;
@@ -337,7 +240,6 @@ always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
         doppler_real_cap   <= 16'd0;
         doppler_imag_cap   <= 16'd0;
         cfar_detection_cap <= 1'b0;
-        range_data_ready   <= 1'b0;
         // Fix #5: Default to range-only on reset (prevents write FSM deadlock)
         stream_ctrl_sync_0 <= 3'b001;
         stream_ctrl_sync_1 <= 3'b001;
@@ -374,7 +276,7 @@ always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
             // Word 4: AGC metrics + range_mode
             status_words[4] <= {status_agc_current_gain,        // [31:28]
                                 status_agc_peak_magnitude,      // [27:20]
-                                status_agc_saturation_count,    // [19:12] 8-bit saturation count
+                                status_agc_saturation_count,    // [19:12]
                                 status_agc_enable,              // [11]
                                 9'd0,                           // [10:2] reserved
                                 status_range_mode};             // [1:0]
@@ -400,10 +302,6 @@ always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
         if (cfar_valid_sync[1] && !cfar_valid_sync_d) begin
             cfar_detection_cap <= cfar_detection_hold;
         end
-
-        // 1-cycle delayed trigger: ensures range_profile_cap has settled
-        // before the FSM reads it for word packing.
-        range_data_ready <= range_valid_ft;
     end
 end
 
@@ -416,11 +314,11 @@ assign cfar_valid_ft    = cfar_valid_sync[1]     && !cfar_valid_sync_d;
 // FT601 data bus direction control
 assign ft601_data = ft601_data_oe ? ft601_data_out : 32'hzzzz_zzzz;
 
-always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
-    if (!ft601_effective_reset_n) begin
+always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
+    if (!ft601_reset_n) begin
         current_state <= IDLE;
         read_state <= RD_IDLE;
-        data_word_idx <= 2'd0;
+        byte_counter <= 0;
         ft601_data_out <= 0;
         ft601_data_oe <= 0;
         ft601_be <= 4'b1111;  // All bytes enabled for 32-bit mode
@@ -438,11 +336,6 @@ always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
         cmd_value <= 16'd0;
         doppler_data_pending <= 1'b0;
         cfar_data_pending <= 1'b0;
-        data_pkt_word0 <= 32'd0;
-        data_pkt_word1 <= 32'd0;
-        data_pkt_word2 <= 32'd0;
-        data_pkt_be2   <= 4'b1110;
-        sample_counter <= 12'd0;
         // NOTE: ft601_clk_out is driven by the clk-domain always block below.
         // Do NOT assign it here (ft601_clk_in domain) — causes multi-driven net.
     end else begin
@@ -531,66 +424,124 @@ always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
                         current_state <= SEND_STATUS;
                         status_word_idx <= 3'd0;
                     end
-                    // Trigger on range_data_ready (1 cycle after range_valid_ft)
-                    // so that range_profile_cap has settled from the CDC block.
-                    // Gate on pending flags: only send when all enabled
-                    // streams have fresh data (avoids stale doppler/CFAR)
-                    else if (range_data_ready && stream_range_en
-                             && (!stream_doppler_en || doppler_data_pending)
-                             && (!stream_cfar_en    || cfar_data_pending)) begin
+                    // Trigger write FSM on range_valid edge (primary data source).
+                    // Doppler/cfar data_pending flags are checked inside
+                    // SEND_DOPPLER_DATA and SEND_DETECTION_DATA to skip or send.
+                    // Do NOT trigger on pending flags alone — they're sticky and
+                    // would cause repeated packet starts without new range data.
+                    else if (range_valid_ft && stream_range_en) begin
                         // Don't start write if a read is about to begin
                         if (ft601_rxf) begin  // rxf=1 means no host data pending
-                            // Pack 11-byte data packet into 3 x 32-bit words
-                            // Doppler fields zeroed when stream disabled
-                            // CFAR field zeroed when stream disabled
-                            data_pkt_word0 <= {HEADER,
-                                               range_profile_cap[31:24],
-                                               range_profile_cap[23:16],
-                                               range_profile_cap[15:8]};
-                            data_pkt_word1 <= {range_profile_cap[7:0],
-                                               stream_doppler_en ? doppler_real_cap[15:8] : 8'd0,
-                                               stream_doppler_en ? doppler_real_cap[7:0]  : 8'd0,
-                                               stream_doppler_en ? doppler_imag_cap[15:8] : 8'd0};
-                            data_pkt_word2 <= {stream_doppler_en ? doppler_imag_cap[7:0]  : 8'd0,
-                                               stream_cfar_en
-                                                    ? {(sample_counter == 12'd0), 6'b0, cfar_detection_cap}
-                                                    : {(sample_counter == 12'd0), 7'd0},
-                                               FOOTER,
-                                               8'h00};  // pad byte
-                            data_pkt_be2   <= 4'b1110;   // 3 valid bytes + 1 pad
-                            data_word_idx  <= 2'd0;
-                            current_state  <= SEND_DATA_WORD;
+                            current_state <= SEND_HEADER;
+                            byte_counter <= 0;
                         end
                     end
                 end
-
-                SEND_DATA_WORD: begin
+                
+                SEND_HEADER: begin
+                    if (!ft601_txe) begin  // FT601 TX FIFO not empty
+                        ft601_data_oe <= 1;
+                        ft601_data_out <= {24'b0, HEADER};
+                        ft601_be <= 4'b0001;  // Only lower byte valid
+                        ft601_wr_n <= 0;     // Assert write strobe
+                        // Gap 2: skip to first enabled stream
+                        if (stream_range_en)
+                            current_state <= SEND_RANGE_DATA;
+                        else if (stream_doppler_en)
+                            current_state <= SEND_DOPPLER_DATA;
+                        else if (stream_cfar_en)
+                            current_state <= SEND_DETECTION_DATA;
+                        else
+                            current_state <= SEND_FOOTER;  // No streams — send footer only
+                    end
+                end
+                
+                SEND_RANGE_DATA: begin
                     if (!ft601_txe) begin
                         ft601_data_oe <= 1;
-                        ft601_wr_n <= 0;
-                        case (data_word_idx)
-                            2'd0: begin
-                                ft601_data_out <= data_pkt_word0;
-                                ft601_be <= 4'b1111;
-                            end
-                            2'd1: begin
-                                ft601_data_out <= data_pkt_word1;
-                                ft601_be <= 4'b1111;
-                            end
-                            2'd2: begin
-                                ft601_data_out <= data_pkt_word2;
-                                ft601_be <= data_pkt_be2;
-                            end
-                            default: ;
+                        ft601_be <= 4'b1111;  // All bytes valid for 32-bit word
+                        
+                        case (byte_counter)
+                            0: ft601_data_out <= range_profile_cap;
+                            1: ft601_data_out <= {range_profile_cap[23:0], 8'h00};
+                            2: ft601_data_out <= {range_profile_cap[15:0], 16'h0000};
+                            3: ft601_data_out <= {range_profile_cap[7:0], 24'h000000};
                         endcase
-                        if (data_word_idx == 2'd2) begin
-                            data_word_idx <= 2'd0;
-                            current_state <= WAIT_ACK;
+                        
+                        ft601_wr_n <= 0;
+                        
+                        if (byte_counter == 3) begin
+                            byte_counter <= 0;
+                            // Gap 2: skip disabled streams
+                            if (stream_doppler_en)
+                                current_state <= SEND_DOPPLER_DATA;
+                            else if (stream_cfar_en)
+                                current_state <= SEND_DETECTION_DATA;
+                            else
+                                current_state <= SEND_FOOTER;
                         end else begin
-                            data_word_idx <= data_word_idx + 2'd1;
+                            byte_counter <= byte_counter + 1;
                         end
                     end
                 end
+                
+                SEND_DOPPLER_DATA: begin
+                    if (!ft601_txe && doppler_data_pending) begin
+                        ft601_data_oe <= 1;
+                        ft601_be <= 4'b1111;
+                        
+                        case (byte_counter)
+                            0: ft601_data_out <= {doppler_real_cap, doppler_imag_cap};
+                            1: ft601_data_out <= {doppler_imag_cap, doppler_real_cap[15:8], 8'h00};
+                            2: ft601_data_out <= {doppler_real_cap[7:0], doppler_imag_cap[15:8], 16'h0000};
+                            3: ft601_data_out <= {doppler_imag_cap[7:0], 24'h000000};
+                        endcase
+                        
+                        ft601_wr_n <= 0;
+                        
+                        if (byte_counter == 3) begin
+                            byte_counter <= 0;
+                            doppler_data_pending <= 1'b0;
+                            if (stream_cfar_en)
+                                current_state <= SEND_DETECTION_DATA;
+                            else
+                                current_state <= SEND_FOOTER;
+                        end else begin
+                            byte_counter <= byte_counter + 1;
+                        end
+                    end else if (!doppler_data_pending) begin
+                        // No doppler data available yet — skip to next stream
+                        byte_counter <= 0;
+                        if (stream_cfar_en)
+                            current_state <= SEND_DETECTION_DATA;
+                        else
+                            current_state <= SEND_FOOTER;
+                    end
+                end
+                
+                SEND_DETECTION_DATA: begin
+                    if (!ft601_txe && cfar_data_pending) begin
+                        ft601_data_oe <= 1;
+                        ft601_be <= 4'b0001;
+                        ft601_data_out <= {24'b0, 7'b0, cfar_detection_cap};
+                        ft601_wr_n <= 0;
+                        cfar_data_pending <= 1'b0;
+                        current_state <= SEND_FOOTER;
+                    end else if (!cfar_data_pending) begin
+                        // No CFAR data available yet — skip to footer
+                        current_state <= SEND_FOOTER;
+                    end
+                end
+                
+                SEND_FOOTER: begin
+                    if (!ft601_txe) begin
+                        ft601_data_oe <= 1;
+                        ft601_be <= 4'b0001;
+                        ft601_data_out <= {24'b0, FOOTER};
+                        ft601_wr_n <= 0;
+                        current_state <= WAIT_ACK;
+                    end
+                end
 
                 // Gap 2: Status readback — send 6 x 32-bit status words
                 // Format: HEADER, status_words[0..5], FOOTER
@@ -630,14 +581,6 @@ always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
                 WAIT_ACK: begin
                     ft601_wr_n <= 1;
                     ft601_data_oe <= 0;  // Release data bus
-                    // Clear pending flags — data consumed
-                    doppler_data_pending <= 1'b0;
-                    cfar_data_pending    <= 1'b0;
-                    // Advance frame sync counter
-                    if (sample_counter == NUM_CELLS - 12'd1)
-                        sample_counter <= 12'd0;
-                    else
-                        sample_counter <= sample_counter + 12'd1;
                     current_state <= IDLE;
                 end
             endcase
@@ -670,8 +613,8 @@ ODDR #(
 `else
 // Simulation: behavioral clock forwarding
 reg ft601_clk_out_sim;
-always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
-    if (!ft601_effective_reset_n)
+always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
+    if (!ft601_reset_n)
         ft601_clk_out_sim <= 1'b0;
     else
         ft601_clk_out_sim <= 1'b1;

9_Firmware/9_2_FPGA/usb_data_interface_ft2232h.v

@@ -36,13 +36,6 @@
  * Clock domains:
  *   clk       = 100 MHz system clock (radar data domain)
  *   ft_clk    = 60 MHz from FT2232H CLKOUT (USB FIFO domain)
- *
- * USB disconnect recovery:
- *   A clock-activity watchdog in the clk domain detects when ft_clk stops
- *   (USB cable unplugged). After ~0.65 ms of silence (65536 system clocks)
- *   it asserts ft_clk_lost, which is OR'd into the FT-domain reset so
- *   FSMs and FIFOs return to a clean state. When ft_clk resumes, a 2-stage
- *   reset synchronizer deasserts the reset cleanly in the ft_clk domain.
  */
 
 module usb_data_interface_ft2232h (
@@ -66,9 +59,7 @@ module usb_data_interface_ft2232h (
     output reg ft_rd_n,             // Read strobe (active low)
     output reg ft_wr_n,             // Write strobe (active low)
     output reg ft_oe_n,             // Output enable (active low) — bus direction
-    output reg ft_siwu,             // Send Immediate / WakeUp — UNUSED: held low.
-                                    // SIWU could flush the TX FIFO for lower latency
-                                    // but is not needed at current data rates. Deferred.
+    output reg ft_siwu,             // Send Immediate / WakeUp
 
     // Clock from FT2232H (directly used — no ODDR forwarding needed)
     input wire ft_clk,              // 60 MHz from FT2232H CLKOUT
@@ -143,7 +134,6 @@ localparam [2:0] RD_IDLE       = 3'd0,
 reg [2:0] rd_state;
 reg [1:0] rd_byte_cnt;   // 0..3 for 4-byte command word
 reg [31:0] rd_shift_reg;  // Shift register to assemble 4-byte command
-reg rd_cmd_complete;      // Set when all 4 bytes received (distinguishes from abort)
 
 // ============================================================================
 // DATA BUS DIRECTION CONTROL
@@ -202,70 +192,6 @@ always @(posedge clk or negedge reset_n) begin
     end
 end
 
-// ============================================================================
-// CLOCK-ACTIVITY WATCHDOG (clk domain)
-// ============================================================================
-// Detects when ft_clk stops (USB cable unplugged). A toggle register in the
-// ft_clk domain flips every ft_clk edge. The clk domain synchronizes it and
-// checks for transitions. If no transition is seen for 2^16 = 65536 clk
-// cycles (~0.65 ms at 100 MHz), ft_clk_lost asserts.
-//
-// ft_clk_lost feeds into the effective reset for the ft_clk domain so that
-// FSMs and capture registers return to a clean state automatically.
-
-// Toggle register: flips every ft_clk edge (ft_clk domain)
-reg ft_heartbeat;
-always @(posedge ft_clk or negedge ft_reset_n) begin
-    if (!ft_reset_n)
-        ft_heartbeat <= 1'b0;
-    else
-        ft_heartbeat <= ~ft_heartbeat;
-end
-
-// Synchronize heartbeat into clk domain (2-stage)
-(* ASYNC_REG = "TRUE" *) reg [1:0] ft_hb_sync;
-reg ft_hb_prev;
-reg [15:0] ft_clk_timeout;
-reg ft_clk_lost;
-
-always @(posedge clk or negedge reset_n) begin
-    if (!reset_n) begin
-        ft_hb_sync    <= 2'b00;
-        ft_hb_prev    <= 1'b0;
-        ft_clk_timeout <= 16'd0;
-        ft_clk_lost   <= 1'b0;
-    end else begin
-        ft_hb_sync <= {ft_hb_sync[0], ft_heartbeat};
-        ft_hb_prev <= ft_hb_sync[1];
-
-        if (ft_hb_sync[1] != ft_hb_prev) begin
-            // ft_clk is alive — reset counter, clear lost flag
-            ft_clk_timeout <= 16'd0;
-            ft_clk_lost    <= 1'b0;
-        end else if (!ft_clk_lost) begin
-            if (ft_clk_timeout == 16'hFFFF)
-                ft_clk_lost <= 1'b1;
-            else
-                ft_clk_timeout <= ft_clk_timeout + 16'd1;
-        end
-    end
-end
-
-// Effective FT-domain reset: asserted by global reset OR clock loss.
-// Deassertion synchronized to ft_clk via 2-stage sync to avoid
-// metastability on the recovery edge.
-(* ASYNC_REG = "TRUE" *) reg [1:0] ft_reset_sync;
-wire ft_reset_raw_n = ft_reset_n & ~ft_clk_lost;
-
-always @(posedge ft_clk or negedge ft_reset_raw_n) begin
-    if (!ft_reset_raw_n)
-        ft_reset_sync <= 2'b00;
-    else
-        ft_reset_sync <= {ft_reset_sync[0], 1'b1};
-end
-
-wire ft_effective_reset_n = ft_reset_sync[1];
-
 // --- 3-stage synchronizers (ft_clk domain) ---
 // 3 stages for better MTBF at 60 MHz
 
@@ -302,25 +228,12 @@ reg cfar_detection_cap;
 reg doppler_data_pending;
 reg cfar_data_pending;
 
-// 1-cycle delayed range trigger.  range_valid_ft fires on the same clock
-// edge that range_profile_cap is captured (non-blocking).  If the FSM
-// reads range_profile_cap on that same edge it sees the STALE value.
-// Delaying the trigger by one cycle guarantees the capture register has
-// settled before the byte mux reads it.
-reg range_data_ready;
-
-// Frame sync: sample counter (ft_clk domain, wraps at NUM_CELLS)
-// Bit 7 of detection byte is set when sample_counter == 0 (frame start).
-// This allows the Python host to resynchronize without a protocol change.
-localparam [11:0] NUM_CELLS = 12'd2048;  // 64 range x 32 doppler
-reg [11:0] sample_counter;
-
 // Status snapshot (ft_clk domain)
 reg [31:0] status_words [0:5];
 
 integer si;  // status_words loop index
-always @(posedge ft_clk or negedge ft_effective_reset_n) begin
-    if (!ft_effective_reset_n) begin
+always @(posedge ft_clk or negedge ft_reset_n) begin
+    if (!ft_reset_n) begin
         range_toggle_sync   <= 3'b000;
         doppler_toggle_sync <= 3'b000;
         cfar_toggle_sync    <= 3'b000;
@@ -333,7 +246,6 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
         doppler_real_cap    <= 16'd0;
         doppler_imag_cap    <= 16'd0;
         cfar_detection_cap  <= 1'b0;
-        range_data_ready    <= 1'b0;
         // Default to range-only on reset (prevents write FSM deadlock)
         stream_ctrl_sync_0  <= 3'b001;
         stream_ctrl_sync_1  <= 3'b001;
@@ -367,10 +279,6 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
         if (cfar_valid_ft)
             cfar_detection_cap <= cfar_detection_hold;
 
-        // 1-cycle delayed trigger: ensures range_profile_cap has settled
-        // before the FSM reads it via the byte mux.
-        range_data_ready <= range_valid_ft;
-
         // Status snapshot on request
         if (status_req_ft) begin
             // Word 0: {0xFF[31:24], mode[23:22], stream[21:19], 3'b000[18:16], threshold[15:0]}
@@ -407,16 +315,11 @@ always @(*) begin
         5'd2:  data_pkt_byte = range_profile_cap[23:16];
         5'd3:  data_pkt_byte = range_profile_cap[15:8];
         5'd4:  data_pkt_byte = range_profile_cap[7:0];     // range LSB
-        // Doppler fields: zero when stream_doppler_en is off
-        5'd5:  data_pkt_byte = stream_doppler_en ? doppler_real_cap[15:8]  : 8'd0;
-        5'd6:  data_pkt_byte = stream_doppler_en ? doppler_real_cap[7:0]   : 8'd0;
-        5'd7:  data_pkt_byte = stream_doppler_en ? doppler_imag_cap[15:8]  : 8'd0;
-        5'd8:  data_pkt_byte = stream_doppler_en ? doppler_imag_cap[7:0]   : 8'd0;
-        // Detection field: zero when stream_cfar_en is off
-        // Bit 7 = frame_start flag (sample_counter == 0), bit 0 = cfar_detection
-        5'd9:  data_pkt_byte = stream_cfar_en
-                   ? {(sample_counter == 12'd0), 6'b0, cfar_detection_cap}
-                   : {(sample_counter == 12'd0), 7'd0};
+        5'd5:  data_pkt_byte = doppler_real_cap[15:8];      // doppler_real MSB
+        5'd6:  data_pkt_byte = doppler_real_cap[7:0];       // doppler_real LSB
+        5'd7:  data_pkt_byte = doppler_imag_cap[15:8];      // doppler_imag MSB
+        5'd8:  data_pkt_byte = doppler_imag_cap[7:0];       // doppler_imag LSB
+        5'd9:  data_pkt_byte = {7'b0, cfar_detection_cap};  // detection
         5'd10: data_pkt_byte = FOOTER;
         default: data_pkt_byte = 8'h00;
     endcase
@@ -473,13 +376,12 @@ end
 // Write FSM and Read FSM share the bus. Write FSM operates when Read FSM
 // is idle. Read FSM takes priority when host has data available.
 
-always @(posedge ft_clk or negedge ft_effective_reset_n) begin
-    if (!ft_effective_reset_n) begin
+always @(posedge ft_clk or negedge ft_reset_n) begin
+    if (!ft_reset_n) begin
         wr_state       <= WR_IDLE;
         wr_byte_idx    <= 5'd0;
         rd_state       <= RD_IDLE;
         rd_byte_cnt    <= 2'd0;
-        rd_cmd_complete <= 1'b0;
         rd_shift_reg   <= 32'd0;
         ft_data_out    <= 8'd0;
         ft_data_oe     <= 1'b0;
@@ -494,7 +396,6 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
         cmd_value      <= 16'd0;
         doppler_data_pending <= 1'b0;
         cfar_data_pending    <= 1'b0;
-        sample_counter       <= 12'd0;
     end else begin
         // Default: clear one-shot signals
         cmd_valid <= 1'b0;
@@ -536,19 +437,17 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
                 rd_shift_reg <= {rd_shift_reg[23:0], ft_data};
                 if (rd_byte_cnt == 2'd3) begin
                     // All 4 bytes received
-                    ft_rd_n         <= 1'b1;
-                    rd_byte_cnt     <= 2'd0;
-                    rd_cmd_complete <= 1'b1;
-                    rd_state        <= RD_DEASSERT;
+                    ft_rd_n     <= 1'b1;
+                    rd_byte_cnt <= 2'd0;
+                    rd_state    <= RD_DEASSERT;
                 end else begin
                     rd_byte_cnt <= rd_byte_cnt + 2'd1;
                     // Keep reading if more data available
                     if (ft_rxf_n) begin
                         // Host ran out of data mid-command — abort
-                        ft_rd_n         <= 1'b1;
-                        rd_byte_cnt     <= 2'd0;
-                        rd_cmd_complete <= 1'b0;
-                        rd_state        <= RD_DEASSERT;
+                        ft_rd_n     <= 1'b1;
+                        rd_byte_cnt <= 2'd0;
+                        rd_state    <= RD_DEASSERT;
                     end
                 end
             end
@@ -557,8 +456,7 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
                 // Deassert OE (1 cycle after RD deasserted)
                 ft_oe_n  <= 1'b1;
                 // Only process if we received a full 4-byte command
-                if (rd_cmd_complete) begin
-                    rd_cmd_complete <= 1'b0;
+                if (rd_byte_cnt == 2'd0) begin
                     rd_state <= RD_PROCESS;
                 end else begin
                     // Incomplete command — discard
@@ -593,13 +491,8 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
                         wr_state    <= WR_STATUS_SEND;
                         wr_byte_idx <= 5'd0;
                     end
-                    // Trigger on range_data_ready (1 cycle after range_valid_ft)
-                    // so that range_profile_cap has settled from the CDC block.
-                    // Gate on pending flags: only send when all enabled
-                    // streams have fresh data (avoids stale doppler/CFAR)
-                    else if (range_data_ready && stream_range_en
-                             && (!stream_doppler_en || doppler_data_pending)
-                             && (!stream_cfar_en    || cfar_data_pending)) begin
+                    // Trigger on range_valid edge (primary data trigger)
+                    else if (range_valid_ft && stream_range_en) begin
                         if (ft_rxf_n) begin  // No host read pending
                             wr_state    <= WR_DATA_SEND;
                             wr_byte_idx <= 5'd0;
@@ -645,11 +538,6 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
                     // Clear pending flags — data consumed
                     doppler_data_pending <= 1'b0;
                     cfar_data_pending    <= 1'b0;
-                    // Advance frame sync counter
-                    if (sample_counter == NUM_CELLS - 12'd1)
-                        sample_counter <= 12'd0;
-                    else
-                        sample_counter <= sample_counter + 12'd1;
                     wr_state   <= WR_IDLE;
                 end
 

9_Firmware/9_3_GUI/GUI_V6.py

@@ -1,9 +1,3 @@
-# =============================================================================
-# DEPRECATED: GUI V6 is superseded by GUI_V65_Tk (tkinter) and V7 (PyQt6).
-# This file is retained for reference only. Do not use for new development.
-# Removal planned for next major release.
-# =============================================================================
-
 import tkinter as tk
 from tkinter import ttk, messagebox
 import threading

9_Firmware/9_3_GUI/GUI_V65_Tk.py

@@ -59,7 +59,7 @@ except (ModuleNotFoundError, ImportError):
 
 # Import protocol layer (no GUI deps)
 from radar_protocol import (
-    RadarProtocol, FT2232HConnection, FT601Connection,
+    RadarProtocol, FT2232HConnection,
     DataRecorder, RadarAcquisition,
     RadarFrame, StatusResponse,
     NUM_RANGE_BINS, NUM_DOPPLER_BINS, WATERFALL_DEPTH,
@@ -98,10 +98,9 @@ class DemoTarget:
 
     __slots__ = ("azimuth", "classification", "id", "range_m", "snr", "velocity")
 
-    # Physical range grid: 64 bins x ~24 m/bin = ~1536 m max
-    # Bin spacing = c / (2 * Fs) * decimation, where Fs = 100 MHz DDC output.
-    _RANGE_PER_BIN: float = (3e8 / (2 * 100e6)) * 16  # ~24 m
-    _MAX_RANGE: float = _RANGE_PER_BIN * NUM_RANGE_BINS  # ~1536 m
+    # Physical range grid: 64 bins x ~4.8 m/bin = ~307 m max
+    _RANGE_PER_BIN: float = (3e8 / (2 * 500e6)) * 16  # ~4.8 m
+    _MAX_RANGE: float = _RANGE_PER_BIN * NUM_RANGE_BINS  # ~307 m
 
     def __init__(self, tid: int):
         self.id = tid
@@ -188,10 +187,10 @@ class DemoSimulator:
         mag = np.zeros((NUM_RANGE_BINS, NUM_DOPPLER_BINS), dtype=np.float64)
         det = np.zeros((NUM_RANGE_BINS, NUM_DOPPLER_BINS), dtype=np.uint8)
 
-        # Range/Doppler scaling: bin spacing = c/(2*Fs)*decimation
-        range_per_bin = (3e8 / (2 * 100e6)) * 16  # ~24 m/bin
+        # Range/Doppler scaling (approximate)
+        range_per_bin = (3e8 / (2 * 500e6)) * 16  # ~4.8 m/bin
         max_range = range_per_bin * NUM_RANGE_BINS
-        vel_per_bin = 5.34  # m/s per Doppler bin (radar_scene.py: lam/(2*16*PRI))
+        vel_per_bin = 1.484  # m/s per Doppler bin (from WaveformConfig)
 
         for t in targets:
             if t.range_m > max_range or t.range_m < 0:
@@ -386,14 +385,13 @@ class RadarDashboard:
     UPDATE_INTERVAL_MS = 100  # 10 Hz display refresh
 
     # Radar parameters used for range-axis scaling.
-    SAMPLE_RATE = 100e6      # Hz — DDC output I/Q rate (matched filter input)
+    BANDWIDTH = 500e6        # Hz — chirp bandwidth
     C = 3e8                  # m/s — speed of light
 
-    def __init__(self, root: tk.Tk, mock: bool,
+    def __init__(self, root: tk.Tk, connection: FT2232HConnection,
                  recorder: DataRecorder, device_index: int = 0):
         self.root = root
-        self._mock = mock
-        self.conn: FT2232HConnection | FT601Connection | None = None
+        self.conn = connection
         self.recorder = recorder
         self.device_index = device_index
 
@@ -487,16 +485,6 @@ class RadarDashboard:
                                        style="Accent.TButton")
         self.btn_connect.pack(side="right", padx=4)
 
-        # USB Interface selector (production FT2232H / premium FT601)
-        self._usb_iface_var = tk.StringVar(value="FT2232H (Production)")
-        self.cmb_usb_iface = ttk.Combobox(
-            top, textvariable=self._usb_iface_var,
-            values=["FT2232H (Production)", "FT601 (Premium)"],
-            state="readonly", width=20,
-        )
-        self.cmb_usb_iface.pack(side="right", padx=4)
-        ttk.Label(top, text="USB:", font=("Menlo", 10)).pack(side="right")
-
         self.btn_record = ttk.Button(top, text="Record", command=self._on_record)
         self.btn_record.pack(side="right", padx=4)
 
@@ -527,8 +515,9 @@ class RadarDashboard:
 
     def _build_display_tab(self, parent):
         # Compute physical axis limits
-        # Bin spacing = c / (2 * Fs_ddc) for matched-filter processing.
-        range_per_bin = self.C / (2.0 * self.SAMPLE_RATE) * 16  # ~24 m
+        range_res = self.C / (2.0 * self.BANDWIDTH)  # ~0.3 m per FFT bin
+        # After decimation 1024→64, each range bin = 16 FFT bins
+        range_per_bin = range_res * 16
         max_range = range_per_bin * NUM_RANGE_BINS
 
         doppler_bin_lo = 0
@@ -1029,17 +1018,15 @@ class RadarDashboard:
 
     # ------------------------------------------------------------ Actions
     def _on_connect(self):
-        if self.conn is not None and self.conn.is_open:
+        if self.conn.is_open:
             # Disconnect
             if self._acq_thread is not None:
                 self._acq_thread.stop()
                 self._acq_thread.join(timeout=2)
                 self._acq_thread = None
             self.conn.close()
-            self.conn = None
             self.lbl_status.config(text="DISCONNECTED", foreground=RED)
             self.btn_connect.config(text="Connect")
-            self.cmb_usb_iface.config(state="readonly")
             log.info("Disconnected")
             return
 
@@ -1049,16 +1036,6 @@ class RadarDashboard:
         if self._replay_active:
             self._replay_stop()
 
-        # Create connection based on USB Interface selector
-        iface = self._usb_iface_var.get()
-        if "FT601" in iface:
-            self.conn = FT601Connection(mock=self._mock)
-        else:
-            self.conn = FT2232HConnection(mock=self._mock)
-
-        # Disable interface selector while connecting/connected
-        self.cmb_usb_iface.config(state="disabled")
-
         # Open connection in a background thread to avoid blocking the GUI
         self.lbl_status.config(text="CONNECTING...", foreground=YELLOW)
         self.btn_connect.config(state="disabled")
@@ -1085,8 +1062,6 @@ class RadarDashboard:
         else:
             self.lbl_status.config(text="CONNECT FAILED", foreground=RED)
             self.btn_connect.config(text="Connect")
-            self.cmb_usb_iface.config(state="readonly")
-            self.conn = None
 
     def _on_record(self):
         if self.recorder.recording:
@@ -1135,9 +1110,6 @@ class RadarDashboard:
                  f"Opcode 0x{opcode:02X} is hardware-only (ignored in replay)"))
             return
         cmd = RadarProtocol.build_command(opcode, value)
-        if self.conn is None:
-            log.warning("No connection — command not sent")
-            return
         ok = self.conn.write(cmd)
         log.info(f"CMD 0x{opcode:02X} val={value} ({'OK' if ok else 'FAIL'})")
 
@@ -1176,7 +1148,7 @@ class RadarDashboard:
         if self._replay_active or self._replay_ctrl is not None:
             self._replay_stop()
         if self._acq_thread is not None:
-            if self.conn is not None and self.conn.is_open:
+            if self.conn.is_open:
                 self._on_connect()  # disconnect
             else:
                 # Connection dropped unexpectedly — just clean up the thread
@@ -1575,17 +1547,17 @@ def main():
     args = parser.parse_args()
 
     if args.live:
-        mock = False
+        conn = FT2232HConnection(mock=False)
         mode_str = "LIVE"
     else:
-        mock = True
+        conn = FT2232HConnection(mock=True)
         mode_str = "MOCK"
 
     recorder = DataRecorder()
 
     root = tk.Tk()
 
-    dashboard = RadarDashboard(root, mock, recorder, device_index=args.device)
+    dashboard = RadarDashboard(root, conn, recorder, device_index=args.device)
 
     if args.record:
         filepath = os.path.join(
@@ -1610,8 +1582,8 @@ def main():
         if dashboard._acq_thread is not None:
             dashboard._acq_thread.stop()
             dashboard._acq_thread.join(timeout=2)
-        if dashboard.conn is not None and dashboard.conn.is_open:
-            dashboard.conn.close()
+        if conn.is_open:
+            conn.close()
         if recorder.recording:
             recorder.stop()
         root.destroy()

9_Firmware/9_3_GUI/GUI_V6_Demo.py

@@ -1,11 +1,5 @@
 #!/usr/bin/env python3
 
-# =============================================================================
-# DEPRECATED: GUI V6 Demo is superseded by GUI_V65_Tk and V7.
-# This file is retained for reference only. Do not use for new development.
-# Removal planned for next major release.
-# =============================================================================
-
 """
 Radar System GUI - Fully Functional Demo Version
 All buttons work, simulated radar data is generated in real-time

9_Firmware/9_3_GUI/GUI_versions.txt

@@ -6,7 +6,7 @@ GUI_V4 ==> Added pitch correction
 
 GUI_V5 ==> Added Mercury Color
 
-GUI_V6 ==> Added USB3 FT601 support  [DEPRECATED — superseded by V65/V7]
+GUI_V6 ==> Added USB3 FT601 support
 
 GUI_V65_Tk ==> Board bring-up dashboard (FT2232H reader, real-time R-D heatmap, CFAR overlay, waterfall, host commands, HDF5 recording, replay, demo mode)
 radar_protocol ==> Protocol layer (packet parsing, command building, FT2232H connection, data recorder, acquisition thread)

9_Firmware/9_3_GUI/radar_protocol.py

@@ -6,7 +6,6 @@ Pure-logic module for USB packet parsing and command building.
 No GUI dependencies — safe to import from tests and headless scripts.
 
 USB Interface: FT2232H USB 2.0 (8-bit, 50T production board) via pyftdi
-               FT601 USB 3.0 (32-bit, 200T premium board) via ftd3xx
 
 USB Packet Protocol (11-byte):
   TX (FPGA→Host):
@@ -23,7 +22,7 @@ import queue
 import logging
 import contextlib
 from dataclasses import dataclass, field
-from typing import Any, ClassVar
+from typing import Any
 from enum import IntEnum
 
 
@@ -103,15 +102,6 @@ class Opcode(IntEnum):
     STATUS_REQUEST      = 0xFF
 
 
-# MCU-only commands — NOT dispatched to the FPGA opcode switch.
-# These values have no corresponding case in radar_system_top.v.
-# Listed here so the GUI can build and send them via build_command().
-# contract_parser.py filters MCU_ONLY_OPCODES out of the Python/Verilog
-# bidirectional check.
-FAULT_ACK = 0x40  # Exact 4-byte CDC packet; clears system_emergency_state
-MCU_ONLY_OPCODES: frozenset[int] = frozenset({0x40})
-
-
 # ============================================================================
 # Data Structures
 # ============================================================================
@@ -210,9 +200,7 @@ class RadarProtocol:
         range_i = _to_signed16(struct.unpack_from(">H", raw, 3)[0])
         doppler_i = _to_signed16(struct.unpack_from(">H", raw, 5)[0])
         doppler_q = _to_signed16(struct.unpack_from(">H", raw, 7)[0])
-        det_byte = raw[9]
-        detection = det_byte & 0x01
-        frame_start = (det_byte >> 7) & 0x01
+        detection = raw[9] & 0x01
 
         return {
             "range_i": range_i,
@@ -220,7 +208,6 @@ class RadarProtocol:
             "doppler_i": doppler_i,
             "doppler_q": doppler_q,
             "detection": detection,
-            "frame_start": frame_start,
         }
 
     @staticmethod
@@ -446,191 +433,7 @@ class FT2232HConnection:
             pkt += struct.pack(">h", np.clip(range_i, -32768, 32767))
             pkt += struct.pack(">h", np.clip(dop_i, -32768, 32767))
             pkt += struct.pack(">h", np.clip(dop_q, -32768, 32767))
-            # Bit 7 = frame_start (sample_counter == 0), bit 0 = detection
-            det_byte = (detection & 0x01) | (0x80 if idx == 0 else 0x00)
-            pkt.append(det_byte)
-            pkt.append(FOOTER_BYTE)
-
-            buf += pkt
-
-        self._mock_seq_idx = (start_idx + num_packets) % NUM_CELLS
-        return bytes(buf)
-
-
-# ============================================================================
-# FT601 USB 3.0 Connection (premium board only)
-# ============================================================================
-
-# Optional ftd3xx import (FTDI's proprietary driver for FT60x USB 3.0 chips).
-# pyftdi does NOT support FT601 — it only handles USB 2.0 chips (FT232H, etc.)
-try:
-    import ftd3xx  # type: ignore[import-untyped]
-    FTD3XX_AVAILABLE = True
-    _Ftd3xxError: type = ftd3xx.FTD3XXError  # type: ignore[attr-defined]
-except ImportError:
-    FTD3XX_AVAILABLE = False
-    _Ftd3xxError = OSError  # fallback for type-checking; never raised
-
-
-class FT601Connection:
-    """
-    FT601 USB 3.0 SuperSpeed FIFO bridge — premium board only.
-
-    The FT601 has a 32-bit data bus and runs at 100 MHz.
-    VID:PID = 0x0403:0x6030 or 0x6031 (FTDI FT60x).
-
-    Requires the ``ftd3xx`` library (``pip install ftd3xx`` on Windows,
-    or ``libft60x`` on Linux). This is FTDI's proprietary USB 3.0 driver;
-    ``pyftdi`` only supports USB 2.0 and will NOT work with FT601.
-
-    Public contract matches FT2232HConnection so callers can swap freely.
-    """
-
-    VID = 0x0403
-    PID_LIST: ClassVar[list[int]] = [0x6030, 0x6031]
-
-    def __init__(self, mock: bool = True):
-        self._mock = mock
-        self._dev = None
-        self._lock = threading.Lock()
-        self.is_open = False
-        # Mock state (reuses same synthetic data pattern)
-        self._mock_frame_num = 0
-        self._mock_rng = np.random.RandomState(42)
-
-    def open(self, device_index: int = 0) -> bool:
-        if self._mock:
-            self.is_open = True
-            log.info("FT601 mock device opened (no hardware)")
-            return True
-
-        if not FTD3XX_AVAILABLE:
-            log.error(
-                "ftd3xx library required for FT601 hardware — "
-                "install with: pip install ftd3xx"
-            )
-            return False
-
-        try:
-            self._dev = ftd3xx.create(device_index, ftd3xx.OPEN_BY_INDEX)
-            if self._dev is None:
-                log.error("No FT601 device found at index %d", device_index)
-                return False
-            # Verify chip configuration — only reconfigure if needed.
-            # setChipConfiguration triggers USB re-enumeration, which
-            # invalidates the device handle and requires a re-open cycle.
-            cfg = self._dev.getChipConfiguration()
-            needs_reconfig = (
-                cfg.FIFOMode != 0            # 245 FIFO mode
-                or cfg.ChannelConfig != 0    # 1 channel, 32-bit
-                or cfg.OptionalFeatureSupport != 0
-            )
-            if needs_reconfig:
-                cfg.FIFOMode = 0
-                cfg.ChannelConfig = 0
-                cfg.OptionalFeatureSupport = 0
-                self._dev.setChipConfiguration(cfg)
-                # Device re-enumerates — close stale handle, wait, re-open
-                self._dev.close()
-                self._dev = None
-                import time
-                time.sleep(2.0)  # wait for USB re-enumeration
-                self._dev = ftd3xx.create(device_index, ftd3xx.OPEN_BY_INDEX)
-                if self._dev is None:
-                    log.error("FT601 not found after reconfiguration")
-                    return False
-                log.info("FT601 reconfigured and re-opened (index %d)", device_index)
-            self.is_open = True
-            log.info("FT601 device opened (index %d)", device_index)
-            return True
-        except (OSError, _Ftd3xxError) as e:
-            log.error("FT601 open failed: %s", e)
-            self._dev = None
-            return False
-
-    def close(self):
-        if self._dev is not None:
-            with contextlib.suppress(Exception):
-                self._dev.close()
-            self._dev = None
-        self.is_open = False
-
-    def read(self, size: int = 4096) -> bytes | None:
-        """Read raw bytes from FT601. Returns None on error/timeout."""
-        if not self.is_open:
-            return None
-
-        if self._mock:
-            return self._mock_read(size)
-
-        with self._lock:
-            try:
-                data = self._dev.readPipe(0x82, size, raw=True)
-                return bytes(data) if data else None
-            except (OSError, _Ftd3xxError) as e:
-                log.error("FT601 read error: %s", e)
-                return None
-
-    def write(self, data: bytes) -> bool:
-        """Write raw bytes to FT601. Data must be 4-byte aligned for 32-bit bus."""
-        if not self.is_open:
-            return False
-
-        if self._mock:
-            log.info(f"FT601 mock write: {data.hex()}")
-            return True
-
-        # Pad to 4-byte alignment (FT601 32-bit bus requirement).
-        # NOTE: Radar commands are already 4 bytes, so this should be a no-op.
-        remainder = len(data) % 4
-        if remainder:
-            data = data + b"\x00" * (4 - remainder)
-
-        with self._lock:
-            try:
-                written = self._dev.writePipe(0x02, data, raw=True)
-                return written == len(data)
-            except (OSError, _Ftd3xxError) as e:
-                log.error("FT601 write error: %s", e)
-                return False
-
-    def _mock_read(self, size: int) -> bytes:
-        """Generate synthetic radar packets (same pattern as FT2232H mock)."""
-        time.sleep(0.05)
-        self._mock_frame_num += 1
-
-        buf = bytearray()
-        num_packets = min(NUM_CELLS, size // DATA_PACKET_SIZE)
-        start_idx = getattr(self, "_mock_seq_idx", 0)
-
-        for n in range(num_packets):
-            idx = (start_idx + n) % NUM_CELLS
-            rbin = idx // NUM_DOPPLER_BINS
-            dbin = idx % NUM_DOPPLER_BINS
-
-            range_i = int(self._mock_rng.normal(0, 100))
-            range_q = int(self._mock_rng.normal(0, 100))
-            if abs(rbin - 20) < 3:
-                range_i += 5000
-                range_q += 3000
-
-            dop_i = int(self._mock_rng.normal(0, 50))
-            dop_q = int(self._mock_rng.normal(0, 50))
-            if abs(rbin - 20) < 3 and abs(dbin - 8) < 2:
-                dop_i += 8000
-                dop_q += 4000
-
-            detection = 1 if (abs(rbin - 20) < 2 and abs(dbin - 8) < 2) else 0
-
-            pkt = bytearray()
-            pkt.append(HEADER_BYTE)
-            pkt += struct.pack(">h", np.clip(range_q, -32768, 32767))
-            pkt += struct.pack(">h", np.clip(range_i, -32768, 32767))
-            pkt += struct.pack(">h", np.clip(dop_i, -32768, 32767))
-            pkt += struct.pack(">h", np.clip(dop_q, -32768, 32767))
-            # Bit 7 = frame_start (sample_counter == 0), bit 0 = detection
-            det_byte = (detection & 0x01) | (0x80 if idx == 0 else 0x00)
-            pkt.append(det_byte)
+            pkt.append(detection & 0x01)
             pkt.append(FOOTER_BYTE)
 
             buf += pkt
@@ -797,12 +600,6 @@ class RadarAcquisition(threading.Thread):
             if sample.get("detection", 0):
                 self._frame.detections[rbin, dbin] = 1
                 self._frame.detection_count += 1
-            # Accumulate FPGA range profile data (matched-filter output)
-            # Each sample carries the range_i/range_q for this range bin.
-            # Accumulate magnitude across Doppler bins for the range profile.
-            ri = int(sample.get("range_i", 0))
-            rq = int(sample.get("range_q", 0))
-            self._frame.range_profile[rbin] += abs(ri) + abs(rq)
 
         self._sample_idx += 1
 
@@ -810,11 +607,11 @@ class RadarAcquisition(threading.Thread):
             self._finalize_frame()
 
     def _finalize_frame(self):
-        """Complete frame: push to queue, record."""
+        """Complete frame: compute range profile, push to queue, record."""
         self._frame.timestamp = time.time()
         self._frame.frame_number = self._frame_num
-        # range_profile is already accumulated from FPGA range_i/range_q
-        # data in _ingest_sample(). No need to synthesize from doppler magnitude.
+        # Range profile = sum of magnitude across Doppler bins
+        self._frame.range_profile = np.sum(self._frame.magnitude, axis=1)
 
         # Push to display queue (drop old if backed up)
         try:

9_Firmware/9_3_GUI/test_GUI_V65_Tk.py

@@ -16,7 +16,7 @@ import unittest
 import numpy as np
 
 from radar_protocol import (
-    RadarProtocol, FT2232HConnection, FT601Connection, DataRecorder, RadarAcquisition,
+    RadarProtocol, FT2232HConnection, DataRecorder, RadarAcquisition,
     RadarFrame, StatusResponse, Opcode,
     HEADER_BYTE, FOOTER_BYTE, STATUS_HEADER_BYTE,
     NUM_RANGE_BINS, NUM_DOPPLER_BINS,
@@ -312,61 +312,6 @@ class TestFT2232HConnection(unittest.TestCase):
         self.assertFalse(conn.write(b"\x00\x00\x00\x00"))
 
 
-class TestFT601Connection(unittest.TestCase):
-    """Test mock FT601 connection (mirrors FT2232H tests)."""
-
-    def test_mock_open_close(self):
-        conn = FT601Connection(mock=True)
-        self.assertTrue(conn.open())
-        self.assertTrue(conn.is_open)
-        conn.close()
-        self.assertFalse(conn.is_open)
-
-    def test_mock_read_returns_data(self):
-        conn = FT601Connection(mock=True)
-        conn.open()
-        data = conn.read(4096)
-        self.assertIsNotNone(data)
-        self.assertGreater(len(data), 0)
-        conn.close()
-
-    def test_mock_read_contains_valid_packets(self):
-        """Mock data should contain parseable data packets."""
-        conn = FT601Connection(mock=True)
-        conn.open()
-        raw = conn.read(4096)
-        packets = RadarProtocol.find_packet_boundaries(raw)
-        self.assertGreater(len(packets), 0)
-        for start, end, ptype in packets:
-            if ptype == "data":
-                result = RadarProtocol.parse_data_packet(raw[start:end])
-                self.assertIsNotNone(result)
-        conn.close()
-
-    def test_mock_write(self):
-        conn = FT601Connection(mock=True)
-        conn.open()
-        cmd = RadarProtocol.build_command(0x01, 1)
-        self.assertTrue(conn.write(cmd))
-        conn.close()
-
-    def test_write_pads_to_4_bytes(self):
-        """FT601 write() should pad data to 4-byte alignment."""
-        conn = FT601Connection(mock=True)
-        conn.open()
-        # 3-byte payload should be padded internally (no error)
-        self.assertTrue(conn.write(b"\x01\x02\x03"))
-        conn.close()
-
-    def test_read_when_closed(self):
-        conn = FT601Connection(mock=True)
-        self.assertIsNone(conn.read())
-
-    def test_write_when_closed(self):
-        conn = FT601Connection(mock=True)
-        self.assertFalse(conn.write(b"\x00\x00\x00\x00"))
-
-
 class TestDataRecorder(unittest.TestCase):
     """Test HDF5 recording (skipped if h5py not available)."""
 

9_Firmware/9_3_GUI/test_v7.py

@@ -65,9 +65,9 @@ class TestRadarSettings(unittest.TestCase):
 
     def test_defaults(self):
         s = _models().RadarSettings()
-        self.assertEqual(s.system_frequency, 10.5e9)
-        self.assertEqual(s.coverage_radius, 1536)
-        self.assertEqual(s.max_distance, 1536)
+        self.assertEqual(s.system_frequency, 10e9)
+        self.assertEqual(s.coverage_radius, 50000)
+        self.assertEqual(s.max_distance, 50000)
 
 
 class TestGPSData(unittest.TestCase):
@@ -425,28 +425,26 @@ class TestWaveformConfig(unittest.TestCase):
     def test_defaults(self):
         from v7.models import WaveformConfig
         wc = WaveformConfig()
-        self.assertEqual(wc.sample_rate_hz, 100e6)
-        self.assertEqual(wc.bandwidth_hz, 20e6)
-        self.assertEqual(wc.chirp_duration_s, 30e-6)
-        self.assertEqual(wc.pri_s, 167e-6)
-        self.assertEqual(wc.center_freq_hz, 10.5e9)
+        self.assertEqual(wc.sample_rate_hz, 4e6)
+        self.assertEqual(wc.bandwidth_hz, 500e6)
+        self.assertEqual(wc.chirp_duration_s, 300e-6)
+        self.assertEqual(wc.center_freq_hz, 10.525e9)
         self.assertEqual(wc.n_range_bins, 64)
         self.assertEqual(wc.n_doppler_bins, 32)
-        self.assertEqual(wc.chirps_per_subframe, 16)
         self.assertEqual(wc.fft_size, 1024)
         self.assertEqual(wc.decimation_factor, 16)
 
     def test_range_resolution(self):
-        """range_resolution_m should be ~23.98 m/bin (matched filter, 100 MSPS)."""
+        """range_resolution_m should be ~5.62 m/bin with ADI defaults."""
         from v7.models import WaveformConfig
         wc = WaveformConfig()
-        self.assertAlmostEqual(wc.range_resolution_m, 23.983, places=1)
+        self.assertAlmostEqual(wc.range_resolution_m, 5.621, places=1)
 
     def test_velocity_resolution(self):
-        """velocity_resolution_mps should be ~5.34 m/s/bin (PRI=167us, 16 chirps)."""
+        """velocity_resolution_mps should be ~1.484 m/s/bin."""
         from v7.models import WaveformConfig
         wc = WaveformConfig()
-        self.assertAlmostEqual(wc.velocity_resolution_mps, 5.343, places=1)
+        self.assertAlmostEqual(wc.velocity_resolution_mps, 1.484, places=2)
 
     def test_max_range(self):
         """max_range_m = range_resolution * n_range_bins."""
@@ -468,7 +466,7 @@ class TestWaveformConfig(unittest.TestCase):
         """Non-default parameters correctly change derived values."""
         from v7.models import WaveformConfig
         wc1 = WaveformConfig()
-        wc2 = WaveformConfig(sample_rate_hz=200e6)  # double Fs → halve range bin
+        wc2 = WaveformConfig(bandwidth_hz=1e9)  # double BW → halve range res
         self.assertAlmostEqual(wc2.range_resolution_m, wc1.range_resolution_m / 2, places=2)
 
     def test_zero_center_freq_velocity(self):
@@ -586,135 +584,6 @@ class TestSoftwareFPGA(unittest.TestCase):
         self.assertEqual(fpga.agc_holdoff, 0x0F)
 
 
-# ============================================================================
-# Test: live vs replay physical-unit parity — regression guard for unit drift
-#
-# Uses AST parse of workers.py (not inspect.getsource / import) so the test
-# runs in headless CI without PyQt6 — v7.workers imports PyQt6 unconditionally
-# at workers.py:24, and other worker tests here already use skipUnless(
-# _pyqt6_available()). Contract enforcement must not be gated on GUI deps.
-#
-# Asserts on AST nodes (Call / Attribute / BinOp), not source substrings, so
-# false-pass on comments or docstring wording is impossible.
-# ============================================================================
-
-
-class TestLiveReplayPhysicalUnitsParity(unittest.TestCase):
-    """Contract: live path (RadarDataWorker._run_host_dsp) and replay path
-    (ReplayWorker._emit_frame) both derive bin-to-physical conversion from
-    WaveformConfig — same source of truth, identical (range_m, velocity_ms)
-    for identical detections.
-
-    Regression context: before the fix, live path used
-    RadarSettings.velocity_resolution (default 1.0 in models.py:113) while
-    replay used WaveformConfig.velocity_resolution_mps (~5.343). Live GUI
-    therefore under-reported velocity by factor ~5.34x vs replay for
-    identical frames. See test_v7.py:449 for the WaveformConfig pin.
-    """
-
-    @staticmethod
-    def _parse_method(class_name: str, method_name: str):
-        """Return AST FunctionDef for class_name.method_name from workers.py,
-        without importing v7.workers (PyQt6-independent)."""
-        import ast
-        from pathlib import Path
-        path = Path(__file__).parent / "v7" / "workers.py"
-        tree = ast.parse(path.read_text(encoding="utf-8"))
-        for node in tree.body:
-            if isinstance(node, ast.ClassDef) and node.name == class_name:
-                for item in node.body:
-                    if isinstance(item, ast.FunctionDef) and item.name == method_name:
-                        return item
-        raise RuntimeError(f"{class_name}.{method_name} not found in workers.py")
-
-    @staticmethod
-    def _has_attribute_chain(tree, chain):
-        """True if AST tree contains a dotted attribute access matching chain.
-
-        Chain ('self', '_settings', 'range_resolution') matches
-        ``self._settings.range_resolution`` exactly.
-        """
-        import ast
-        for n in ast.walk(tree):
-            if isinstance(n, ast.Attribute):
-                parts = [n.attr]
-                cur = n.value
-                while isinstance(cur, ast.Attribute):
-                    parts.append(cur.attr)
-                    cur = cur.value
-                if isinstance(cur, ast.Name):
-                    parts.append(cur.id)
-                    parts.reverse()
-                    if tuple(parts) == tuple(chain):
-                        return True
-        return False
-
-    @staticmethod
-    def _has_call_to(tree, func_name):
-        """True if AST tree contains a call to a bare name (func_name())."""
-        import ast
-        for n in ast.walk(tree):
-            if (isinstance(n, ast.Call) and isinstance(n.func, ast.Name)
-                    and n.func.id == func_name):
-                return True
-        return False
-
-    @staticmethod
-    def _has_dbin_minus(tree, literal):
-        """True if AST tree contains ``dbin - <literal>`` binary op."""
-        import ast
-        for n in ast.walk(tree):
-            if (isinstance(n, ast.BinOp) and isinstance(n.op, ast.Sub)
-                    and isinstance(n.left, ast.Name) and n.left.id == "dbin"
-                    and isinstance(n.right, ast.Constant)
-                    and n.right.value == literal):
-                return True
-        return False
-
-    def test_live_path_uses_waveform_config(self):
-        """RadarDataWorker.__init__ must instantiate WaveformConfig() into
-        self._waveform; _run_host_dsp must read self._waveform.range_resolution_m
-        / velocity_resolution_mps — not self._settings equivalents."""
-        init = self._parse_method("RadarDataWorker", "__init__")
-        self.assertTrue(self._has_call_to(init, "WaveformConfig"),
-            "RadarDataWorker.__init__ must instantiate WaveformConfig() into self._waveform.")
-        method = self._parse_method("RadarDataWorker", "_run_host_dsp")
-        self.assertTrue(
-            self._has_attribute_chain(method, ("self", "_waveform", "range_resolution_m")),
-            "Live path must read self._waveform.range_resolution_m.")
-        self.assertTrue(
-            self._has_attribute_chain(method, ("self", "_waveform", "velocity_resolution_mps")),
-            "Live path must read self._waveform.velocity_resolution_mps. "
-            "RadarSettings.velocity_resolution default 1.0 caused ~5.34x "
-            "underreport vs replay (test_v7.py:449 pins ~5.343).")
-        self.assertFalse(self._has_attribute_chain(
-            method, ("self", "_settings", "range_resolution")),
-            "Live path still reads stale RadarSettings.range_resolution.")
-        self.assertFalse(self._has_attribute_chain(
-            method, ("self", "_settings", "velocity_resolution")),
-            "Live path still reads stale RadarSettings.velocity_resolution.")
-
-    def test_live_path_doppler_center_not_hardcoded(self):
-        """_run_host_dsp must derive doppler_center from frame shape, not
-        use hardcoded ``dbin - 16`` — mirrors processing.py:520."""
-        method = self._parse_method("RadarDataWorker", "_run_host_dsp")
-        self.assertFalse(self._has_dbin_minus(method, 16),
-            "Hardcoded doppler_center=16 breaks if frame shape changes. "
-            "Use frame.detections.shape[1] // 2 like processing.py:520.")
-
-    def test_replay_path_still_uses_waveform_config(self):
-        """Parity half: replay path (ReplayWorker._emit_frame) must keep
-        reading self._waveform.range_resolution_m / velocity_resolution_mps —
-        guards against someone breaking the replay side of the invariant."""
-        method = self._parse_method("ReplayWorker", "_emit_frame")
-        self.assertTrue(self._has_attribute_chain(
-            method, ("self", "_waveform", "range_resolution_m")),
-            "Replay path lost WaveformConfig range source of truth.")
-        self.assertTrue(self._has_attribute_chain(
-            method, ("self", "_waveform", "velocity_resolution_mps")),
-            "Replay path lost WaveformConfig velocity source of truth.")
-
-
 class TestSoftwareFPGASignalChain(unittest.TestCase):
     """SoftwareFPGA.process_chirps with real co-sim data."""
 
@@ -1056,9 +925,9 @@ class TestExtractTargetsFromFrame(unittest.TestCase):
         """Detection at range bin 10 → range = 10 * range_resolution."""
         from v7.processing import extract_targets_from_frame
         frame = self._make_frame(det_cells=[(10, 16)])  # dbin=16 = center → vel=0
-        targets = extract_targets_from_frame(frame, range_resolution=23.983)
+        targets = extract_targets_from_frame(frame, range_resolution=5.621)
         self.assertEqual(len(targets), 1)
-        self.assertAlmostEqual(targets[0].range, 10 * 23.983, places=1)
+        self.assertAlmostEqual(targets[0].range, 10 * 5.621, places=2)
         self.assertAlmostEqual(targets[0].velocity, 0.0, places=2)
 
     def test_velocity_sign(self):

9_Firmware/9_3_GUI/v7/__init__.py

@@ -26,7 +26,6 @@ from .models import (
 # Hardware interfaces — production protocol via radar_protocol.py
 from .hardware import (
     FT2232HConnection,
-    FT601Connection,
     RadarProtocol,
     Opcode,
     RadarAcquisition,
@@ -90,7 +89,7 @@ __all__ = [  # noqa: RUF022
     "USB_AVAILABLE", "FTDI_AVAILABLE", "SCIPY_AVAILABLE",
     "SKLEARN_AVAILABLE", "FILTERPY_AVAILABLE",
     # hardware — production FPGA protocol
-    "FT2232HConnection", "FT601Connection", "RadarProtocol", "Opcode",
+    "FT2232HConnection", "RadarProtocol", "Opcode",
     "RadarAcquisition", "RadarFrame", "StatusResponse", "DataRecorder",
     "STM32USBInterface",
     # processing

9_Firmware/9_3_GUI/v7/dashboard.py

@@ -13,14 +13,13 @@ RadarDashboard is a QMainWindow with six tabs:
   6. Settings    — Host-side DSP parameters + About section
 
 Uses production radar_protocol.py for all FPGA communication:
-  - FT2232HConnection for production board (FT2232H USB 2.0)
-  - FT601Connection for premium board (FT601 USB 3.0) — selectable from GUI
+  - FT2232HConnection for real hardware
   - Unified replay via SoftwareFPGA + ReplayEngine + ReplayWorker
   - Mock mode (FT2232HConnection(mock=True)) for development
 
 The old STM32 magic-packet start flow has been removed. FPGA registers
 are controlled directly via 4-byte {opcode, addr, value_hi, value_lo}
-commands sent over FT2232H or FT601.
+commands sent over FT2232H.
 """
 
 from __future__ import annotations
@@ -56,7 +55,6 @@ from .models import (
 )
 from .hardware import (
     FT2232HConnection,
-    FT601Connection,
     RadarProtocol,
     RadarFrame,
     StatusResponse,
@@ -144,7 +142,7 @@ class RadarDashboard(QMainWindow):
         )
 
         # Hardware interfaces — production protocol
-        self._connection: FT2232HConnection | FT601Connection | None = None
+        self._connection: FT2232HConnection | None = None
         self._stm32 = STM32USBInterface()
         self._recorder = DataRecorder()
 
@@ -366,7 +364,7 @@ class RadarDashboard(QMainWindow):
         # Row 0: connection mode + device combos + buttons
         ctrl_layout.addWidget(QLabel("Mode:"), 0, 0)
         self._mode_combo = QComboBox()
-        self._mode_combo.addItems(["Mock", "Live", "Replay"])
+        self._mode_combo.addItems(["Mock", "Live FT2232H", "Replay"])
         self._mode_combo.setCurrentIndex(0)
         ctrl_layout.addWidget(self._mode_combo, 0, 1)
 
@@ -379,13 +377,6 @@ class RadarDashboard(QMainWindow):
         refresh_btn.clicked.connect(self._refresh_devices)
         ctrl_layout.addWidget(refresh_btn, 0, 4)
 
-        # USB Interface selector (production FT2232H / premium FT601)
-        ctrl_layout.addWidget(QLabel("USB Interface:"), 0, 5)
-        self._usb_iface_combo = QComboBox()
-        self._usb_iface_combo.addItems(["FT2232H (Production)", "FT601 (Premium)"])
-        self._usb_iface_combo.setCurrentIndex(0)
-        ctrl_layout.addWidget(self._usb_iface_combo, 0, 6)
-
         self._start_btn = QPushButton("Start Radar")
         self._start_btn.setStyleSheet(
             f"QPushButton {{ background-color: {DARK_SUCCESS}; color: white; font-weight: bold; }}"
@@ -1010,8 +1001,7 @@ class RadarDashboard(QMainWindow):
         self._conn_ft2232h = self._make_status_label("FT2232H")
         self._conn_stm32 = self._make_status_label("STM32 USB")
 
-        self._conn_usb_label = QLabel("USB Data:")
-        conn_layout.addWidget(self._conn_usb_label, 0, 0)
+        conn_layout.addWidget(QLabel("FT2232H:"), 0, 0)
         conn_layout.addWidget(self._conn_ft2232h, 0, 1)
         conn_layout.addWidget(QLabel("STM32 USB:"), 1, 0)
         conn_layout.addWidget(self._conn_stm32, 1, 1)
@@ -1177,7 +1167,7 @@ class RadarDashboard(QMainWindow):
         about_lbl = QLabel(
             "<b>AERIS-10 Radar System V7</b><br>"
             "PyQt6 Edition with Embedded Leaflet Map<br><br>"
-            "<b>Data Interface:</b> FT2232H USB 2.0 (production) / FT601 USB 3.0 (premium)<br>"
+            "<b>Data Interface:</b> FT2232H USB 2.0 (production protocol)<br>"
             "<b>FPGA Protocol:</b> 4-byte register commands, 0xAA/0xBB packets<br>"
             "<b>Map:</b> OpenStreetMap + Leaflet.js<br>"
             "<b>Framework:</b> PyQt6 + QWebEngine<br>"
@@ -1234,7 +1224,7 @@ class RadarDashboard(QMainWindow):
     # =====================================================================
 
     def _send_fpga_cmd(self, opcode: int, value: int):
-        """Send a 4-byte register command to the FPGA via USB (FT2232H or FT601)."""
+        """Send a 4-byte register command to the FPGA via FT2232H."""
         if self._connection is None or not self._connection.is_open:
             logger.warning(f"Cannot send 0x{opcode:02X}={value}: no connection")
             return
@@ -1297,26 +1287,16 @@ class RadarDashboard(QMainWindow):
 
             if "Mock" in mode:
                 self._replay_mode = False
-                iface = self._usb_iface_combo.currentText()
-                if "FT601" in iface:
-                    self._connection = FT601Connection(mock=True)
-                else:
-                    self._connection = FT2232HConnection(mock=True)
+                self._connection = FT2232HConnection(mock=True)
                 if not self._connection.open():
                     QMessageBox.critical(self, "Error", "Failed to open mock connection.")
                     return
             elif "Live" in mode:
                 self._replay_mode = False
-                iface = self._usb_iface_combo.currentText()
-                if "FT601" in iface:
-                    self._connection = FT601Connection(mock=False)
-                    iface_name = "FT601"
-                else:
-                    self._connection = FT2232HConnection(mock=False)
-                    iface_name = "FT2232H"
+                self._connection = FT2232HConnection(mock=False)
                 if not self._connection.open():
                     QMessageBox.critical(self, "Error",
-                                         f"Failed to open {iface_name}. Check USB connection.")
+                                         "Failed to open FT2232H. Check USB connection.")
                     return
             elif "Replay" in mode:
                 self._replay_mode = True
@@ -1388,7 +1368,6 @@ class RadarDashboard(QMainWindow):
                 self._start_btn.setEnabled(False)
                 self._stop_btn.setEnabled(True)
                 self._mode_combo.setEnabled(False)
-                self._usb_iface_combo.setEnabled(False)
                 self._demo_btn_main.setEnabled(False)
                 self._demo_btn_map.setEnabled(False)
                 n_frames = self._replay_engine.total_frames
@@ -1438,7 +1417,6 @@ class RadarDashboard(QMainWindow):
             self._start_btn.setEnabled(False)
             self._stop_btn.setEnabled(True)
             self._mode_combo.setEnabled(False)
-            self._usb_iface_combo.setEnabled(False)
             self._demo_btn_main.setEnabled(False)
             self._demo_btn_map.setEnabled(False)
             self._status_label_main.setText(f"Status: Running ({mode})")
@@ -1484,7 +1462,6 @@ class RadarDashboard(QMainWindow):
         self._start_btn.setEnabled(True)
         self._stop_btn.setEnabled(False)
         self._mode_combo.setEnabled(True)
-        self._usb_iface_combo.setEnabled(True)
         self._demo_btn_main.setEnabled(True)
         self._demo_btn_map.setEnabled(True)
         self._status_label_main.setText("Status: Radar stopped")
@@ -1977,12 +1954,6 @@ class RadarDashboard(QMainWindow):
         self._set_conn_indicator(self._conn_ft2232h, conn_open)
         self._set_conn_indicator(self._conn_stm32, self._stm32.is_open)
 
-        # Update USB label to reflect which interface is active
-        if isinstance(self._connection, FT601Connection):
-            self._conn_usb_label.setText("FT601:")
-        else:
-            self._conn_usb_label.setText("FT2232H:")
-
         gps_count = self._gps_packet_count
         if self._gps_worker:
             gps_count = self._gps_worker.gps_count

9_Firmware/9_3_GUI/v7/hardware.py

@@ -25,7 +25,6 @@ if USB_AVAILABLE:
 sys.path.insert(0, os.path.join(os.path.dirname(__file__), ".."))
 from radar_protocol import (  # noqa: F401 — re-exported for v7 package
     FT2232HConnection,
-    FT601Connection,
     RadarProtocol,
     Opcode,
     RadarAcquisition,
@@ -47,9 +46,8 @@ class STM32USBInterface:
 
     Used ONLY for receiving GPS data from the MCU.
 
-    FPGA register commands are sent via the USB data interface — either
-    FT2232HConnection (production) or FT601Connection (premium), both
-    from radar_protocol.py. The old send_start_flag() / send_settings()
+    FPGA register commands are sent via FT2232H (see FT2232HConnection
+    from radar_protocol.py). The old send_start_flag() / send_settings()
     methods have been removed — they used an incompatible magic-packet
     protocol that the FPGA does not understand.
     """

9_Firmware/9_3_GUI/v7/map_widget.py

@@ -98,7 +98,7 @@ class RadarMapWidget(QWidget):
         )
         self._targets: list[RadarTarget] = []
         self._pending_targets: list[RadarTarget] | None = None
-        self._coverage_radius = 1_536   # metres (64 bins x ~24 m/bin)
+        self._coverage_radius = 50_000   # metres
         self._tile_server = TileServer.OPENSTREETMAP
         self._show_coverage = True
         self._show_trails = False

9_Firmware/9_3_GUI/v7/models.py

@@ -108,12 +108,12 @@ class RadarSettings:
     range_resolution and velocity_resolution should be calibrated to
     the actual waveform parameters.
     """
-    system_frequency: float = 10.5e9    # Hz (carrier, used for velocity calc)
-    range_resolution: float = 24.0       # Meters per range bin (c/(2*Fs)*decim)
-    velocity_resolution: float = 1.0     # m/s per Doppler bin (calibrate to waveform)
-    max_distance: float = 1536           # Max detection range (m)
-    map_size: float = 2000               # Map display size (m)
-    coverage_radius: float = 1536        # Map coverage radius (m)
+    system_frequency: float = 10e9      # Hz (carrier, used for velocity calc)
+    range_resolution: float = 781.25    # Meters per range bin (default: 50km/64)
+    velocity_resolution: float = 1.0    # m/s per Doppler bin (calibrate to waveform)
+    max_distance: float = 50000         # Max detection range (m)
+    map_size: float = 50000             # Map display size (m)
+    coverage_radius: float = 50000      # Map coverage radius (m)
 
 
 @dataclass
@@ -199,46 +199,39 @@ class WaveformConfig:
     Encapsulates the radar waveform so that range/velocity resolution
     can be derived automatically instead of hardcoded in RadarSettings.
 
-    Defaults match the AERIS-10 production system parameters from
-    radar_scene.py / plfm_chirp_controller.v:
-      100 MSPS DDC output, 20 MHz chirp BW, 30 us long chirp,
-      167 us long-chirp PRI, X-band 10.5 GHz carrier.
+    Defaults match the ADI CN0566 Phaser capture parameters used in
+    the golden_reference cosim (4 MSPS, 500 MHz BW, 300 us chirp).
     """
 
-    sample_rate_hz: float = 100e6        # DDC output I/Q rate (matched filter input)
-    bandwidth_hz: float = 20e6           # Chirp bandwidth (not used in range calc;
-                                         # retained for time-bandwidth product / display)
-    chirp_duration_s: float = 30e-6      # Long chirp ramp time
-    pri_s: float = 167e-6               # Pulse repetition interval (chirp + listen)
-    center_freq_hz: float = 10.5e9       # Carrier frequency (radar_scene.py: F_CARRIER)
+    sample_rate_hz: float = 4e6          # ADC sample rate
+    bandwidth_hz: float = 500e6          # Chirp bandwidth
+    chirp_duration_s: float = 300e-6     # Chirp ramp time
+    center_freq_hz: float = 10.525e9     # Carrier frequency
     n_range_bins: int = 64               # After decimation
-    n_doppler_bins: int = 32             # Total Doppler bins (2 sub-frames x 16)
-    chirps_per_subframe: int = 16        # Chirps in one Doppler sub-frame
+    n_doppler_bins: int = 32             # After Doppler FFT
     fft_size: int = 1024                 # Pre-decimation FFT length
     decimation_factor: int = 16          # 1024 → 64
 
     @property
     def range_resolution_m(self) -> float:
-        """Meters per decimated range bin (matched-filter pulse compression).
+        """Meters per decimated range bin (FMCW deramped baseband).
 
-        For FFT-based matched filtering, each IFFT output bin spans
-        c / (2 * Fs) in range, where Fs is the I/Q sample rate at the
-        matched-filter input (DDC output).  After decimation the bin
-        spacing grows by *decimation_factor*.
+        For deramped FMCW: bin spacing = c * Fs * T / (2 * N_FFT * BW).
+        After decimation the bin spacing grows by *decimation_factor*.
         """
         c = 299_792_458.0
-        raw_bin = c / (2.0 * self.sample_rate_hz)
+        raw_bin = (
+            c * self.sample_rate_hz * self.chirp_duration_s
+            / (2.0 * self.fft_size * self.bandwidth_hz)
+        )
         return raw_bin * self.decimation_factor
 
     @property
     def velocity_resolution_mps(self) -> float:
-        """m/s per Doppler bin.
-
-        lambda / (2 * chirps_per_subframe * PRI), matching radar_scene.py.
-        """
+        """m/s per Doppler bin.  lambda / (2 * n_doppler * chirp_duration)."""
         c = 299_792_458.0
         wavelength = c / self.center_freq_hz
-        return wavelength / (2.0 * self.chirps_per_subframe * self.pri_s)
+        return wavelength / (2.0 * self.n_doppler_bins * self.chirp_duration_s)
 
     @property
     def max_range_m(self) -> float:

9_Firmware/9_3_GUI/v7/workers.py

@@ -23,7 +23,7 @@ import numpy as np
 
 from PyQt6.QtCore import QThread, QObject, QTimer, pyqtSignal
 
-from .models import RadarTarget, GPSData, RadarSettings, WaveformConfig
+from .models import RadarTarget, GPSData, RadarSettings
 from .hardware import (
     RadarAcquisition,
     RadarFrame,
@@ -84,7 +84,6 @@ class RadarDataWorker(QThread):
         self._recorder = recorder
         self._gps = gps_data_ref
         self._settings = settings or RadarSettings()
-        self._waveform = WaveformConfig()
         self._running = False
 
         # Frame queue for production RadarAcquisition → this thread
@@ -98,9 +97,6 @@ class RadarDataWorker(QThread):
         self._byte_count = 0
         self._error_count = 0
 
-    def set_waveform(self, wf: "WaveformConfig") -> None:
-        self._waveform = wf
-
     def stop(self):
         self._running = False
         if self._acquisition:
@@ -173,8 +169,8 @@ class RadarDataWorker(QThread):
         The FPGA already does: FFT, MTI, CFAR, DC notch.
         Host-side DSP adds: clustering, tracking, geo-coordinate mapping.
 
-        Bin-to-physical conversion uses self._waveform (WaveformConfig) to keep
-        live and replay units aligned. Override via set_waveform() if needed.
+        Bin-to-physical conversion uses RadarSettings.range_resolution
+        and velocity_resolution (should be calibrated to actual waveform).
         """
         targets: list[RadarTarget] = []
 
@@ -184,11 +180,8 @@ class RadarDataWorker(QThread):
 
         # Extract detections from FPGA CFAR flags
         det_indices = np.argwhere(frame.detections > 0)
-        r_res = self._waveform.range_resolution_m
-        v_res = self._waveform.velocity_resolution_mps
-        n_doppler = (frame.detections.shape[1] if frame.detections.ndim == 2
-                     else self._waveform.n_doppler_bins)
-        doppler_center = n_doppler // 2
+        r_res = self._settings.range_resolution
+        v_res = self._settings.velocity_resolution
 
         for idx in det_indices:
             rbin, dbin = idx
@@ -197,9 +190,8 @@ class RadarDataWorker(QThread):
 
             # Convert bin indices to physical units
             range_m = float(rbin) * r_res
-            # Doppler: centre bin = 0 m/s; positive bins = approaching.
-            # Derived from frame shape — mirrors processing.py:520.
-            velocity_ms = float(dbin - doppler_center) * v_res
+            # Doppler: centre bin (16) = 0 m/s; positive bins = approaching
+            velocity_ms = float(dbin - 16) * v_res
 
             # Apply pitch correction if GPS data available
             raw_elev = 0.0  # FPGA doesn't send elevation per-detection
@@ -342,7 +334,7 @@ class TargetSimulator(QObject):
             self._add_random_target()
 
     def _add_random_target(self):
-        range_m = random.uniform(50, 1400)
+        range_m = random.uniform(5000, 40000)
         azimuth = random.uniform(0, 360)
         velocity = random.uniform(-100, 100)
         elevation = random.uniform(-5, 45)
@@ -376,7 +368,7 @@ class TargetSimulator(QObject):
 
         for t in self._targets:
             new_range = t.range - t.velocity * 0.5
-            if new_range < 10 or new_range > 1536:
+            if new_range < 500 or new_range > 50000:
                 continue  # target exits coverage — drop it
 
             new_vel = max(-150, min(150, t.velocity + random.uniform(-2, 2)))

9_Firmware/tests/cross_layer/contract_parser.py

@@ -108,23 +108,12 @@ class ConcatWidth:
 
 def parse_python_opcodes(filepath: Path | None = None) -> dict[int, OpcodeEntry]:
     """Parse the Opcode enum from radar_protocol.py.
-    Returns {opcode_value: OpcodeEntry}, excluding MCU_ONLY_OPCODES.
-    MCU-only opcodes have no FPGA case statement and must not appear in
-    the bidirectional Python/Verilog contract check.
+    Returns {opcode_value: OpcodeEntry}.
     """
     if filepath is None:
         filepath = GUI_DIR / "radar_protocol.py"
     text = filepath.read_text()
 
-    # Extract MCU_ONLY_OPCODES set so we can exclude those values below.
-    mcu_only: set[int] = set()
-    m_set = re.search(r'MCU_ONLY_OPCODES[^=]*=\s*frozenset\(\{([^}]*)\}\)', text)
-    if m_set:
-        for tok in m_set.group(1).split(','):
-            tok = tok.strip()
-            if tok.startswith(('0x', '0X')):
-                mcu_only.add(int(tok, 16))
-
     # Find the Opcode class body
     match = re.search(r'class Opcode\b.*?(?=\nclass |\Z)', text, re.DOTALL)
     if not match:
@@ -134,8 +123,7 @@ def parse_python_opcodes(filepath: Path | None = None) -> dict[int, OpcodeEntry]
     for m in re.finditer(r'(\w+)\s*=\s*(0x[0-9a-fA-F]+)', match.group()):
         name = m.group(1)
         value = int(m.group(2), 16)
-        if value not in mcu_only:
-            opcodes[value] = OpcodeEntry(name=name, value=value)
+        opcodes[value] = OpcodeEntry(name=name, value=value)
     return opcodes
 
 
@@ -200,7 +188,7 @@ def parse_python_data_packet_fields(filepath: Path | None = None) -> list[DataPa
             width_bits=size * 8
         ))
 
-    # Match detection = raw[9] & 0x01  (direct access)
+    # Match detection = raw[9] & 0x01
     for m in re.finditer(r'(\w+)\s*=\s*raw\[(\d+)\]\s*&\s*(0x[0-9a-fA-F]+|\d+)', body):
         name = m.group(1)
         offset = int(m.group(2))
@@ -208,24 +196,6 @@ def parse_python_data_packet_fields(filepath: Path | None = None) -> list[DataPa
             name=name, byte_start=offset, byte_end=offset, width_bits=1
         ))
 
-    # Match intermediate variable pattern: var = raw[N], then field = var & MASK
-    for m in re.finditer(r'(\w+)\s*=\s*raw\[(\d+)\]', body):
-        var_name = m.group(1)
-        offset = int(m.group(2))
-        # Find fields derived from this intermediate variable
-        for m2 in re.finditer(
-            rf'(\w+)\s*=\s*(?:\({var_name}\s*>>\s*\d+\)\s*&|{var_name}\s*&)\s*'
-            r'(0x[0-9a-fA-F]+|\d+)',
-            body,
-        ):
-            name = m2.group(1)
-            # Skip if already captured by direct raw[] access pattern
-            if not any(f.name == name for f in fields):
-                fields.append(DataPacketField(
-                    name=name, byte_start=offset, byte_end=offset,
-                    width_bits=1
-                ))
-
     fields.sort(key=lambda f: f.byte_start)
     return fields
 
@@ -614,28 +584,12 @@ def parse_verilog_data_mux(
 
     for m in re.finditer(
         r"5'd(\d+)\s*:\s*data_pkt_byte\s*=\s*(.+?);",
-        mux_body, re.DOTALL
+        mux_body
     ):
         idx = int(m.group(1))
         expr = m.group(2).strip()
         entries.append((idx, expr))
 
-    # Helper: extract the dominant signal name from a mux expression.
-    # Handles direct refs like ``range_profile_cap[31:24]``, ternaries
-    # like ``stream_doppler_en ? doppler_real_cap[15:8] : 8'd0``, and
-    # concat-ternaries like ``stream_cfar_en ? {…, cfar_detection_cap} : …``.
-    def _extract_signal(expr: str) -> str | None:
-        # If it's a ternary, use the true-branch to find the data signal
-        tern = re.match(r'\w+\s*\?\s*(.+?)\s*:\s*.+', expr, re.DOTALL)
-        target = tern.group(1) if tern else expr
-        # Look for a known data signal (xxx_cap pattern or cfar_detection_cap)
-        cap_match = re.search(r'(\w+_cap)\b', target)
-        if cap_match:
-            return cap_match.group(1)
-        # Fall back to first identifier before a bit-select
-        sig_match = re.match(r'(\w+?)(?:\[|$)', target)
-        return sig_match.group(1) if sig_match else None
-
     # Group consecutive bytes by signal root name
     fields: list[DataPacketField] = []
     i = 0
@@ -645,21 +599,22 @@ def parse_verilog_data_mux(
             i += 1
             continue
 
-        signal = _extract_signal(expr)
-        if not signal:
+        # Extract signal name (e.g., range_profile_cap from range_profile_cap[31:24])
+        sig_match = re.match(r'(\w+?)(?:\[|$)', expr)
+        if not sig_match:
             i += 1
             continue
 
+        signal = sig_match.group(1)
         start_byte = idx
         end_byte = idx
 
         # Find consecutive bytes of the same signal
         j = i + 1
         while j < len(entries):
-            _next_idx, next_expr = entries[j]
-            next_sig = _extract_signal(next_expr)
-            if next_sig == signal:
-                end_byte = _next_idx
+            next_idx, next_expr = entries[j]
+            if next_expr.startswith(signal):
+                end_byte = next_idx
                 j += 1
             else:
                 break

9_Firmware/tests/cross_layer/tb_cross_layer_ft2232h.v

@@ -620,10 +620,8 @@ module tb_cross_layer_ft2232h;
               "Data pkt: byte 7 = 0x56 (doppler_imag MSB)");
         check(captured_bytes[8] === 8'h78,
               "Data pkt: byte 8 = 0x78 (doppler_imag LSB)");
-        // Byte 9 = {frame_start, 6'b0, cfar_detection}
-        // After reset sample_counter==0, so frame_start=1 → 0x81
-        check(captured_bytes[9] === 8'h81,
-              "Data pkt: byte 9 = 0x81 (frame_start=1, cfar_detection=1)");
+        check(captured_bytes[9] === 8'h01,
+              "Data pkt: byte 9 = 0x01 (cfar_detection=1)");
         check(captured_bytes[10] === 8'h55,
               "Data pkt: byte 10 = 0x55 (footer)");
 

CONTRIBUTING.md

@@ -5,109 +5,140 @@ for getting a change reviewed and merged.
 
 ## Getting started
 
-1. Fork the repository and create a topic branch from `develop`. The `main` branch is for production releases only.
-2. Keep generated outputs (Vivado projects, bitstreams, build logs) out of version control.
-
-### Security Mandate: Package Installation
-Due to supply chain attack risks, **ALL package installations MUST use the `sfw` (secure firewall) prefix**.
-- Python: `sfw uv pip install <package>` (Do not use raw pip)
-- Node/JS: `sfw npm install <package>`
-- Rust/Cargo: `sfw cargo <command>`
-
-Never run bare package installation commands without the `sfw` prefix.
+1. Fork the repository and create a topic branch from `develop`.
+2. Keep generated outputs (Vivado projects, bitstreams, build logs)
+   out of version control — the `.gitignore` already covers most of
+   these.
 
 ## Repository layout
 
 | Path | Contents |
 |------|----------|
 | `4_Schematics and Boards Layout/` | KiCad schematics, Gerbers, BOM/CPL |
-| `9_Firmware/9_1_Microcontroller/` | STM32 MCU C/C++ firmware and unit tests |
 | `9_Firmware/9_2_FPGA/` | Verilog RTL, constraints, testbenches, build scripts |
-| `9_Firmware/9_3_GUI/` | Python radar dashboard (Tkinter/PyQt6) and CLI tools |
-| `9_Firmware/tests/cross_layer/` | Python-based system invariant/contract tests |
+| `9_Firmware/9_2_FPGA/formal/` | SymbiYosys formal-verification wrappers |
+| `9_Firmware/9_2_FPGA/scripts/` | Vivado TCL build & debug scripts |
+| `9_Firmware/9_3_GUI/` | Python radar dashboard (Tkinter + matplotlib) |
 | `docs/` | GitHub Pages documentation site |
 
-## Code Standards & Tooling
+## Before submitting a pull request
 
-- **Python (GUI, Scripts, Tests)**:
-  - We use `uv` for dependency management.
-  - We strictly enforce linting with `ruff`. Run `uv run ruff check .` before committing.
-  - Test with `pytest`.
-- **Verilog (FPGA)**:
-  - The RTL (`radar_system_top.v`) is the single source of truth for opcode values, bit widths, reset defaults, and valid ranges.
-  - Testbenches must include **adversarial validation**: actively test boundary conditions, race conditions, unexpected input sequences, and reset mid-operation.
-  - Use `iverilog` for simulation.
-- **C/C++ (MCU)**:
-  - Use `make test` for host-side unit testing (cpputest).
-- **System-Level Invariants**:
-  - Whenever adding code, verify that system-level invariants (across module, process, and chip boundaries) hold true.
+- **Python** — verify syntax: `python3 -m py_compile <file>`
+- **Verilog** — if you have Vivado, run the relevant `build*.tcl`;
+  if not, note which scripts your change affects
+- **Whitespace** — `git diff --check` should be clean
+- Keep PRs focused: one logical change per PR is easier to review
+- **Run the regression tests** (see below)
 
-## AI Usage Policy
+## Running regression tests
 
-The use of AI is permitted but we have to make sure that the quality and control of the codebase doesn't depend on the agents but the maintainer pushing the changes, meaning they are fully responsible for the code they commit.
+After any change, run the relevant test suites to verify nothing is
+broken. All commands assume you are at the repository root.
 
-1. **Human Accountability** — The committing engineer is fully responsible for AI-generated code as if they wrote it. Every PR must be understood and defensible by a human.
-2. **Mandatory Review** — No raw AI output may be committed unread. AI code must pass the same review bar as hand-written code.
-3. **Full CI Before Commit** — All AI-assisted changes must pass the complete CI suite locally (lint, unit, regression, cross-layer) before commit.
+### Prerequisites
 
-## Running the Test Suites
+| Tool | Used by | Install |
+|------|---------|---------|
+| [Icarus Verilog](http://iverilog.icarus.com/) (`iverilog`) | FPGA regression | `brew install icarus-verilog` / `apt install iverilog` |
+| Python 3.8+ | GUI tests, co-sim | Usually pre-installed |
+| GNU Make | MCU tests | Usually pre-installed |
+| [SymbiYosys](https://symbiyosys.readthedocs.io/) (`sby`) | Formal verification | Optional — see SymbiYosys docs |
 
-We use GitHub Actions for CI, which runs four main jobs on every PR. Run these locally before pushing.
+### FPGA regression (RTL lint + unit/integration/signal-processing tests)
 
-### 1. Python & Linting
-```bash
-uv run ruff check .
-cd 9_Firmware/9_3_GUI
-uv run pytest test_GUI_V65_Tk.py test_v7.py -v
-```
-
-### 2. FPGA Regression
 ```bash
 cd 9_Firmware/9_2_FPGA
 bash run_regression.sh
 ```
-This runs five phases (Lint, Changed Modules, Integration, Signal Processing, Infrastructure, and **P0 Adversarial Tests**). All must pass.
 
-### 3. MCU Unit Tests
+This runs four phases:
+
+| Phase | What it checks |
+|-------|----------------|
+| 0 — Lint | `iverilog -Wall` on all production RTL + static regex checks |
+| 1 — Changed Modules | Unit tests for individual blocks (CIC, Doppler, CFAR, etc.) |
+| 2 — Integration | DDC chain, receiver golden-compare, system-top, end-to-end |
+| 3 — Signal Processing | FFT engine, NCO, FIR, matched filter chain |
+| 4 — Infrastructure | CDC modules, edge detector, USB interface, range-bin decimator, mode controller |
+
+All tests must pass (exit code 0). Advisory lint warnings (e.g., `case
+without default`) are non-blocking.
+
+### MCU unit tests
+
 ```bash
 cd 9_Firmware/9_1_Microcontroller/tests
-make clean && make
+make clean && make all
 ```
 
-### 4. Cross-Layer Contract Tests
+Runs 20 C-based unit tests covering safety, bug-fix, and gap-3 tests.
+Every test binary must exit 0.
+
+### GUI / dashboard tests
+
 ```bash
-uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py -v
+cd 9_Firmware/9_3_GUI
+python3 -m pytest test_GUI_V65_Tk.py -v
+# or without pytest:
+python3 -m unittest test_GUI_V65_Tk -v
 ```
 
-## Before merging: CI checklist
+57+ protocol and rendering tests. The `test_record_and_stop` test
+requires `h5py` and will be skipped if it is not installed.
 
-All PRs must pass CI:
+### Co-simulation (Python vs RTL golden comparison)
 
-| Job | What it checks |
-|----|---------------|
-| `python-tests` | ruff clean + pytest green |
-| `mcu-tests` | make all exits 0 |
-| `fpga-regression` | run_regression.sh exits 0 |
-| `cross-layer-tests` | pytest exits 0 |
+Run from the co-sim directory after a successful FPGA regression (the
+regression generates the RTL CSV outputs that the co-sim scripts compare
+against):
 
-## Important Notes
+```bash
+cd 9_Firmware/9_2_FPGA/tb/cosim
 
-- **NO LEGACY COMPATIBILITY** unless explicitly requested by the maintainer.
-- **The FPGA RTL (`radar_system_top.v`) is the single source of truth** for opcode values, bit widths, reset defaults, and valid ranges. All other layers must align to it.
-- **Adversarial testing is mandatory**: Every test must actively try to break the code.
-- **Testbench timing**: Always add a `#1` delay after `@(posedge clk)` before driving DUT inputs with blocking assignments.
-- **Pre-fetch FIFO**: Remember `wr_full` is asserted after DEPTH+1 writes, not just DEPTH.
+# Validate all .mem files (twiddles, chirp ROMs, addressing)
+python3 validate_mem_files.py
 
-## Checklist Before Push
+# DDC chain: RTL vs Python model (5 scenarios)
+python3 compare.py dc
+python3 compare.py single_target
+python3 compare.py multi_target
+python3 compare.py noise_only
+python3 compare.py sine_1mhz
 
-- [ ] `uv run ruff check .` — no lint errors
-- [ ] `uv run pytest test_GUI_V65_Tk.py test_v7.py -v` — all pass
-- [ ] `cd 9_Firmware/9_2_FPGA && bash run_regression.sh` — all 5 phases pass
-- [ ] `cd 9_Firmware/9_1_Microcontroller/tests && make clean && make` — pass
-- [ ] `uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py` — pass
-- [ ] `git diff --check` — no whitespace issues
-- [ ] PR targets `develop` branch
+# Doppler processor: RTL vs golden reference
+python3 compare_doppler.py stationary
+
+# Matched filter: RTL vs Python model (4 scenarios)
+python3 compare_mf.py all
+```
+
+Each script prints PASS/FAIL per scenario and exits non-zero on failure.
+
+### Formal verification (optional)
+
+Requires SymbiYosys (`sby`), Yosys, and a solver (z3 or boolector):
+
+```bash
+cd 9_Firmware/9_2_FPGA/formal
+sby -f fv_doppler_processor.sby
+sby -f fv_radar_mode_controller.sby
+```
+
+### Quick checklist
+
+Before pushing, confirm:
+
+1. `bash run_regression.sh` — all phases pass
+2. `make all` (MCU tests) — 20/20 pass
+3. `python3 -m unittest test_GUI_V65_Tk -v` — all pass
+4. `python3 validate_mem_files.py` — all checks pass
+5. `python3 compare.py dc && python3 compare_doppler.py stationary && python3 compare_mf.py all`
+6. `git diff --check` — no whitespace issues
+
+## Areas where help is especially welcome
+
+See the list in [README.md](README.md#-contributing).
 
 ## Questions?
 
-Open a GitHub issue — discussion is visible to everyone.
+Open a GitHub issue — that way the discussion is visible to everyone.

README.md

@@ -7,6 +7,7 @@
 [![Frequency: 10.5GHz](https://img.shields.io/badge/Frequency-10.5GHz-blue)](https://github.com/NawfalMotii79/PLFM_RADAR)
 [![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg)](https://github.com/NawfalMotii79/PLFM_RADAR/pulls)
 
+![AERIS-10 Radar System](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/3fb1dabf-2c6d-4b5d-b471-48bc461ce914.jpg)
 
 AERIS-10 is an open-source, low-cost 10.5 GHz phased array radar system featuring Pulse Linear Frequency Modulated (LFM) modulation. Available in two versions (3km and 20km range), it's designed for researchers, drone developers, and serious SDR enthusiasts who want to explore and experiment with phased array radar technology.
 
@@ -46,13 +47,13 @@ The AERIS-10 main sub-systems are:
 
 - **Main Board** containing:
   - **DAC** - Generates the RADAR Chirps
-  - **2x Microwave Mixers (LTC5552)** - For up-conversion and IF-down-conversion
+  - **2x Microwave Mixers (LT5552)** - For up-conversion and IF-down-conversion
   - **4x 4-Channel Phase Shifters (ADAR1000)** - For RX and TX chain beamforming
   - **16x Front End Chips (ADTR1107)** - Used for both Low Noise Amplifying (RX) and Power Amplifying (TX) stages
   - **XC7A50T FPGA** - Handles RADAR Signal Processing on the upstream FTG256 board:
     - PLFM Chirps generation via the DAC
     - Raw ADC data read
-    - Hybrid Automatic Gain Control (AGC) — cross-layer FPGA/STM32/GUI loop
+    - Digital Gain Control (host-configurable gain shift)
     - I/Q Baseband Down-Conversion
     - Decimation
     - Filtering
@@ -91,7 +92,7 @@ The AERIS-10 main sub-systems are:
 ### Processing Pipeline
 
 1. **Waveform Generation** - DAC creates LFM chirps
-2. **Up/Down Conversion** - LTC5552 mixers handle frequency translation
+2. **Up/Down Conversion** - LT5552 mixers handle frequency translation
 3. **Beam Steering** - ADAR1000 phase shifters control 16 elements
 4. **Signal Processing (FPGA)**:
    - Raw ADC data capture
@@ -110,8 +111,7 @@ The AERIS-10 main sub-systems are:
    - Map integration
    - Radar control interface
 
-![AERIS-10 Dashboard](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/GUI_V6.gif)
-<!-- V6 GIF removed — V6 is deprecated. V65 Tk and V7 PyQt6 are the active GUIs. -->
+![AERIS-10 GUI Demo](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/GUI_V6.gif)
 
 ## 📊 Technical Specifications
 

docs/index.html

@@ -32,11 +32,6 @@
     </section>
 
     <section class="stats-grid">
-      <article class="card stat notice">
-        <h2>Production Board USB</h2>
-        <p class="metric">FT2232H (USB 2.0)</p>
-        <p class="muted">50T production board uses FT2232H. FT601 USB 3.0 is available on 200T premium dev board only.</p>
-      </article>
       <article class="card stat">
         <h2>Tracked Timing Baseline</h2>
         <p class="metric">WNS +0.058 ns</p>