5499827ab7
add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean)
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FMC LPC dev build for TE0713/TE0701 + UMFT601X-B stack. Fixed timing
closure: replaced set_output_delay with set_max_delay -datapath_only
to eliminate false IBUF+BUFG clock skew penalty on source-synchronous
outputs. Removed erroneous set_input_delay on output-only ft601_be[*].
Added IOB packing for siwu_n, false paths for async GPIO/reset/wakeup.
Strategy: Performance_ExplorePostRoutePhysOpt.
Results: WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors, 0 failing endpoints.
Bitstream: docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit
2026-03-21 20:43:52 +02:00
2efab23cd9
Fix Vivado DRC: consolidate data_pending flags into single always block, fix MMCM LOCKED false_path
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usb_data_interface.v: doppler_data_pending and cfar_data_pending were
driven by two always blocks (CDC sync block set them, write FSM cleared
them). Vivado DRC MDRV-1 flagged this as multiple drivers. Moved all
set/clear logic into the write FSM always block using doppler_valid_ft
and cfar_valid_ft edge wires.
adc_clk_mmcm.xdc: changed set_false_path -from to -through for MMCM
LOCKED pin (not a valid timing startpoint). Eliminates CRITICAL WARNING
from Builds 19/20/21.
19/19 FPGA regression pass.
2026-03-20 01:56:20 +02:00
c6103b37de
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
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MMCM (Gap 7):
- Add adc_clk_mmcm.v: MMCME2_ADV wrapper (VCO=800MHz, CLKOUT0=400MHz)
- Modify ad9484_interface_400m.v: replace BUFG with MMCM path, gate reset on mmcm_locked
- Add adc_clk_mmcm.xdc: CDC false paths for clk_mmcm_out0 <-> clk_100m
XDC Fix (Build 19 WNS=-0.011 root cause):
- Remove conflicting create_generated_clock -name clk_400m_mmcm
- Replace all clk_400m_mmcm references with Vivado auto-generated clk_mmcm_out0
- CDC false paths now correctly apply to actual timing paths
CIC CREG Pipeline (Build 18 critical path fix):
- Explicit DSP48E1 for comb[0] with CREG=1/AREG=1/BREG=1/PREG=1
- Absorbs integrator_sampled_comb fabric FDRE into DSP48 C-port register
- Eliminates 0.643ns fabric->DSP routing delay (Build 18 tightest path)
- +1 cycle comb latency via data_valid_comb_0_out pipeline
- Move shared register declarations above ifndef SIMULATION (iverilog fix)
- Update golden data for +1 cycle CIC pipeline shift
Build scripts: build19_mmcm.tcl, build20_mmcm_creg.tcl
Regression: 18/18 FPGA pass, 20/20 MCU pass
Build 20 launched on remote Vivado (pending results)
2026-03-19 22:59:46 +02:00
683e70e784
Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments
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- Changed user_led/system_status IOSTANDARD from LVCMOS25 to LVCMOS33
to match VIOTB=3.3V needed for FT601 on Bank 16
- Added register init value for hb_counter
- Added comments documenting clock source (50 MHz FIFO0CLK at U20, Bank 14)
and expected LED toggle rates
2026-03-19 16:47:59 +02:00
9b786eb33f
Add FMC-path FT601 XDC for TE0713+TE0701+UMFT601X-B pin mapping
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Maps all 47 FT601 signals through FMC LPC J10 to correct FPGA pins:
- DATA[31:0] + D_CLK: Bank 15 (LA17-LA33)
- BE_N[3:0], control, status: Bank 16 (LA00-LA15)
Both banks share VIOTB rail — set to 3.3V for LVCMOS33.
Includes timing constraints and RTL adaptation notes.
2026-03-19 16:20:56 +02:00
e62f3cd950
Port validated Build 16 XDC cleanup and sync docs
2026-03-19 14:34:26 +02:00
967ce179eb
Add TE0713/TE0701 alternate dev target for in-stock SoM path
2026-03-18 15:02:09 +02:00
0ae7b40ff0
Add TE0712/TE0701 split target with dedicated top, XDC, and build flow
2026-03-18 03:57:26 +02:00
f6877aab64
Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
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- Rename latency_buffer_2159 -> latency_buffer (module + file + all refs)
- Add CDC waivers for 5 verified false-positive criticals to XDC
- Add ILA debug probe insertion script (4 cores, 126 probe bits, 2 clock domains)
- Add FPGA programming script (7-step flow with DONE pin verification)
- Add ILA capture script (4 scenarios + health check, CSV export)
- Add debug_ila.xdc with MARK_DEBUG fallback attributes
- Full regression clean: 13/13 suites, 266/266 checks, 2048/2048 golden match
2026-03-18 01:28:42 +02:00
fcf3999e39
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
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Split cdc_adc_to_processing reset_n into src_reset_n/dst_reset_n so source
and destination clock domains use correctly-synchronized resets. Previously
cdc_chirp_counter's destination-side sync chain (100MHz) was reset by
sys_reset_120m_n (120MHz domain), causing 30 CDC critical warnings.
RTL changes:
- cdc_modules.v: split reset port, source logic uses src_reset_n,
destination sync chains + output logic use dst_reset_n
- radar_system_top.v: cdc_chirp_counter gets proper per-domain resets
- ddc_400m.v: CDC_FIR_i/q use reset_n_400m (src) and reset_n (dst)
- formal/fv_cdc_adc.v: updated wrapper for new port interface
Build 7 fixes (previously untouched):
- radar_transmitter.v: SPI level-shifter assigns, STM32 GPIO CDC sync
- latency_buffer_2159.v: BRAM read registration
- constraints: ft601 IOB -quiet fix
- tb_latency_buffer.v: updated for BRAM changes
Testbench hardening (tb_cdc_modules.v, +31 new assertions):
- A5-A7: split-domain reset tests (staggered deassertion, independent
dst reset while src active — catches the P0 bug class)
- A8: port connectivity (no X/Z on outputs)
- B7: cdc_single_bit port connectivity
- C6: cdc_handshake reset recovery + port connectivity
Full regression: 13/13 test suites pass (257 total assertions).
2026-03-17 19:38:09 +02:00
49eb6169b6
Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB
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- Expand ft601_be from [1:0] to [3:0] across RTL, top-level, testbenches,
and XDC (uncomment be[2:3] pin assignments B21/A21)
- Fix NCO XSim testbench: correct reset check (0x7FFF not 0), add pipeline
warmup and sample skip for DSP48E1 quadrature test
- All local regression tests pass (39/39 USB, 10/10 integration, all co-sim)
2026-03-16 23:17:38 +02:00
af1af3bb91
Fix XDC for timing closure: add hold waivers, remove stale constraints
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Build 3 on XC7A200T-2FBG484I achieves full timing closure:
- WNS +0.040ns (setup), WHS +0.036ns (hold), 0 failing endpoints
- Add 3 hold false-path waivers for ODDR/BUFIO I/O boundaries
(DAC clk_120m→dac_clk_fwd, FT601 ft601_clk_in→ft601_clk_fwd,
ADC adc_d_p→adc_dco_p) — all artifacts of STA modeling
- Comment out ft601_be[2:3] pins (RTL only drives [1:0])
- Remove CIC multicycle paths (DSP48E1 cells not matchable)
- Add -quiet to IOB properties for tristate/optimized registers
2026-03-16 23:04:16 +02:00
1acedf494c
Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I
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Production FPGA: Artix-7 XC7A200T-2FBG484I (33,650 slices, 740 DSP48E1,
365 BRAM, -2 speed grade). Pin-mapped across 6 banks with proper VCCO
assignment (3.3V/2.5V/1.8V).
RTL timing primitives added for clean timing closure:
- ad9484_interface_400m.v: BUFIO for IDDR capture at 400MHz DDR,
BUFG for fabric logic, reset synchronizer (P1-7)
- dac_interface_single.v: ODDR for dac_clk forwarding + dac_data[7:0]
output registration, eliminates clock-forwarding insertion delay
- usb_data_interface.v: ODDR for ft601_clk_out forwarding, FSM runs
on ft601_clk_in domain with CDC synchronizers
Constraints:
- New production XDC (xc7a200t_fbg484.xdc): 182 pins, generated clocks
for ODDR outputs, BUFIO/DDR input delays, fixed false_path strategy
(from reset source, not to CLR pins), IOB packing on cells not ports
- Preserved upstream XDC as xc7a50t_ftg256.xdc for reference
- Updated cntrt.xdc with DRC fixes (I/O standards, missing constraints)
2026-03-16 22:24:22 +02:00
Jason