- usb_data_interface.v: Add 3 self-test status inputs, expand status packet
from 7 words (header + 5 data + footer) to 8 words (header + 6 data + footer).
New status_words[5] carries {busy, detail[7:0], flags[4:0]}.
- radar_system_top.v: Wire self_test_flags_latched, self_test_detail_latched,
self_test_busy to usb_data_interface ports. Add opcode 0x31 as status
readback alias so host can read self-test results.
- tb_usb_data_interface.v: Add self-test port connections, verify word 5 in
Group 16, add Group 18 (busy flag + partial failure variant). 81 checks pass.
- run_regression.sh: Add fpga_self_test.v to PROD_RTL lint list and system-
level compile lists. Add tb_fpga_self_test as Phase 1 unit test.
- 24/24 regression tests pass, lint clean (0 errors, 4 advisory warnings).
MTI canceller (2-pulse, H(z)=1-z^{-1}) between range decimator and
Doppler processor. Subtracts previous chirp from current, nulling DC
Doppler (stationary clutter). Pass-through when host_mti_enable=0.
DC notch filter (post-Doppler, pre-CFAR) zeros bins within
+/-host_dc_notch_width of DC. Complements MTI for residual clutter.
New host registers: 0x26 (mti_enable), 0x27 (dc_notch_width).
Both default to 0 (disabled) - fully backward-compatible.
Verification: 23/23 regression, 29/29 MTI standalone, 3/3 real-data
co-sim (5137/5137 exact match) all PASS.
Split ST_CFAR_THR into two pipeline stages (THR + MUL) to fix Build 23
timing violation (WNS = -0.309 ns). The combinational path from
leading_sum through GO/SO cross-multiply into alpha*noise DSP was too
long for 10 ns.
New pipeline:
ST_CFAR_THR: register noise_sum_comb (mode select + cross-multiply)
ST_CFAR_MUL: compute alpha * noise_sum_reg in DSP
ST_CFAR_CMP: compare + update window (unchanged)
3 cycles per CUT instead of 2 (~85 us vs 70 us per frame, negligible).
All detection results identical: 23/23 CFAR standalone, 22/22 full
regression, 3/3 real-data co-sim (5137/5137 exact match) PASS.
usb_data_interface.v: doppler_data_pending and cfar_data_pending were
driven by two always blocks (CDC sync block set them, write FSM cleared
them). Vivado DRC MDRV-1 flagged this as multiple drivers. Moved all
set/clear logic into the write FSM always block using doppler_valid_ft
and cfar_valid_ft edge wires.
adc_clk_mmcm.xdc: changed set_false_path -from to -through for MMCM
LOCKED pin (not a valid timing startpoint). Eliminates CRITICAL WARNING
from Builds 19/20/21.
19/19 FPGA regression pass.
RTL fixes discovered via new end-to-end testbench:
- plfm_chirp_controller: TX/RX mixer enables now mutually exclusive
by FSM state (Fix#4), preventing simultaneous TX+RX activation
- usb_data_interface: stream control reset default 3'b001 (range-only),
added doppler/cfar data_pending sticky flags, write FSM triggers on
range_valid only — eliminates startup deadlock (Fix#5)
- radar_receiver_final: STM32 toggle signals wired through for mode-00
pass-through, dynamic frame detection via host_chirps_per_elev
- radar_system_top: STM32 toggle signal wiring to receiver instance
- chirp_memory_loader_param: explicit readmemh range for short chirp
Test infrastructure:
- New tb_system_e2e.v: 46 checks across 12 groups (reset, TX, safety,
RX, USB R/W, CDC, beam scanning, reset recovery, stream control,
latency budgets, watchdog)
- tb_usb_data_interface: Tests 21/22/56 updated for data_pending
architecture (preload flags, verify consumption instead of state)
- tb_chirp_controller: mixer tests T7.1/T7.2 updated for Fix#4
- run_regression.sh: PASS/FAIL regex fixed to match only [PASS]/[FAIL]
markers, added E2E test entry
- Updated rx_final_doppler_out.csv golden data
Opt 1: Eliminated ST_BF_SHIFT state — arithmetic right-shift is pure
bit-selection (zero logic levels), merged into BF_WRITE combinational
add/subtract. Saves LOG2N * N/2 = 5120 cycles per 1024-pt FFT.
Opt 2: Replaced idx_val * tw_stride_reg general multiply with
idx_val << (LOG2N-1-stage) barrel shift. tw_stride_reg is always a
power of 2, so this is mathematically identical and frees a multiplier.
Regression: 18/18 FPGA pass (bit-exact results).
- release-notes.html: Add commits for Gaps 3-5-7-4, tagged releases table,
architectural gap status table, updated GitHub links
- implementation-log.html: Add Build 20/19/18 timeline entries, Gap 3-4-5
milestones, updated quality/build history sections
- reports.html: Update FPGA status to Build 20 baseline, MCU regression
to 20/20, report currency notice with current gap status
Adds two-layer lint pass (iverilog -Wall + custom static checks) that
catches part-select OOB errors and case-without-default warnings before
pushing to remote Vivado. Catches the exact Synth 8-524 class error that
broke Build 18 initial attempt. Lint errors abort regression; warnings
are advisory. Regenerated golden data for BRAM-migrated matched filter.
Vivado 2025.2 (Synth 8-524): overlap_copy_count is 8-bit but [9:0]
part-select was 10-bit. Changed to explicit zero-extend concat.
Added default case to FSM to suppress non-full case warning.
- Changed user_led/system_status IOSTANDARD from LVCMOS25 to LVCMOS33
to match VIOTB=3.3V needed for FT601 on Bank 16
- Added register init value for hb_counter
- Added comments documenting clock source (50 MHz FIFO0CLK at U20, Bank 14)
and expected LED toggle rates
Maps all 47 FT601 signals through FMC LPC J10 to correct FPGA pins:
- DATA[31:0] + D_CLK: Bank 15 (LA17-LA33)
- BE_N[3:0], control, status: Bank 16 (LA00-LA15)
Both banks share VIOTB rail — set to 3.3V for LVCMOS33.
Includes timing constraints and RTL adaptation notes.
NawfalMotii79
Jason