Add board-day worksheet and cross-link bring-up docs
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Jason
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<!doctype html>
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<html lang="en">
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<head>
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<meta charset="utf-8">
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<meta name="viewport" content="width=device-width, initial-scale=1">
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<title>AERIS-10 Docs | Board-Day Worksheet</title>
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<link rel="stylesheet" href="assets/style.css">
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</head>
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<body>
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<header class="topbar">
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<div class="container nav">
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<a class="brand" href="index.html">AERIS-10 Docs</a>
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<nav>
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<a href="architecture.html">Architecture</a>
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<a href="implementation-log.html">Implementation Log</a>
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<a href="bring-up.html">Bring-Up</a>
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<a href="reports.html">Reports</a>
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<a href="release-notes.html">Release Notes</a>
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</nav>
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</div>
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</header>
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<main class="container page">
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<section class="hero">
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<p class="eyebrow">Board-Day Execution</p>
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<h1>Board-Day Worksheet</h1>
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<p>Printable operator worksheet for the first FPGA module and carrier-board sessions. Use this alongside the bring-up plan and artifact inventory to capture evidence, pass/fail state, and blockers in real time.</p>
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<div class="cta-row">
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<a class="button" href="bring-up.html">Open Bring-Up Plan</a>
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<a class="button ghost" href="reports.html">Open Artifact Inventory</a>
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</div>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Session metadata</h2>
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<div class="table-wrap">
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<table>
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<tbody>
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<tr><td>Date / Time</td><td></td><td>Operator</td><td></td></tr>
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<tr><td>Carrier board revision</td><td></td><td>FPGA module revision</td><td></td></tr>
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<tr><td>MCU firmware commit</td><td></td><td>FPGA bitstream / probes tag</td><td></td></tr>
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<tr><td>Power supply setup</td><td></td><td>Ambient temperature</td><td></td></tr>
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</tbody>
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</table>
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</div>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Pre-power checks</h2>
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<div class="table-wrap">
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<table>
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<thead>
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<tr>
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<th>Check</th>
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<th>Expected evidence</th>
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<th>Status</th>
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<th>Notes</th>
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</tr>
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</thead>
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<tbody>
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<tr><td>Carrier jumpers / default straps reviewed</td><td>Documented against board notes</td><td></td><td></td></tr>
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<tr><td>Module seating and connectors inspected</td><td>No bent pins, no obvious shorts, no cable strain</td><td></td><td></td></tr>
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<tr><td>RF transmit path kept disabled for initial power-up</td><td>Safe GPIO / supply state confirmed</td><td></td><td></td></tr>
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<tr><td>Chosen image set identified</td><td>Heartbeat, debug, or baseline image selected intentionally</td><td></td><td></td></tr>
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</tbody>
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</table>
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</div>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Power and configuration checks</h2>
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<div class="table-wrap">
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<table>
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<thead>
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<tr>
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<th>Step</th>
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<th>Expected evidence</th>
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<th>Status</th>
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<th>Notes</th>
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</tr>
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</thead>
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<tbody>
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<tr><td>Initial power applied</td><td>Idle current within planned envelope, no thermal surprise</td><td></td><td></td></tr>
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<tr><td>JTAG enumeration</td><td>Target device visible in hardware manager</td><td></td><td></td></tr>
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<tr><td>Bitstream programming</td><td>DONE = HIGH, INIT_COMPLETE = asserted</td><td></td><td></td></tr>
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<tr><td>Optional probes load</td><td>Expected ILA cores enumerate</td><td></td><td></td></tr>
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<tr><td>Reset / heartbeat sanity</td><td>Deterministic reset release and status activity</td><td></td><td></td></tr>
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</tbody>
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</table>
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</div>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Firmware and control-path checks</h2>
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<div class="table-wrap">
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<table>
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<thead>
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<tr>
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<th>Check</th>
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<th>Expected evidence</th>
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<th>Status</th>
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<th>Notes</th>
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</tr>
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</thead>
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<tbody>
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<tr><td>USART3 bring-up log</td><td>Boot messages present with timestamps</td><td></td><td></td></tr>
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<tr><td>AD9523 status</td><td>Status pins/logs indicate healthy clocking</td><td></td><td></td></tr>
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<tr><td>ADF4382A TX/RX init</td><td>Initialization returns OK, lock states sensible</td><td></td><td></td></tr>
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<tr><td>ADAR1000 communication</td><td>Scratchpad/readback passes on all devices</td><td></td><td></td></tr>
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<tr><td>Temperature / health checks</td><td>No early overtemp, fault, or emergency shutdown</td><td></td><td></td></tr>
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</tbody>
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</table>
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</div>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>FPGA data-path and USB checks</h2>
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<div class="table-wrap">
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<table>
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<thead>
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<tr>
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<th>Stage</th>
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<th>Expected evidence</th>
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<th>Status</th>
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<th>Notes</th>
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</tr>
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</thead>
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<tbody>
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<tr><td>Raw ADC visibility</td><td>ILA or status evidence shows activity on expected clock</td><td></td><td></td></tr>
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<tr><td>DDC / matched-filter activity</td><td>Valid strobes and non-flat outputs observed</td><td></td><td></td></tr>
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<tr><td>USB framing sanity</td><td>Headers, payload length, and footer remain consistent</td><td></td><td></td></tr>
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<tr><td>FT601 behavior</td><td>No obvious backpressure or bus-direction anomalies</td><td></td><td></td></tr>
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<tr><td>Sustained streaming trial</td><td>No immediate lockup, framing drift, or reset event</td><td></td><td></td></tr>
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</tbody>
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</table>
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</div>
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</section>
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<section class="grid-2" style="margin-top:0.8rem;">
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<article class="card">
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<h2>Measurements to record</h2>
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<div class="table-wrap">
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<table>
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<thead>
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<tr>
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<th>Measurement</th>
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<th>Observed value</th>
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<th>Notes</th>
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</tr>
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</thead>
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<tbody>
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<tr><td>Carrier/module idle current</td><td></td><td></td></tr>
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<tr><td>5V / 3V3 rails</td><td></td><td></td></tr>
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<tr><td>LO lock indicators</td><td></td><td></td></tr>
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<tr><td>ADAR temperatures</td><td></td><td></td></tr>
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<tr><td>PA IDQ spot checks</td><td></td><td></td></tr>
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<tr><td>USB enumeration / throughput notes</td><td></td><td></td></tr>
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</tbody>
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</table>
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</div>
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</article>
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<article class="card">
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<h2>Stop conditions encountered?</h2>
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<div class="table-wrap">
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<table>
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<thead>
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<tr>
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<th>Condition</th>
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<th>Triggered</th>
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<th>Notes</th>
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</tr>
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</thead>
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<tbody>
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<tr><td>Unexpected current or thermal rise</td><td></td><td></td></tr>
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<tr><td>LO lock/readback disagreement</td><td></td><td></td></tr>
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<tr><td>ADAR comm failure</td><td></td><td></td></tr>
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<tr><td>USB framing or bus-direction anomaly</td><td></td><td></td></tr>
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<tr><td>Reset / clock ambiguity</td><td></td><td></td></tr>
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<tr><td>Other blocker</td><td></td><td></td></tr>
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</tbody>
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</table>
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</div>
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</article>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Outcome</h2>
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<div class="table-wrap">
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<table>
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<tbody>
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<tr><td>Session result</td><td></td><td>Next image to use</td><td></td></tr>
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<tr><td>Main blocker</td><td colspan="3"></td></tr>
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<tr><td>Next action owner</td><td></td><td>Target completion</td><td></td></tr>
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</tbody>
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</table>
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</div>
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</section>
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</main>
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<footer class="footer">
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<div class="container"><p>Use this worksheet together with the bring-up plan and artifact inventory so observations are captured consistently.</p></div>
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</footer>
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</body>
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</html>
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<p class="eyebrow">Execution Checklist</p>
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<p class="eyebrow">Execution Checklist</p>
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<h1>Hardware Bring-Up Plan</h1>
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<h1>Hardware Bring-Up Plan</h1>
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<p>Pre-arrival completeness gates, board-day smoke tests, and fault-localization rules for the first FPGA module and carrier-board sessions.</p>
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<p>Pre-arrival completeness gates, board-day smoke tests, and fault-localization rules for the first FPGA module and carrier-board sessions.</p>
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<div class="cta-row">
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<a class="button" href="board-day-worksheet.html">Open Board-Day Worksheet</a>
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<a class="button ghost" href="reports.html">Open Artifact Inventory</a>
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</div>
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</section>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<section class="card" style="margin-top:0.8rem;">
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<li>Regression evidence for the tracked branch: MCU host suite and FPGA regression/integration suite.</li>
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<li>Regression evidence for the tracked branch: MCU host suite and FPGA regression/integration suite.</li>
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<li>Day-0 measurement sheet covering supply currents, temperatures, and observed status outputs.</li>
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<li>Day-0 measurement sheet covering supply currents, temperatures, and observed status outputs.</li>
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</ul>
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</ul>
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<p><a class="button ghost" href="reports.html">View concrete artifact inventory</a></p>
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</article>
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</article>
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<article class="card">
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<article class="card">
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<h2>Host-side tools and workflows</h2>
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<h2>Host-side tools and workflows</h2>
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<li>ILA capture workflow for raw ADC, DDC, matched-filter, and USB-domain checkpoints.</li>
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<li>ILA capture workflow for raw ADC, DDC, matched-filter, and USB-domain checkpoints.</li>
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<li>Repeatable checklist for baseline image, debug image, and rollback image selection.</li>
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<li>Repeatable checklist for baseline image, debug image, and rollback image selection.</li>
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</ul>
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</ul>
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<p><a class="button ghost" href="board-day-worksheet.html">Open printable worksheet</a></p>
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</article>
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</article>
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</section>
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</section>
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+32
-1
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<section class="hero">
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<section class="hero">
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<p class="eyebrow">Artifacts</p>
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<p class="eyebrow">Artifacts</p>
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<h1>Published Reports and Visuals</h1>
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<h1>Published Reports and Visuals</h1>
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<p>Central access point for antenna simulations, implementation summaries, timing baselines, and visuals.</p>
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<p>Central access point for antenna simulations, implementation summaries, timing baselines, and board-day artifact references.</p>
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<div class="cta-row">
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<a class="button" href="board-day-worksheet.html">Open Board-Day Worksheet</a>
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<a class="button ghost" href="bring-up.html">Open Bring-Up Plan</a>
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</div>
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</section>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<section class="card" style="margin-top:0.8rem;">
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</ul>
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</ul>
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</section>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Board-day artifact inventory</h2>
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<div class="table-wrap">
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<table>
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<thead>
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<tr>
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<th>Artifact</th>
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<th>Source path</th>
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<th>Day-0 use</th>
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<th>Status / note</th>
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</tr>
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</thead>
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<tbody>
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<tr><td>Production-target XDC</td><td><code>9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc</code></td><td>Constraint source of truth for the production FPGA target</td><td>Tracked and validated after Build 16 cleanup port</td></tr>
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<tr><td>FPGA programming flow</td><td><code>9_Firmware/9_2_FPGA/scripts/program_fpga.tcl</code></td><td>Programs the device and reports DONE / INIT_COMPLETE / probes presence</td><td>Primary operator-facing programming script</td></tr>
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<tr><td>Debug probe insertion flow</td><td><code>9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl</code></td><td>Used when generating or refreshing debug-capable images</td><td>Keep matched with the selected debug bitstream</td></tr>
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<tr><td>FPGA regression runner</td><td><code>9_Firmware/9_2_FPGA/run_regression.sh</code></td><td>Pre-arrival regression evidence for the tracked FPGA baseline</td><td>18 / 18 passing on the current tracked branch</td></tr>
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<tr><td>MCU regression harness</td><td><code>9_Firmware/9_1_Microcontroller/tests/Makefile</code></td><td>Pre-arrival firmware regression evidence before flashing hardware</td><td>15 / 15 passing on the current tracked branch</td></tr>
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<tr><td>Bring-up logging macros</td><td><code>9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h</code></td><td>Defines the main first-power-on log vocabulary used over USART3</td><td>Observation-only instrumentation layer</td></tr>
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<tr><td>Board-day worksheet</td><td><code>docs/board-day-worksheet.html</code></td><td>Record pass/fail, measurements, and blockers during first sessions</td><td>Use with this page and the bring-up plan</td></tr>
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<tr><td>Bring-up execution plan</td><td><code>docs/bring-up.html</code></td><td>Operator checklist, abort criteria, observability targets, and open risks</td><td>Primary readiness document</td></tr>
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</tbody>
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</table>
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</div>
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</section>
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<section class="grid-2" style="margin-top:0.8rem;">
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<section class="grid-2" style="margin-top:0.8rem;">
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<article class="card">
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<article class="card">
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<h2>Antenna Simulation Report</h2>
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<h2>Antenna Simulation Report</h2>
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<li>The current routed production-target baseline is Build 15, with Build 16 used as a remote-only XDC cleanup validation pass.</li>
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<li>The current routed production-target baseline is Build 15, with Build 16 used as a remote-only XDC cleanup validation pass.</li>
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<li>The latest public simulation PDF should be interpreted alongside the implementation log and release notes for the most accurate state of firmware bug closure and FPGA integration readiness.</li>
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<li>The latest public simulation PDF should be interpreted alongside the implementation log and release notes for the most accurate state of firmware bug closure and FPGA integration readiness.</li>
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<li>Detailed Build 15 and Build 16 engineering notes currently live in internal working reports and remote Vivado artifacts rather than this public docs directory.</li>
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<li>Detailed Build 15 and Build 16 engineering notes currently live in internal working reports and remote Vivado artifacts rather than this public docs directory.</li>
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<li>The artifact inventory above is intended to stabilize day-0 execution even when the detailed internal engineering reports stay outside the public docs site.</li>
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</ul>
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</ul>
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</section>
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</section>
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Reference in New Issue
Block a user