From f16d9524e5d6b64df0c4c9117cc8e07895c23bbb Mon Sep 17 00:00:00 2001 From: Jason <83615043+JJassonn69@users.noreply.github.com> Date: Thu, 19 Mar 2026 15:25:23 +0200 Subject: [PATCH] Add board-day worksheet and cross-link bring-up docs --- docs/board-day-worksheet.html | 204 ++++++++++++++++++++++++++++++++++ docs/bring-up.html | 6 + docs/reports.html | 33 +++++- 3 files changed, 242 insertions(+), 1 deletion(-) create mode 100644 docs/board-day-worksheet.html diff --git a/docs/board-day-worksheet.html b/docs/board-day-worksheet.html new file mode 100644 index 0000000..dfc7ed9 --- /dev/null +++ b/docs/board-day-worksheet.html @@ -0,0 +1,204 @@ + + + + + + AERIS-10 Docs | Board-Day Worksheet + + + +
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Board-Day Execution

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Board-Day Worksheet

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Printable operator worksheet for the first FPGA module and carrier-board sessions. Use this alongside the bring-up plan and artifact inventory to capture evidence, pass/fail state, and blockers in real time.

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+ Open Bring-Up Plan + Open Artifact Inventory +
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Session metadata

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Date / TimeOperator
Carrier board revisionFPGA module revision
MCU firmware commitFPGA bitstream / probes tag
Power supply setupAmbient temperature
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Pre-power checks

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CheckExpected evidenceStatusNotes
Carrier jumpers / default straps reviewedDocumented against board notes
Module seating and connectors inspectedNo bent pins, no obvious shorts, no cable strain
RF transmit path kept disabled for initial power-upSafe GPIO / supply state confirmed
Chosen image set identifiedHeartbeat, debug, or baseline image selected intentionally
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Power and configuration checks

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StepExpected evidenceStatusNotes
Initial power appliedIdle current within planned envelope, no thermal surprise
JTAG enumerationTarget device visible in hardware manager
Bitstream programmingDONE = HIGH, INIT_COMPLETE = asserted
Optional probes loadExpected ILA cores enumerate
Reset / heartbeat sanityDeterministic reset release and status activity
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Firmware and control-path checks

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CheckExpected evidenceStatusNotes
USART3 bring-up logBoot messages present with timestamps
AD9523 statusStatus pins/logs indicate healthy clocking
ADF4382A TX/RX initInitialization returns OK, lock states sensible
ADAR1000 communicationScratchpad/readback passes on all devices
Temperature / health checksNo early overtemp, fault, or emergency shutdown
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FPGA data-path and USB checks

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StageExpected evidenceStatusNotes
Raw ADC visibilityILA or status evidence shows activity on expected clock
DDC / matched-filter activityValid strobes and non-flat outputs observed
USB framing sanityHeaders, payload length, and footer remain consistent
FT601 behaviorNo obvious backpressure or bus-direction anomalies
Sustained streaming trialNo immediate lockup, framing drift, or reset event
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Measurements to record

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MeasurementObserved valueNotes
Carrier/module idle current
5V / 3V3 rails
LO lock indicators
ADAR temperatures
PA IDQ spot checks
USB enumeration / throughput notes
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Stop conditions encountered?

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ConditionTriggeredNotes
Unexpected current or thermal rise
LO lock/readback disagreement
ADAR comm failure
USB framing or bus-direction anomaly
Reset / clock ambiguity
Other blocker
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Outcome

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Session resultNext image to use
Main blocker
Next action ownerTarget completion
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Execution Checklist

Hardware Bring-Up Plan

Pre-arrival completeness gates, board-day smoke tests, and fault-localization rules for the first FPGA module and carrier-board sessions.

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  • Regression evidence for the tracked branch: MCU host suite and FPGA regression/integration suite.
  • Day-0 measurement sheet covering supply currents, temperatures, and observed status outputs.
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    View concrete artifact inventory

    Host-side tools and workflows

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  • ILA capture workflow for raw ADC, DDC, matched-filter, and USB-domain checkpoints.
  • Repeatable checklist for baseline image, debug image, and rollback image selection.
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    Open printable worksheet

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    Artifacts

    Published Reports and Visuals

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    Central access point for antenna simulations, implementation summaries, timing baselines, and visuals.

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    Central access point for antenna simulations, implementation summaries, timing baselines, and board-day artifact references.

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    Board-day artifact inventory

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    ArtifactSource pathDay-0 useStatus / note
    Production-target XDC9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdcConstraint source of truth for the production FPGA targetTracked and validated after Build 16 cleanup port
    FPGA programming flow9_Firmware/9_2_FPGA/scripts/program_fpga.tclPrograms the device and reports DONE / INIT_COMPLETE / probes presencePrimary operator-facing programming script
    Debug probe insertion flow9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tclUsed when generating or refreshing debug-capable imagesKeep matched with the selected debug bitstream
    FPGA regression runner9_Firmware/9_2_FPGA/run_regression.shPre-arrival regression evidence for the tracked FPGA baseline18 / 18 passing on the current tracked branch
    MCU regression harness9_Firmware/9_1_Microcontroller/tests/MakefilePre-arrival firmware regression evidence before flashing hardware15 / 15 passing on the current tracked branch
    Bring-up logging macros9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.hDefines the main first-power-on log vocabulary used over USART3Observation-only instrumentation layer
    Board-day worksheetdocs/board-day-worksheet.htmlRecord pass/fail, measurements, and blockers during first sessionsUse with this page and the bring-up plan
    Bring-up execution plandocs/bring-up.htmlOperator checklist, abort criteria, observability targets, and open risksPrimary readiness document
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    Antenna Simulation Report

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  • The current routed production-target baseline is Build 15, with Build 16 used as a remote-only XDC cleanup validation pass.
  • The latest public simulation PDF should be interpreted alongside the implementation log and release notes for the most accurate state of firmware bug closure and FPGA integration readiness.
  • Detailed Build 15 and Build 16 engineering notes currently live in internal working reports and remote Vivado artifacts rather than this public docs directory.
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  • The artifact inventory above is intended to stabilize day-0 execution even when the detailed internal engineering reports stay outside the public docs site.