Port validated Build 16 XDC cleanup and sync docs
This commit is contained in:
Jason
@@ -525,12 +525,14 @@ set_input_delay -clock [get_clocks ft601_clk_in] -min 1.000 [get_ports {ft601_sw
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# output_delay_max = Tsu + trace_skew = 2.0 + 0.5 = 2.5 ns
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# output_delay_min = -(Th - trace_skew) = -(1.5 - 0.5) = -1.0 ns
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create_generated_clock -name dac_clk_fwd \
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-source [get_pins -hierarchical -filter {NAME =~ *oddr_dac_clk/C}] \
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-source [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hierarchical *oddr_dac_clk]] \
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-divide_by 1 \
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[get_ports {dac_clk}]
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set_output_delay -clock [get_clocks dac_clk_fwd] -max 2.500 [get_ports {dac_data[*]}]
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set_output_delay -clock [get_clocks dac_clk_fwd] -min -1.000 [get_ports {dac_data[*]}]
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set_output_delay -clock [get_clocks dac_clk_fwd] -clock_fall -add_delay -max 2.500 [get_ports {dac_data[*]}]
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set_output_delay -clock [get_clocks dac_clk_fwd] -clock_fall -add_delay -min -1.000 [get_ports {dac_data[*]}]
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# Hold analysis for ODDR source-synchronous outputs is inherently safe:
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# both data ODDR and clock ODDR are driven by the same BUFG, so insertion
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@@ -555,7 +557,7 @@ set_false_path -hold -from [get_clocks clk_120m_dac] -to [get_clocks dac_clk_fwd
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# output_delay_max = Tsu + trace_skew = 3.0 + 0.5 = 3.5 ns
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# output_delay_min = -(Th - trace_skew) = -(0.5 - 0.5) = 0.0 ns
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create_generated_clock -name ft601_clk_fwd \
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-source [get_pins -hierarchical -filter {NAME =~ *oddr_ft601_clk/C}] \
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-source [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hierarchical *oddr_ft601_clk]] \
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-divide_by 1 \
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[get_ports {ft601_clk_out}]
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@@ -609,6 +611,7 @@ set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_100m]
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# clk_100m ↔ ft601_clk_in: USB data interface has CDC synchronizers
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set_false_path -from [get_clocks clk_100m] -to [get_clocks ft601_clk_in]
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set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_100m]
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set_false_path -from [get_ports {ft601_txe}] -to [all_registers -clock [get_clocks clk_100m]]
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# clk_120m_dac ↔ ft601_clk_in: no direct data path expected
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set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks ft601_clk_in]
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@@ -743,6 +746,20 @@ create_waiver -type CDC -id CDC-11 \
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-to [get_pins -quiet -hierarchical -filter {NAME =~ *usb_inst/range_valid_sync_reg[0]/D}] \
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-description "doppler_valid CDC fan-out to USB sync chain 2: ASYNC_REG + false_path applied"
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set_false_path -to [get_ports {current_elevation[*]}]
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set_false_path -to [get_ports {current_azimuth[*]}]
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set_false_path -to [get_ports {current_chirp[*]}]
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set_false_path -to [get_ports {new_chirp_frame}]
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set_false_path -to [get_ports {system_status[*]}]
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set_false_path -to [get_ports {dbg_doppler_data[*]}]
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set_false_path -to [get_ports {dbg_doppler_valid}]
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set_false_path -to [get_ports {dbg_doppler_bin[*]}]
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set_false_path -to [get_ports {dbg_range_bin[*]}]
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set_false_path -to [get_ports adar_tr_*]
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set_false_path -to [get_ports {fpga_rf_switch}]
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set_false_path -to [get_ports {rx_mixer_en}]
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set_false_path -to [get_ports {tx_mixer_en}]
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# ============================================================================
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# END OF CONSTRAINTS
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# ============================================================================
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@@ -31,24 +31,28 @@
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<h2>Recent milestone timeline</h2>
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<div class="timeline">
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<article>
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<h3>Build 13 frozen as hardware candidate</h3>
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<p class="muted">WNS +0.311 ns, TNS 0.000, WHS +0.060, THS 0.000 on production target.</p>
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<h3>Build 16 XDC cleanup validated on production target</h3>
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<p class="muted">Remote production XDC pass eliminated XDCB-5 warnings, collapsed the large TIMING-18 bucket to a single ft601_txe residue, and preserved timing at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.</p>
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</article>
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<article>
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<h3>CDC analysis completed with waivers</h3>
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<p class="muted">5 critical warnings verified as false positives and documented as waivers.</p>
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<h3>Build 15 timing-clean integration baseline established</h3>
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<p class="muted">Production-target implementation completed with all timing constraints met after USB range-profile wiring and the CFAR sequential-assignment fix.</p>
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</article>
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<article>
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<h3>ILA insertion flow hardened</h3>
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<p class="muted">Added net discovery pass, deferred core creation, and Vivado 2025.2 MU_CNT handling.</p>
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<h3>USB range profile path wired to matched-filter output</h3>
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<p class="muted">The top-level Doppler placeholder was removed from the USB range-profile path and replaced with the real matched-filter range output propagated through the receiver chain.</p>
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</article>
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<article>
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<h3>Bring-up scripts and bitstreams generated</h3>
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<p class="muted">Baseline + debug bitstreams, programming script, and ILA capture script prepared.</p>
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<h3>Firmware bug sweep closed with regression coverage</h3>
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<p class="muted">All 17 audited MCU firmware bugs were fixed, regression-tested, and pushed, including LO init ordering, SPI chip-select handling, PA calibration logic, TIM3 PWM bring-up, and stale diagnostic mismatches.</p>
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</article>
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<article>
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<h3>Target split for Trenz development path</h3>
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<p class="muted">Added TE0712 and TE0713 separate top wrappers/XDC/build scripts to isolate pinout differences.</p>
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<h3>FPGA timing/resource cleanup phase completed</h3>
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<p class="muted">Chirp BRAM migration, Doppler DSP48 pipelining, CIC pipeline staging, matched-filter regression repair, and full FPGA regression brought the active baseline to 18/18 passing tests.</p>
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</article>
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<article>
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<h3>Build 13 frozen as earlier hardware candidate</h3>
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<p class="muted">Historical milestone retained for traceability: WNS +0.311 ns, TNS 0.000, WHS +0.060, THS 0.000 on the production target before the later DSP and integration work.</p>
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</article>
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</div>
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</section>
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@@ -57,19 +61,19 @@
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<article class="card">
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<h2>Codebase quality and verification upgrades</h2>
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<ul>
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<li>Expanded simulation and co-simulation coverage with golden comparison workflows.</li>
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<li>Formal verification executed across critical modules with passing results.</li>
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<li>Improved reset strategy in key blocks to reduce async-reset related methodology warnings.</li>
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<li>Renamed latency buffer module for maintainability and consistent references.</li>
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<li>Added comprehensive DIAG instrumentation across MCU bring-up, LO, PA, USB, and safety paths before executing the bug-fix phase.</li>
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<li>Built an STM32 HAL/mock regression harness and closed the audited firmware bug list with MCU regression passing.</li>
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<li>Ran full FPGA regression with 18/18 passing suites, including matched filter, Doppler, CIC, CDC, USB, and system-top coverage.</li>
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<li>Migrated the chirp LUT path toward BRAM, added DSP48 and CIC pipeline staging, and validated that the active FPGA baseline still meets timing.</li>
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</ul>
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</article>
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<article class="card">
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<h2>Debug and infrastructure improvements</h2>
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<ul>
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<li>Post-synthesis net-name mapping documented to avoid brittle ILA net paths.</li>
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<li>Generated both no-ILA and ILA debug bitstreams for staged bring-up.</li>
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<li>Added dedicated scripts for TE0712/TE0713 split builds.</li>
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<li>Created community issue to crowdsource compatible hardware test execution.</li>
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<li>Completed Build 15 production-target analysis with timing, power, route, DRC, methodology, and CDC evidence captured in the internal engineering reports.</li>
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<li>Validated a remote-only Build 16 XDC cleanup pass that removed XDCB-5, reduced TIMING-18 to a single ft601_txe methodology residue, and preserved post-route timing.</li>
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<li>Kept separate Trenz development targets while prioritizing the in-stock TE0713 path for practical hardware execution.</li>
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<li>Preserved remote Vivado baselines so timing-clean builds can be compared before and after constraint-only experiments.</li>
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</ul>
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</article>
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</section>
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+45
-24
@@ -40,49 +40,70 @@
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</thead>
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<tbody>
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<tr>
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<td><code>f6877aa</code></td>
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<td>Phase 1 hardware bring-up prep</td>
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<td>Added ILA/debug constraints, CDC waivers, and programming/capture scripts for hardware readiness.</td>
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<td><code>2763b4b</code></td>
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<td>CFAR sequential fix and Build 15 analysis capture</td>
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<td>Replaced the clocked-block CFAR blocking assignment with sequential logic and published the Build 15 timing/DRC/methodology analysis baseline.</td>
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</tr>
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<tr>
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<td><code>12e63b7</code></td>
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<td>ILA insertion script hardening</td>
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<td>Fixed deferred core creation, exact-path resolution, and Vivado 2025.2 MU_CNT handling.</td>
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<td><code>3fa26c9</code></td>
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<td>USB range profile wiring completed</td>
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<td>Removed the Doppler placeholder from the USB range path and propagated real matched-filter range data through the receiver/top-level interfaces.</td>
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</tr>
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<tr>
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<td><code>0ae7b40</code></td>
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<td>TE0712/TE0701 split target</td>
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<td>Introduced dedicated dev top, XDC, and build flow to isolate carrier-board pinout from production target.</td>
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<td><code>f4ff271</code></td>
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<td>Matched-filter regression repair</td>
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<td>Corrected golden-case <code>$readmemh</code> paths so the matched-filter regression returned to 40/40 passing.</td>
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</tr>
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<tr>
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<td><code>967ce17</code></td>
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<td>TE0713/TE0701 alternate target</td>
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<td>Added in-stock SoM path with TE0713-specific constraints and build automation.</td>
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<td><code>463ebef</code></td>
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<td>CIC pipeline staging and regression runner</td>
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<td>Added CIC comb pipeline staging, simulation guards, and an FPGA regression runner to preserve timing while tightening verification.</td>
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</tr>
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<tr>
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<td><code>fcdd270</code></td>
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<td>Initial GitHub Pages publication</td>
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<td>Published antenna and Python simulation PDFs with static site entry point and <code>.nojekyll</code> fix.</td>
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<td><code>c466021</code></td>
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<td>Firmware bug sweep closure (B12-B17)</td>
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<td>Closed the PA calibration, ADC buffer, DIAG macro, TIM3 PWM, and stale-diagnostic issues with additional MCU regression coverage.</td>
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</tr>
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<tr>
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<td><code>94eed1e</code></td>
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<td>Full docs website expansion</td>
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<td>Introduced multi-page engineering documentation site with architecture, bring-up, implementation, and reports pages.</td>
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<td><code>49c9aa2</code></td>
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<td>SPI platform fix plus FPGA B2/B3 timing work</td>
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<td>Fixed the legacy platform SPI transmit-only path and landed chirp BRAM migration plus Doppler DSP48 pipelining work.</td>
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</tr>
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<tr>
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<td><code>3b32f67</code></td>
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<td>ADF4382A SPI and chip-select correctness</td>
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<td>Fixed platform SPI ops wiring, added software-managed CS behavior, and widened SPI chip-select storage to handle STM32 pin values correctly.</td>
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</tr>
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<tr>
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<td><code>3979693</code></td>
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<td>Initial 8-firmware-bug closure with tests</td>
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<td>Closed the LO init ordering, AD9523 sequencing, sync trigger, temperature timer, GPIO mapping, and related MCU issues with regression coverage.</td>
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</tr>
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</tbody>
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</table>
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</div>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Uncommitted validated work</h2>
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<ul>
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<li>Build 16 remote production-XDC cleanup has been validated in the remote Vivado workspace but is not yet represented by a git commit.</li>
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<li>The remote-only pass removed XDCB-5 warnings, reduced the large TIMING-18 bucket to a single <code>ft601_txe</code> methodology residue, and preserved timing at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.</li>
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<li>The surviving <code>ft601_txe</code> item currently behaves like a methodology residue on an async status-observation path rather than a proven unconstrained functional FT601 interface.</li>
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</ul>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Open in GitHub</h2>
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<ul>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/f6877aa" target="_blank" rel="noopener">f6877aa</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/12e63b7" target="_blank" rel="noopener">12e63b7</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/0ae7b40" target="_blank" rel="noopener">0ae7b40</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/967ce17" target="_blank" rel="noopener">967ce17</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/fcdd270" target="_blank" rel="noopener">fcdd270</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/94eed1e" target="_blank" rel="noopener">94eed1e</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/2763b4b" target="_blank" rel="noopener">2763b4b</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3fa26c9" target="_blank" rel="noopener">3fa26c9</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/f4ff271" target="_blank" rel="noopener">f4ff271</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/463ebef" target="_blank" rel="noopener">463ebef</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c466021" target="_blank" rel="noopener">c466021</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/49c9aa2" target="_blank" rel="noopener">49c9aa2</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3b32f67" target="_blank" rel="noopener">3b32f67</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3979693" target="_blank" rel="noopener">3979693</a></li>
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</ul>
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</section>
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</main>
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+21
-5
@@ -24,7 +24,16 @@
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<section class="hero">
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<p class="eyebrow">Artifacts</p>
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<h1>Published Reports and Visuals</h1>
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<p>Central access point for antenna simulations, Python simulation outputs, and visuals.</p>
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<p>Central access point for antenna simulations, implementation summaries, timing baselines, and visuals.</p>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Current FPGA implementation status</h2>
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<ul>
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<li>Build 15 is the current detailed analysis baseline for the production XC7A200T target and completed with all timing constraints met.</li>
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<li>Build 16 was validated in the remote Vivado workspace as a constraint-cleanup pass: XDCB-5 warnings were removed, the large TIMING-18 bucket collapsed to a single <code>ft601_txe</code> methodology residue, and routed timing remained clean at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.</li>
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<li>The remaining <code>ft601_txe</code> methodology item currently behaves like an async-status-observation residue rather than a proven unconstrained functional FT601 path.</li>
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</ul>
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</section>
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<section class="grid-2" style="margin-top:0.8rem;">
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@@ -50,11 +59,18 @@
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</article>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>FPGA implementation analysis</h2>
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<p><span class="chip">Status: Current engineering baseline</span></p>
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<p class="muted">Primary detailed write-up: internal Build 15 implementation analysis captured timing, power, route status, DRC, methodology, CDC, and utilization for the production-target design after USB range wiring and CFAR cleanup.</p>
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<p class="muted">Follow-on Build 16 remote validation focused on production XDC cleanup only and confirmed no timing regression while reducing methodology noise substantially.</p>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Latest Simulation Report (Recommended)</h2>
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<p><span class="chip">Status: Current baseline (v2)</span></p>
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<p class="muted">File: <code>AERIS_Simulation_Report_v2.pdf</code></p>
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<p class="muted">Aligned to current project baseline: XC7A200T target, Build 13 freeze, regression/timing/CDC gates, ILA readiness, and TE0712/TE0713 split-target flow.</p>
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<p class="muted">Aligned to the active project baseline: XC7A200T target, firmware regression closure, FPGA regression/timing gates, USB range-profile integration, and TE0712/TE0713 split-target flow.</p>
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<p>
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<a class="button" href="AERIS_Simulation_Report_v2.pdf" target="_blank" rel="noopener">Open PDF</a>
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<a class="button ghost" href="AERIS_Simulation_Report_v2.pdf" download>Download</a>
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||||
@@ -64,9 +80,9 @@
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<section class="card" style="margin-top:0.8rem;">
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<h2>Report Currency Notice</h2>
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<ul>
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<li>Current implementation baseline is Build 13 on XC7A200T with full regression/timing closure campaign completed.</li>
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<li>The simulation PDF currently published predates part of this migration and should not be treated as the latest hardware-equivalent verification record.</li>
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<li>A revised Simulation Report v2 should align with current FPGA target, test coverage, and TE0712/TE0713 bring-up split flow.</li>
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<li>The current routed production-target baseline is Build 15, with Build 16 used as a remote-only XDC cleanup validation pass.</li>
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<li>The latest public simulation PDF should be interpreted alongside the implementation log and release notes for the most accurate state of firmware bug closure and FPGA integration readiness.</li>
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<li>Detailed Build 15 and Build 16 engineering notes currently live in internal working reports and remote Vivado artifacts rather than this public docs directory.</li>
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</ul>
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</section>
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