diff --git a/9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc b/9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc index 0f995c3..1185c2e 100644 --- a/9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc +++ b/9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc @@ -525,12 +525,14 @@ set_input_delay -clock [get_clocks ft601_clk_in] -min 1.000 [get_ports {ft601_sw # output_delay_max = Tsu + trace_skew = 2.0 + 0.5 = 2.5 ns # output_delay_min = -(Th - trace_skew) = -(1.5 - 0.5) = -1.0 ns create_generated_clock -name dac_clk_fwd \ - -source [get_pins -hierarchical -filter {NAME =~ *oddr_dac_clk/C}] \ + -source [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hierarchical *oddr_dac_clk]] \ -divide_by 1 \ [get_ports {dac_clk}] set_output_delay -clock [get_clocks dac_clk_fwd] -max 2.500 [get_ports {dac_data[*]}] set_output_delay -clock [get_clocks dac_clk_fwd] -min -1.000 [get_ports {dac_data[*]}] +set_output_delay -clock [get_clocks dac_clk_fwd] -clock_fall -add_delay -max 2.500 [get_ports {dac_data[*]}] +set_output_delay -clock [get_clocks dac_clk_fwd] -clock_fall -add_delay -min -1.000 [get_ports {dac_data[*]}] # Hold analysis for ODDR source-synchronous outputs is inherently safe: # both data ODDR and clock ODDR are driven by the same BUFG, so insertion @@ -555,7 +557,7 @@ set_false_path -hold -from [get_clocks clk_120m_dac] -to [get_clocks dac_clk_fwd # output_delay_max = Tsu + trace_skew = 3.0 + 0.5 = 3.5 ns # output_delay_min = -(Th - trace_skew) = -(0.5 - 0.5) = 0.0 ns create_generated_clock -name ft601_clk_fwd \ - -source [get_pins -hierarchical -filter {NAME =~ *oddr_ft601_clk/C}] \ + -source [get_pins -filter {REF_PIN_NAME =~ C} -of_objects [get_cells -hierarchical *oddr_ft601_clk]] \ -divide_by 1 \ [get_ports {ft601_clk_out}] @@ -609,6 +611,7 @@ set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_100m] # clk_100m ↔ ft601_clk_in: USB data interface has CDC synchronizers set_false_path -from [get_clocks clk_100m] -to [get_clocks ft601_clk_in] set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_100m] +set_false_path -from [get_ports {ft601_txe}] -to [all_registers -clock [get_clocks clk_100m]] # clk_120m_dac ↔ ft601_clk_in: no direct data path expected set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks ft601_clk_in] @@ -743,6 +746,20 @@ create_waiver -type CDC -id CDC-11 \ -to [get_pins -quiet -hierarchical -filter {NAME =~ *usb_inst/range_valid_sync_reg[0]/D}] \ -description "doppler_valid CDC fan-out to USB sync chain 2: ASYNC_REG + false_path applied" +set_false_path -to [get_ports {current_elevation[*]}] +set_false_path -to [get_ports {current_azimuth[*]}] +set_false_path -to [get_ports {current_chirp[*]}] +set_false_path -to [get_ports {new_chirp_frame}] +set_false_path -to [get_ports {system_status[*]}] +set_false_path -to [get_ports {dbg_doppler_data[*]}] +set_false_path -to [get_ports {dbg_doppler_valid}] +set_false_path -to [get_ports {dbg_doppler_bin[*]}] +set_false_path -to [get_ports {dbg_range_bin[*]}] +set_false_path -to [get_ports adar_tr_*] +set_false_path -to [get_ports {fpga_rf_switch}] +set_false_path -to [get_ports {rx_mixer_en}] +set_false_path -to [get_ports {tx_mixer_en}] + # ============================================================================ # END OF CONSTRAINTS # ============================================================================ diff --git a/docs/implementation-log.html b/docs/implementation-log.html index 3e3e504..c0bff69 100644 --- a/docs/implementation-log.html +++ b/docs/implementation-log.html @@ -31,24 +31,28 @@

Recent milestone timeline

-

Build 13 frozen as hardware candidate

-

WNS +0.311 ns, TNS 0.000, WHS +0.060, THS 0.000 on production target.

+

Build 16 XDC cleanup validated on production target

+

Remote production XDC pass eliminated XDCB-5 warnings, collapsed the large TIMING-18 bucket to a single ft601_txe residue, and preserved timing at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.

-

CDC analysis completed with waivers

-

5 critical warnings verified as false positives and documented as waivers.

+

Build 15 timing-clean integration baseline established

+

Production-target implementation completed with all timing constraints met after USB range-profile wiring and the CFAR sequential-assignment fix.

-

ILA insertion flow hardened

-

Added net discovery pass, deferred core creation, and Vivado 2025.2 MU_CNT handling.

+

USB range profile path wired to matched-filter output

+

The top-level Doppler placeholder was removed from the USB range-profile path and replaced with the real matched-filter range output propagated through the receiver chain.

-

Bring-up scripts and bitstreams generated

-

Baseline + debug bitstreams, programming script, and ILA capture script prepared.

+

Firmware bug sweep closed with regression coverage

+

All 17 audited MCU firmware bugs were fixed, regression-tested, and pushed, including LO init ordering, SPI chip-select handling, PA calibration logic, TIM3 PWM bring-up, and stale diagnostic mismatches.

-

Target split for Trenz development path

-

Added TE0712 and TE0713 separate top wrappers/XDC/build scripts to isolate pinout differences.

+

FPGA timing/resource cleanup phase completed

+

Chirp BRAM migration, Doppler DSP48 pipelining, CIC pipeline staging, matched-filter regression repair, and full FPGA regression brought the active baseline to 18/18 passing tests.

+
+
+

Build 13 frozen as earlier hardware candidate

+

Historical milestone retained for traceability: WNS +0.311 ns, TNS 0.000, WHS +0.060, THS 0.000 on the production target before the later DSP and integration work.

@@ -57,19 +61,19 @@

Codebase quality and verification upgrades

Debug and infrastructure improvements

diff --git a/docs/release-notes.html b/docs/release-notes.html index 26297c7..a618776 100644 --- a/docs/release-notes.html +++ b/docs/release-notes.html @@ -40,49 +40,70 @@ - f6877aa - Phase 1 hardware bring-up prep - Added ILA/debug constraints, CDC waivers, and programming/capture scripts for hardware readiness. + 2763b4b + CFAR sequential fix and Build 15 analysis capture + Replaced the clocked-block CFAR blocking assignment with sequential logic and published the Build 15 timing/DRC/methodology analysis baseline. - 12e63b7 - ILA insertion script hardening - Fixed deferred core creation, exact-path resolution, and Vivado 2025.2 MU_CNT handling. + 3fa26c9 + USB range profile wiring completed + Removed the Doppler placeholder from the USB range path and propagated real matched-filter range data through the receiver/top-level interfaces. - 0ae7b40 - TE0712/TE0701 split target - Introduced dedicated dev top, XDC, and build flow to isolate carrier-board pinout from production target. + f4ff271 + Matched-filter regression repair + Corrected golden-case $readmemh paths so the matched-filter regression returned to 40/40 passing. - 967ce17 - TE0713/TE0701 alternate target - Added in-stock SoM path with TE0713-specific constraints and build automation. + 463ebef + CIC pipeline staging and regression runner + Added CIC comb pipeline staging, simulation guards, and an FPGA regression runner to preserve timing while tightening verification. - fcdd270 - Initial GitHub Pages publication - Published antenna and Python simulation PDFs with static site entry point and .nojekyll fix. + c466021 + Firmware bug sweep closure (B12-B17) + Closed the PA calibration, ADC buffer, DIAG macro, TIM3 PWM, and stale-diagnostic issues with additional MCU regression coverage. - 94eed1e - Full docs website expansion - Introduced multi-page engineering documentation site with architecture, bring-up, implementation, and reports pages. + 49c9aa2 + SPI platform fix plus FPGA B2/B3 timing work + Fixed the legacy platform SPI transmit-only path and landed chirp BRAM migration plus Doppler DSP48 pipelining work. + + + 3b32f67 + ADF4382A SPI and chip-select correctness + Fixed platform SPI ops wiring, added software-managed CS behavior, and widened SPI chip-select storage to handle STM32 pin values correctly. + + + 3979693 + Initial 8-firmware-bug closure with tests + Closed the LO init ordering, AD9523 sequencing, sync trigger, temperature timer, GPIO mapping, and related MCU issues with regression coverage. +
+

Uncommitted validated work

+ +
+

Open in GitHub

diff --git a/docs/reports.html b/docs/reports.html index d61bf8e..866b734 100644 --- a/docs/reports.html +++ b/docs/reports.html @@ -24,7 +24,16 @@

Artifacts

Published Reports and Visuals

-

Central access point for antenna simulations, Python simulation outputs, and visuals.

+

Central access point for antenna simulations, implementation summaries, timing baselines, and visuals.

+
+ +
+

Current FPGA implementation status

+
@@ -50,11 +59,18 @@
+
+

FPGA implementation analysis

+

Status: Current engineering baseline

+

Primary detailed write-up: internal Build 15 implementation analysis captured timing, power, route status, DRC, methodology, CDC, and utilization for the production-target design after USB range wiring and CFAR cleanup.

+

Follow-on Build 16 remote validation focused on production XDC cleanup only and confirmed no timing regression while reducing methodology noise substantially.

+
+

Latest Simulation Report (Recommended)

Status: Current baseline (v2)

File: AERIS_Simulation_Report_v2.pdf

-

Aligned to current project baseline: XC7A200T target, Build 13 freeze, regression/timing/CDC gates, ILA readiness, and TE0712/TE0713 split-target flow.

+

Aligned to the active project baseline: XC7A200T target, firmware regression closure, FPGA regression/timing gates, USB range-profile integration, and TE0712/TE0713 split-target flow.

Open PDF Download @@ -64,9 +80,9 @@

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