Build 25 engineering report: MTI canceller + DC notch timing PASS

Build 25 results (MTI + DC notch integration):
- WNS +0.132 ns, WHS +0.058 ns (all domains PASS)
- 9,252 LUTs, 12,488 FFs, 17 BRAM, 142 DSP, 0.753 W
- MTI cost: +694 LUTs, +2,104 FFs, 0 BRAM, 0 DSP
- Bitstream: radar_system_top_build25.bit (production-safe)
- 23/23 FPGA regression, 29/29 MTI checks, 3/3 real-data co-sim

Updated reports.html (15-point Build 25 report), implementation-log.html
(timeline entries for production fixes, CFAR, MTI), and release-notes.html
(new tagged releases, gap status update).

docs/implementation-log.html

@@ -31,7 +31,27 @@
       <h2>Recent milestone timeline</h2>
       <div class="timeline">
         <article>
-          <h3>Build 21 tagged v0.1.4-build21 &mdash; new production baseline (2efab23)</h3>
+          <h3>Build 25 &mdash; MTI canceller + DC notch filter (ed629e7)</h3>
+          <p class="muted">MTI 2-pulse canceller (H(z) = 1 - z^{-1}) integrated between range bin decimator and Doppler processor for ground clutter removal. DC notch filter (post-Doppler, pre-CFAR) zeroes bins within &plusmn;host_dc_notch_width of bin 0. Two new host registers: host_mti_enable (0x26), host_dc_notch_width (0x27). Both default to off/pass-through for backward compatibility. Build 25: WNS +0.132 ns, WHS +0.058 ns. 9,252 LUTs, 12,488 FFs, 17 BRAM, 142 DSP, 0.753 W. 23/23 FPGA regression, 29/29 MTI standalone checks, 3/3 real-data co-sim exact match.</p>
+        </article>
+        <article>
+          <h3>Build 24 tagged v0.1.5-cfar &mdash; CA-CFAR production baseline (075ae1e)</h3>
+          <p class="muted">CA-CFAR detector with CA/GO/SO modes integrated, replacing old threshold detector. Pipelined noise computation (Build 23 fix). WNS +0.179 ns, WHS +0.056 ns. 8,558 LUTs, 10,384 FFs, 17 BRAM, 142 DSP, 0.754 W. CFAR cost: +2,229 LUTs, +1,281 FFs, +1 BRAM, +3 DSP. Includes magnitude BRAM buffer, sliding-window algorithm, host-configurable guard/train/alpha/mode registers (opcodes 0x21-0x25).</p>
+        </article>
+        <article>
+          <h3>Build 23 failed timing, root-caused and fixed (0745cc4)</h3>
+          <p class="muted">Build 23 had WNS -0.309 ns due to combinational path through CFAR noise_sum_comb &rarr; cross-multiply &rarr; alpha*noise DSP. Fixed by pipelining noise computation into ST_CFAR_THR + ST_CFAR_MUL stages, splitting the path across two clock cycles.</p>
+        </article>
+        <article>
+          <h3>7 production fixes tagged v0.1.4-prod-fixes (e93bc33)</h3>
+          <p class="muted">Detection bug fixes (sticky flag + one-cycle-lag magnitude), rename cfar&rarr;threshold_detect, digital gain control (host-configurable power-of-2 shift), Doppler/chirps mismatch protection (clamp + error flag), decimator watchdog (timeout counter), bypass_mode dead code removal, range-mode register (0x20). Real-data co-simulation framework added. 22/22 FPGA regression.</p>
+        </article>
+        <article>
+          <h3>Real-data co-simulation framework (0b06436)</h3>
+          <p class="muted">Three real-data testbenches added: range FFT, Doppler, and full-chain. Compare RTL outputs against Python golden reference using recorded ADC captures. 5,137 total data checks, all exact bit-for-bit match. Tagged v0.1.4-pre-fixes as safety net before production fixes.</p>
+        </article>
+        <article>
+          <h3>Build 21 tagged v0.1.4-build21 &mdash; pre-CFAR production baseline (2efab23)</h3>
           <p class="muted">WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns. 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%), 0.732 W. Includes FFT 4-cycle butterfly (20% throughput), barrel-shift twiddle (-1 DSP), Gap 2 GUI Settings, E2E RTL fixes (mixer sequencing, USB data-pending, receiver toggle wiring), Vivado DRC multiple-driver fix for data_pending flags, and MMCM LOCKED XDC false_path correction (-from &rarr; -through). Build script crash at report_exceptions/check_timing (Vivado 2025.2 bug) fixed by wrapping in catch blocks; all 12 critical reports and bitstream generated successfully.</p>
         </article>
         <article>
@@ -85,9 +105,9 @@
       <article class="card">
         <h2>Codebase quality and verification upgrades</h2>
         <ul>
-          <li>FPGA regression: 19/19 passing suites covering matched filter, Doppler, CIC, CDC, USB (with read path), FFT, NCO, FIR, range decimator, mode controller, system-top integration, and system E2E.</li>
+          <li>FPGA regression: 23/23 passing suites covering matched filter, Doppler, CIC, CDC, USB (with read path), FFT, NCO, FIR, range decimator, mode controller, system-top integration, system E2E, CFAR standalone, and MTI standalone.</li>
           <li>MCU regression: 20/20 passing tests (15 bug-fix + 5 Gap-3 safety tests).</li>
-          <li>Architectural gaps 2, 3, 4, 5, 7 closed with full test coverage. Gaps 1 and 6 deferred to post-bring-up.</li>
+          <li>Architectural gaps 1&ndash;7 all closed. Gap 1 (CFAR) integrated as CA-CFAR detector (Build 24). MTI canceller + DC notch filter added (Build 25). Gaps 2&ndash;7 closed prior to Build 21.</li>
           <li>USB host-to-FPGA command path fully wired: read FSM, toggle CDC, command decode for mode/trigger/CFAR/stream control. GUI settings (chirp timing, stream gating, status readback) fully operational.</li>
           <li>Safety architecture: IWDG watchdog, emergency stop PA cutoff, temperature guard, IDQ re-read, state ordering.</li>
         </ul>
@@ -95,7 +115,9 @@
       <article class="card">
         <h2>Build history and timing improvements</h2>
         <ul>
-          <li><strong>Build 21 (v0.1.4-build21)</strong>: Current production baseline. WNS +0.156 ns, WHS +0.064 ns. FFT 4-cycle butterfly + barrel-shift twiddle. 139 DSP48E1 (-1). 0.732 W.</li>
+          <li><strong>Build 25 (v0.1.6-mti)</strong>: Current production baseline. WNS +0.132 ns, WHS +0.058 ns. MTI canceller + DC notch filter. 9,252 LUTs, 12,488 FFs, 142 DSP48E1. 0.753 W.</li>
+          <li><strong>Build 24 (v0.1.5-cfar)</strong>: Prior production baseline. WNS +0.179 ns, WHS +0.056 ns. CA-CFAR detector (CA/GO/SO). 8,558 LUTs, 142 DSP48E1. 0.754 W.</li>
+          <li><strong>Build 21 (v0.1.4-build21)</strong>: Pre-CFAR baseline. WNS +0.156 ns, WHS +0.064 ns. FFT 4-cycle butterfly + barrel-shift twiddle. 139 DSP48E1 (-1). 0.732 W.</li>
           <li><strong>Build 20 (v0.1.3-build20)</strong>: Prior production baseline. WNS +0.426 ns, WHS +0.058 ns. 400 MHz MMCM + CIC CREG pipeline. 0.730 W.</li>
           <li><strong>Build 19</strong>: Failed (WNS -0.011 ns). Root cause: conflicting XDC generated clock prevented false-path application.</li>
           <li><strong>Build 18 (v0.1.2-build18)</strong>: Prior baseline. WNS +0.062 ns, WHS +0.059 ns. 0.631 W.</li>

docs/release-notes.html

@@ -39,6 +39,21 @@
             </tr>
           </thead>
           <tbody>
+            <tr>
+              <td><code>ed629e7</code> <strong>v0.1.6-mti</strong></td>
+              <td>Build 25: MTI canceller + DC notch filter integration</td>
+              <td>New production baseline. WNS +0.132 ns, WHS +0.058 ns. 9,252 LUTs (6.87%), 12,488 FFs (4.64%), 17 BRAM (4.66%), 142 DSP48E1 (19.19%), 0.753 W. New modules: mti_canceller.v (2-pulse canceller, H(z)=1-z^-1), DC notch filter (inline in system_top). Two new host registers: host_mti_enable (0x26), host_dc_notch_width (0x27). 23/23 FPGA, 20/20 MCU, 3/3 real-data co-sim exact match.</td>
+            </tr>
+            <tr>
+              <td><code>075ae1e</code> <strong>v0.1.5-cfar</strong></td>
+              <td>Build 24: CA-CFAR detector integration with pipelined noise computation</td>
+              <td>Prior production baseline. WNS +0.179 ns, WHS +0.056 ns. 8,558 LUTs, 10,384 FFs, 17 BRAM, 142 DSP48E1, 0.754 W. CA/GO/SO CFAR modes with BRAM magnitude buffer, sliding-window algorithm. Host-configurable guard/train/alpha/mode registers (0x21-0x25). Build 23 timing failure fixed by pipelining noise computation. 22/22 FPGA, 20/20 MCU.</td>
+            </tr>
+            <tr>
+              <td><code>e93bc33</code> <strong>v0.1.4-prod-fixes</strong></td>
+              <td>7 production-quality fixes: detection bugs, digital gain, watchdog, dead code removal</td>
+              <td>Detection sticky flag + magnitude lag fix, rename cfar&rarr;threshold_detect, host-configurable digital gain control (power-of-2 shift), Doppler/chirps mismatch protection (clamp + error flag), decimator watchdog timeout, bypass_mode dead code removal, range-mode register (0x20). Real-data co-sim framework added. 22/22 FPGA.</td>
+            </tr>
             <tr>
               <td><code>2efab23</code> <strong>v0.1.4-build21</strong></td>
               <td>Build 21: FFT opts + E2E RTL fixes + Vivado DRC fix + MMCM LOCKED false_path fix</td>
@@ -117,7 +132,10 @@
     <section class="card" style="margin-top:0.8rem;">
       <h2>Tagged releases</h2>
       <ul>
-        <li><strong>v0.1.4-build21</strong> (2efab23) &mdash; Current production baseline. WNS +0.156 ns, WHS +0.064 ns. Includes FFT opts, E2E RTL fixes, Vivado DRC fix, MMCM LOCKED XDC fix. 139 DSP48E1 (-1 vs Build 20).</li>
+        <li><strong>v0.1.6-mti</strong> (ed629e7) &mdash; Current production baseline. WNS +0.132 ns, WHS +0.058 ns. MTI canceller + DC notch filter. 9,252 LUTs, 12,488 FFs, 142 DSP48E1, 17 BRAM. 0.753 W.</li>
+        <li><strong>v0.1.5-cfar</strong> (075ae1e) &mdash; Prior production baseline. WNS +0.179 ns. CA-CFAR detector (CA/GO/SO modes) with pipelined noise computation.</li>
+        <li><strong>v0.1.4-prod-fixes</strong> (e93bc33) &mdash; 7 production fixes + real-data co-sim framework. WNS same as Build 21 (simulation-only changes).</li>
+        <li><strong>v0.1.4-build21</strong> (2efab23) &mdash; Pre-CFAR production baseline. WNS +0.156 ns, WHS +0.064 ns. Includes FFT opts, E2E RTL fixes, Vivado DRC fix, MMCM LOCKED XDC fix. 139 DSP48E1 (-1 vs Build 20).</li>
         <li><strong>v0.1.3-build20</strong> (c6103b3) &mdash; Prior production baseline. WNS +0.426 ns, all timing met. Includes Gaps 3, 5, 7.</li>
         <li><strong>v0.1.2-build18</strong> (3b7afba) &mdash; Prior production baseline. WNS +0.062 ns.</li>
         <li><strong>v0.1.1-build17</strong> (ed6f79c) &mdash; FIR DSP48 + BRAM migration build.</li>
@@ -137,7 +155,7 @@
             <tr><td>4</td><td>USB Read Path</td><td>Done (e5d1b3c)</td></tr>
             <tr><td>2</td><td>GUI Settings</td><td>Done (7cdfa48)</td></tr>
             <tr><td>6</td><td>CDC-15 USB Buses</td><td>Post-bring-up</td></tr>
-            <tr><td>1</td><td>CFAR Real Implementation</td><td>Post-bring-up</td></tr>
+            <tr><td>1</td><td>CFAR Real Implementation</td><td>Done (075ae1e, Build 24 + MTI in ed629e7)</td></tr>
           </tbody>
         </table>
       </div>
@@ -146,6 +164,12 @@
     <section class="card" style="margin-top:0.8rem;">
       <h2>Open in GitHub</h2>
       <ul>
+        <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/ed629e7" target="_blank" rel="noopener">ed629e7</a> MTI canceller + DC notch filter (v0.1.6-mti)</li>
+        <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/075ae1e" target="_blank" rel="noopener">075ae1e</a> Build 24 report (v0.1.5-cfar)</li>
+        <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/0745cc4" target="_blank" rel="noopener">0745cc4</a> Pipeline CFAR noise computation (timing fix)</li>
+        <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/f71923b" target="_blank" rel="noopener">f71923b</a> Integrate CA-CFAR detector</li>
+        <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/e93bc33" target="_blank" rel="noopener">e93bc33</a> Production fixes 1-7 (v0.1.4-prod-fixes)</li>
+        <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/0b06436" target="_blank" rel="noopener">0b06436</a> Real-data co-simulation (v0.1.4-pre-fixes)</li>
         <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/2efab23" target="_blank" rel="noopener">2efab23</a> Build 21: FFT opts + DRC fix + XDC fix (v0.1.4-build21)</li>
         <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/0773001" target="_blank" rel="noopener">0773001</a> E2E test + RTL fixes</li>
         <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/a3e1996" target="_blank" rel="noopener">a3e1996</a> FFT engine optimizations</li>

docs/reports.html

@@ -34,12 +34,228 @@
     <section class="card" style="margin-top:0.8rem;">
       <h2>Current FPGA implementation status</h2>
       <ul>
-        <li><strong>Build 24</strong> is the current production baseline for the XC7A200T target. All timing constraints met. Includes CA-CFAR detector integration with pipelined noise computation.</li>
+        <li><strong>Build 25</strong> is the current production baseline for the XC7A200T target. All timing constraints met. Includes MTI canceller + DC notch filter integration on top of CA-CFAR.</li>
-        <li>Build 24 reports are available on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build24/</code>.</li>
+        <li>Build 25 reports are available on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build25/</code>.</li>
+        <li>Build 24 (v0.1.5-cfar) retained as pre-MTI reference at <code>reports_build24/</code>.</li>
         <li>Build 21 (v0.1.4-build21) retained as pre-CFAR reference at <code>reports_build21/</code>.</li>
       </ul>
     </section>
 
+    <!-- ===== Build 25 — 15-Point Report ===== -->
+    <section class="card" style="margin-top:0.8rem;">
+      <h2>Build 25 &mdash; 15-Point Engineering Report</h2>
+      <p><span class="chip">Status: PASS &mdash; Production-safe bitstream generated</span></p>
+      <p class="muted">Date: 2026-03-20 &nbsp;|&nbsp; Commit: <code>ed629e7</code> &nbsp;|&nbsp; Device: XC7A200T-2FBG484I &nbsp;|&nbsp; Vivado 2025.2</p>
+
+      <!-- 1. Timing -->
+      <h3>1. Timing Summary</h3>
+      <div class="table-wrap">
+        <table>
+          <thead><tr><th>Clock Domain</th><th>Period (ns)</th><th>WNS (ns)</th><th>WHS (ns)</th><th>WPWS (ns)</th><th>Status</th></tr></thead>
+          <tbody>
+            <tr><td>clk_100m</td><td>10.000</td><td>+0.634</td><td>+0.058</td><td>+3.870</td><td>PASS</td></tr>
+            <tr><td>clk_mmcm_out0 (400 MHz)</td><td>2.500</td><td>+0.304</td><td>+0.115</td><td>+0.684</td><td>PASS</td></tr>
+            <tr><td>adc_dco_p</td><td>&mdash;</td><td>+0.904</td><td>&mdash;</td><td>+0.361</td><td>PASS</td></tr>
+            <tr><td>ft601_clk_in</td><td>10.000</td><td>+0.132</td><td>+0.121</td><td>+4.500</td><td>PASS</td></tr>
+            <tr><td>clk_120m_dac</td><td>&mdash;</td><td>+0.773</td><td>+0.151</td><td>+3.666</td><td>PASS</td></tr>
+          </tbody>
+        </table>
+      </div>
+      <p class="muted">TNS = 0.000 ns, THS = 0.000 ns across all domains. Zero failing endpoints. Overall WNS +0.132 ns (ft601_clk_in domain, USB FSM path). Overall WHS +0.058 ns.</p>
+
+      <!-- 2. Utilization -->
+      <h3>2. Utilization (Post-Route)</h3>
+      <div class="table-wrap">
+        <table>
+          <thead><tr><th>Resource</th><th>Build 24 (CFAR)</th><th>Build 25 (MTI)</th><th>Available</th><th>Util%</th><th>Delta</th></tr></thead>
+          <tbody>
+            <tr><td>Slice LUTs</td><td>8,558</td><td>9,252</td><td>134,600</td><td>6.87%</td><td>+694 (+8.1%)</td></tr>
+            <tr><td>Slice Registers (FFs)</td><td>10,384</td><td>12,488</td><td>269,200</td><td>4.64%</td><td>+2,104 (+20%)</td></tr>
+            <tr><td>Block RAM Tiles</td><td>17</td><td>17</td><td>365</td><td>4.66%</td><td>0</td></tr>
+            <tr><td>&nbsp;&nbsp;RAMB36E1</td><td>12</td><td>12</td><td>365</td><td>3.29%</td><td>0</td></tr>
+            <tr><td>&nbsp;&nbsp;RAMB18E1</td><td>10</td><td>10</td><td>730</td><td>1.37%</td><td>0</td></tr>
+            <tr><td>LUT as Distributed RAM</td><td>&mdash;</td><td>48</td><td>46,200</td><td>0.10%</td><td>&mdash;</td></tr>
+            <tr><td>DSP48E1</td><td>142</td><td>142</td><td>740</td><td>19.19%</td><td>0</td></tr>
+            <tr><td>Bonded IOBs</td><td>178</td><td>178</td><td>285</td><td>62.46%</td><td>0</td></tr>
+            <tr><td>BUFGCTRL</td><td>5</td><td>5</td><td>32</td><td>15.63%</td><td>0</td></tr>
+            <tr><td>MMCME2_ADV</td><td>1</td><td>1</td><td>10</td><td>10.00%</td><td>0</td></tr>
+          </tbody>
+        </table>
+      </div>
+      <p class="muted">MTI canceller added +694 LUTs (distributed RAM for chirp delay line + subtraction logic + DC notch comparators) and +2,104 FFs (I/Q pipeline registers, saturation logic, notch width comparators). Zero BRAM and DSP impact &mdash; MTI uses distributed RAM and fabric arithmetic only.</p>
+
+      <!-- 3. DSP48E1 Breakdown -->
+      <h3>3. DSP48E1 Breakdown by Module</h3>
+      <div class="table-wrap">
+        <table>
+          <thead><tr><th>Module</th><th>DSP48E1</th><th>Notes</th></tr></thead>
+          <tbody>
+            <tr><td>DDC (FIR I + FIR Q + CIC + NCO)</td><td>117</td><td>Dominant consumer: 47+47 FIR taps + 10+10 CIC + 2 DDC + 1 NCO</td></tr>
+            <tr><td>Matched Filter Processing Chain</td><td>12</td><td>8 FFT butterflies + 4 freq-domain multiply</td></tr>
+            <tr><td>Doppler Processor + FFT</td><td>10</td><td>8 FFT butterflies + 2 magnitude</td></tr>
+            <tr><td>CFAR Detector</td><td>3</td><td>alpha*noise multiply + GO/SO cross-multiply (pipelined)</td></tr>
+            <tr><td>MTI Canceller</td><td>0</td><td>Pure fabric arithmetic (subtraction + saturation)</td></tr>
+            <tr><td><strong>Total</strong></td><td><strong>142</strong></td><td>19.19% of 740 available</td></tr>
+          </tbody>
+        </table>
+      </div>
+
+      <!-- 4. BRAM Breakdown -->
+      <h3>4. BRAM Breakdown by Module</h3>
+      <div class="table-wrap">
+        <table>
+          <thead><tr><th>Module</th><th>RAMB36</th><th>RAMB18</th><th>Tiles</th><th>Notes</th></tr></thead>
+          <tbody>
+            <tr><td>Doppler Processor</td><td>4</td><td>0</td><td>4</td><td>Range-Doppler accumulation buffers</td></tr>
+            <tr><td>Matched Filter (mf_dual)</td><td>2</td><td>10</td><td>7</td><td>Coefficient + I/Q data BRAMs</td></tr>
+            <tr><td>CFAR Detector</td><td>1</td><td>0</td><td>1</td><td>Magnitude buffer (2048&times;17 bits)</td></tr>
+            <tr><td>Transmitter (chirp mem)</td><td>1</td><td>0</td><td>1</td><td>Chirp waveform storage</td></tr>
+            <tr><td>FFT Engines (2&times;)</td><td>4</td><td>0</td><td>4</td><td>Twiddle factor + butterfly BRAMs</td></tr>
+            <tr><td>MTI Canceller</td><td>0</td><td>0</td><td>0</td><td>Uses distributed RAM (LUTs), not BRAM</td></tr>
+            <tr><td><strong>Total</strong></td><td><strong>12</strong></td><td><strong>10</strong></td><td><strong>17</strong></td><td>4.66% of 365 tiles</td></tr>
+          </tbody>
+        </table>
+      </div>
+
+      <!-- 5. Power -->
+      <h3>5. Power Estimate</h3>
+      <div class="table-wrap">
+        <table>
+          <thead><tr><th>Category</th><th>Build 24</th><th>Build 25</th></tr></thead>
+          <tbody>
+            <tr><td>Dynamic Power</td><td>0.591 W</td><td>0.590 W</td></tr>
+            <tr><td>Device Static</td><td>0.163 W</td><td>0.163 W</td></tr>
+            <tr><td><strong>Total On-Chip</strong></td><td><strong>0.754 W</strong></td><td><strong>0.753 W</strong></td></tr>
+          </tbody>
+        </table>
+      </div>
+      <p class="muted">Power is essentially unchanged (-1 mW). MTI logic is lightweight fabric arithmetic; DC notch is combinational zeroing with negligible dynamic power.</p>
+
+      <!-- 6. Critical Path -->
+      <h3>6. Critical Path Analysis</h3>
+      <p>The tightest path (WNS = +0.132 ns) is in the <code>ft601_clk_in</code> (100 MHz) domain: <code>ft601_rxf</code> input pad &rarr; 8 logic levels (IBUF + LUT1 + LUT3 + 4&times;LUT6 + LUT5) &rarr; <code>usb_inst/FSM_sequential_current_state_reg[2]/D</code>. This is the USB read FSM path and is unrelated to MTI or CFAR.</p>
+      <p>The <code>clk_100m</code> domain (where MTI, CFAR, and Doppler operate) has +0.634 ns slack &mdash; improved from Build 24's +0.287 ns. The MTI canceller adds no new critical paths.</p>
+
+      <!-- 7. Post-synth vs Post-route -->
+      <h3>7. Post-Synthesis vs Post-Route Comparison</h3>
+      <div class="table-wrap">
+        <table>
+          <thead><tr><th>Metric</th><th>Post-Synth</th><th>Post-Route (final)</th></tr></thead>
+          <tbody>
+            <tr><td>WNS (setup)</td><td>+0.123 ns</td><td>+0.132 ns</td></tr>
+            <tr><td>WHS (hold)</td><td>-0.076 ns (29 violations)</td><td>+0.058 ns (0 violations)</td></tr>
+            <tr><td>LUTs</td><td>9,363</td><td>9,252</td></tr>
+            <tr><td>FFs</td><td>12,537</td><td>12,488</td></tr>
+          </tbody>
+        </table>
+      </div>
+      <p class="muted">Post-route phys_opt resolved all 29 hold violations and improved setup slack by 9 ps. LUT/FF count reduced slightly by optimization passes.</p>
+
+      <!-- 8. DRC -->
+      <h3>8. DRC (Design Rule Checks)</h3>
+      <p>184 checks performed. <strong>0 errors, 0 critical warnings.</strong> Same advisory/warning profile as Build 24 (DPIP-1, DPOP-1/2, REQP-1839/1840, RPBF-3 etc.). No new DRC issues from MTI integration.</p>
+
+      <!-- 9. Methodology -->
+      <h3>9. Methodology Report</h3>
+      <p>Same methodology advisory profile as Build 24. No new methodology warnings from MTI or DC notch logic.</p>
+
+      <!-- 10. Congestion -->
+      <h3>10. Congestion</h3>
+      <p><strong>No congestion windows found above level 5.</strong> The design remains well-placed at 6.87% LUT utilization.</p>
+
+      <!-- 11. Route Status -->
+      <h3>11. Route Status</h3>
+      <ul>
+        <li>Total logical nets: 34,325</li>
+        <li>Routable nets: 24,510 &mdash; <strong>24,510 fully routed (100%)</strong></li>
+        <li>Nets with routing errors: <strong>0</strong></li>
+      </ul>
+
+      <!-- 12. Hierarchical Utilization (MTI focus) -->
+      <h3>12. Hierarchical Utilization &mdash; MTI Module</h3>
+      <div class="table-wrap">
+        <table>
+          <thead><tr><th>Instance</th><th>LUTs</th><th>FFs</th><th>BRAM</th><th>DSP</th><th>Notes</th></tr></thead>
+          <tbody>
+            <tr><td>radar_system_top (total)</td><td>9,252</td><td>12,488</td><td>17</td><td>142</td><td>Full design</td></tr>
+            <tr><td>&nbsp;&nbsp;cfar_inst</td><td>2,210</td><td>1,282</td><td>1</td><td>3</td><td>CA-CFAR detector</td></tr>
+            <tr><td>&nbsp;&nbsp;rx_inst (receiver)</td><td>6,731</td><td>10,703</td><td>10</td><td>139</td><td>Full receiver chain</td></tr>
+            <tr><td>&nbsp;&nbsp;&nbsp;&nbsp;mti_inst</td><td>544</td><td>2,082</td><td>0</td><td>0</td><td>MTI canceller (new)</td></tr>
+            <tr><td>&nbsp;&nbsp;&nbsp;&nbsp;doppler_proc</td><td>681</td><td>540</td><td>4</td><td>10</td><td>Doppler processor</td></tr>
+            <tr><td>&nbsp;&nbsp;&nbsp;&nbsp;ddc</td><td>676</td><td>2,959</td><td>0</td><td>117</td><td>DDC subsystem</td></tr>
+            <tr><td>&nbsp;&nbsp;&nbsp;&nbsp;mf_dual</td><td>2,439</td><td>4,796</td><td>7</td><td>12</td><td>Matched filter</td></tr>
+            <tr><td>&nbsp;&nbsp;&nbsp;&nbsp;range_decim</td><td>219</td><td>129</td><td>0</td><td>0</td><td>Range bin decimator</td></tr>
+            <tr><td>&nbsp;&nbsp;usb_inst</td><td>159</td><td>217</td><td>0</td><td>0</td><td>USB data interface</td></tr>
+            <tr><td>&nbsp;&nbsp;tx_inst</td><td>111</td><td>91</td><td>1</td><td>0</td><td>Transmitter</td></tr>
+          </tbody>
+        </table>
+      </div>
+      <p class="muted">MTI canceller: 544 LUTs (0.40% device), 2,082 FFs (0.77% device), 0 BRAM, 0 DSP. The high FF count is from the chirp delay line (64 range bins &times; 16-bit I + 16-bit Q = 2,048 FFs for storage) implemented as distributed register file rather than BRAM.</p>
+
+      <!-- 13. Build Comparison -->
+      <h3>13. Build-Over-Build Comparison</h3>
+      <div class="table-wrap">
+        <table>
+          <thead><tr><th>Metric</th><th>Build 21 (baseline)</th><th>Build 23 (failed)</th><th>Build 24 (CFAR)</th><th>Build 25 (MTI)</th></tr></thead>
+          <tbody>
+            <tr><td>WNS (ns)</td><td>+0.156</td><td style="color:#c33;">-0.309</td><td>+0.179</td><td style="color:#080;"><strong>+0.132</strong></td></tr>
+            <tr><td>WHS (ns)</td><td>+0.064</td><td>&mdash;</td><td>+0.056</td><td>+0.058</td></tr>
+            <tr><td>LUTs</td><td>6,192</td><td>8,668 (synth)</td><td>8,558</td><td>9,252</td></tr>
+            <tr><td>FFs</td><td>9,064</td><td>10,411 (synth)</td><td>10,384</td><td>12,488</td></tr>
+            <tr><td>BRAM Tiles</td><td>16</td><td>17 (synth)</td><td>17</td><td>17</td></tr>
+            <tr><td>DSP48E1</td><td>139</td><td>&mdash;</td><td>142</td><td>142</td></tr>
+            <tr><td>Power (W)</td><td>0.732</td><td>&mdash;</td><td>0.754</td><td>0.753</td></tr>
+            <tr><td>Bitstream</td><td>Safe</td><td style="color:#c33;">Unsafe</td><td>Safe</td><td style="color:#080;"><strong>Safe</strong></td></tr>
+          </tbody>
+        </table>
+      </div>
+
+      <!-- 14. MTI + DC Notch Resource Cost -->
+      <h3>14. MTI + DC Notch Integration Resource Cost</h3>
+      <div class="table-wrap">
+        <table>
+          <thead><tr><th>Resource</th><th>MTI + DC Notch</th><th>% of Device</th><th>Notes</th></tr></thead>
+          <tbody>
+            <tr><td>LUTs</td><td>~694</td><td>0.52%</td><td>MTI: 544 LUTs (subtraction, saturation, mux). DC notch: ~150 LUTs (bin compare, data zeroing) in system_top.</td></tr>
+            <tr><td>FFs</td><td>~2,104</td><td>0.78%</td><td>MTI: 2,082 FFs (chirp delay line 64&times;32-bit + control). DC notch: ~22 FFs (registered width, active flags).</td></tr>
+            <tr><td>BRAM</td><td>0</td><td>0%</td><td>Chirp delay line fits in distributed registers (64 bins &times; 32 bits = 2,048 bits)</td></tr>
+            <tr><td>DSP48E1</td><td>0</td><td>0%</td><td>Subtraction uses fabric adders, no multiply needed</td></tr>
+          </tbody>
+        </table>
+      </div>
+      <p class="muted">Total MTI + DC notch cost: 0.52% of device LUTs, 0.78% of FFs. Very lightweight addition. Backward-compatible: <code>host_mti_enable</code> defaults to 0 (pass-through), <code>host_dc_notch_width</code> defaults to 0 (off).</p>
+
+      <!-- 15. Verification Summary -->
+      <h3>15. Verification Summary</h3>
+      <div class="table-wrap">
+        <table>
+          <thead><tr><th>Test Suite</th><th>Tests</th><th>Checks</th><th>Status</th></tr></thead>
+          <tbody>
+            <tr><td>FPGA regression (run_regression.sh)</td><td>23</td><td>&mdash;</td><td>23/23 PASS</td></tr>
+            <tr><td>MTI standalone (tb_mti_canceller.v)</td><td>11</td><td>29</td><td>29/29 PASS</td></tr>
+            <tr><td>CFAR standalone (tb_cfar_ca.v)</td><td>14</td><td>23</td><td>23/23 PASS</td></tr>
+            <tr><td>Digital gain (tb_rx_gain_control.v)</td><td>&mdash;</td><td>32</td><td>32/32 PASS</td></tr>
+            <tr><td>Threshold fallback (tb_threshold_detector.v)</td><td>&mdash;</td><td>22</td><td>22/22 PASS</td></tr>
+            <tr><td>System E2E (tb_system_e2e.v, Group 14)</td><td>13</td><td>67</td><td>67/67 PASS</td></tr>
+            <tr><td>Real-data co-sim: Range FFT</td><td>1</td><td>1,024</td><td>1024/1024 exact</td></tr>
+            <tr><td>Real-data co-sim: Doppler</td><td>1</td><td>2,056</td><td>2056/2056 exact</td></tr>
+            <tr><td>Real-data co-sim: Full-chain</td><td>1</td><td>2,057</td><td>2057/2057 exact</td></tr>
+            <tr><td>MCU regression</td><td>20</td><td>&mdash;</td><td>20/20 PASS</td></tr>
+          </tbody>
+        </table>
+      </div>
+      <p class="muted">5,310 individual data checks across all RTL test suites. Zero failures. MTI standalone test covers: pass-through, first-chirp mute, subtraction correctness, stationary target cancellation, moving target preservation, saturation (positive/negative), enable toggle, reset behavior, bin tracking, back-to-back chirps, and negative value handling.</p>
+
+      <h3>Build 25 Artifacts</h3>
+      <ul>
+        <li>Bitstream: <code>~/PLFM_RADAR_work/vivado_project/bitstream/radar_system_top_build25.bit</code> (9.7 MB)</li>
+        <li>Reports: <code>~/PLFM_RADAR_work/vivado_project/reports_build25/</code> (21 report files)</li>
+        <li>Build log: <code>~/PLFM_RADAR_work/build25.log</code></li>
+        <li>TCL script: <code>~/PLFM_RADAR_work/vivado_project/build25_mti.tcl</code></li>
+      </ul>
+      <p class="muted">Note: TCL crashed at step 13/15 (<code>extract_files</code> missing parameter) after all reports were generated. Same non-critical scripting bug as Build 24.</p>
+    </section>
+
     <!-- ===== Build 24 — 15-Point Report ===== -->
     <section class="card" style="margin-top:0.8rem;">
       <h2>Build 24 &mdash; 15-Point Engineering Report</h2>
@@ -280,7 +496,7 @@
             <tr><td>Production-target XDC</td><td><code>9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc</code></td><td>Constraint source of truth for the production FPGA target</td><td>Tracked and validated after Build 16 cleanup port</td></tr>
             <tr><td>FPGA programming flow</td><td><code>9_Firmware/9_2_FPGA/scripts/program_fpga.tcl</code></td><td>Programs the device and reports DONE / INIT_COMPLETE / probes presence</td><td>Primary operator-facing programming script</td></tr>
             <tr><td>Debug probe insertion flow</td><td><code>9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl</code></td><td>Used when generating or refreshing debug-capable images</td><td>Keep matched with the selected debug bitstream</td></tr>
-            <tr><td>FPGA regression runner</td><td><code>9_Firmware/9_2_FPGA/run_regression.sh</code></td><td>Pre-arrival regression evidence for the tracked FPGA baseline</td><td>22 / 22 passing on the current tracked branch (includes CFAR + E2E tests)</td></tr>
+            <tr><td>FPGA regression runner</td><td><code>9_Firmware/9_2_FPGA/run_regression.sh</code></td><td>Pre-arrival regression evidence for the tracked FPGA baseline</td><td>23 / 23 passing on the current tracked branch (includes CFAR + MTI + E2E tests)</td></tr>
             <tr><td>MCU regression harness</td><td><code>9_Firmware/9_1_Microcontroller/tests/Makefile</code></td><td>Pre-arrival firmware regression evidence before flashing hardware</td><td>20 / 20 passing on the current tracked branch</td></tr>
             <tr><td>Bring-up logging macros</td><td><code>9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h</code></td><td>Defines the main first-power-on log vocabulary used over USART3</td><td>Observation-only instrumentation layer</td></tr>
             <tr><td>Board-day worksheet</td><td><code>docs/board-day-worksheet.html</code></td><td>Record pass/fail, measurements, and blockers during first sessions</td><td>Use with this page and the bring-up plan</td></tr>
@@ -315,9 +531,9 @@
 
     <section class="card" style="margin-top:0.8rem;">
       <h2>FPGA implementation analysis</h2>
-      <p><span class="chip">Status: Current engineering baseline &mdash; Build 24 (CFAR + pipeline fix)</span></p>
+      <p><span class="chip">Status: Current engineering baseline &mdash; Build 25 (MTI + DC notch)</span></p>
-      <p class="muted">Build 24 is the current production baseline. Includes CA-CFAR detector integration (CA/GO/SO modes) with pipelined noise computation for timing closure. Full 15-point report above. WNS +0.179 ns (improved from Build 21's +0.156 ns due to phys_opt improvements). DSP count 142 (+3 for CFAR alpha and cross-multiply). BRAM 17 (+1 for CFAR magnitude buffer).</p>
+      <p class="muted">Build 25 is the current production baseline. Includes MTI canceller (2-pulse clutter cancellation) and DC notch filter on top of CA-CFAR detector. Full 15-point report above. WNS +0.132 ns, WHS +0.058 ns. DSP count 142 (unchanged). BRAM 17 (unchanged). LUTs 9,252 (+694 from Build 24). FFs 12,488 (+2,104). Power 0.753 W (unchanged).</p>
-      <p class="muted">Build 23 failed timing (WNS -0.309 ns) due to combinational critical path in CFAR noise computation. Root-caused and fixed by pipelining <code>noise_sum_comb</code> into a registered intermediate (<code>noise_sum_reg</code>), splitting the path across two clock cycles.</p>
+      <p class="muted">Build 24 (v0.1.5-cfar) integrated CA-CFAR with pipelined noise computation. Build 23 failed timing (WNS -0.309 ns) due to combinational critical path &mdash; fixed by pipelining.</p>
       <p class="muted">Build 21 (v0.1.4-build21) retained as pre-CFAR reference. Build 20 (v0.1.3-build20) and earlier retained for historical reference.</p>
     </section>
 
@@ -335,11 +551,11 @@
     <section class="card" style="margin-top:0.8rem;">
       <h2>Report Currency Notice</h2>
       <ul>
-        <li>The current routed production-target baseline is <strong>Build 24</strong> with all timing constraints met. WNS +0.179 ns, WHS +0.056 ns, 142 DSP48E1, 17 BRAM, 0.754 W.</li>
+        <li>The current routed production-target baseline is <strong>Build 25</strong> with all timing constraints met. WNS +0.132 ns, WHS +0.058 ns, 142 DSP48E1, 17 BRAM, 0.753 W.</li>
-        <li>All architectural gaps are closed: Gap 1 (CFAR) integrated as CA-CFAR detector with CA/GO/SO modes. Gaps 2&ndash;7 were closed prior to Build 21.</li>
+        <li>All architectural gaps are closed: Gap 1 (CFAR) integrated as CA-CFAR detector with CA/GO/SO modes (Build 24). MTI canceller + DC notch filter added in Build 25. Gaps 2&ndash;7 were closed prior to Build 21.</li>
-        <li>FPGA regression: 22/22 pass (includes CFAR standalone + E2E CFAR config tests). MCU regression: 20/20 pass. Real-data co-sim: 3/3 exact match (5,137 data checks).</li>
+        <li>FPGA regression: 23/23 pass (includes CFAR + MTI + E2E tests). MCU regression: 20/20 pass. Real-data co-sim: 3/3 exact match (5,137 data checks).</li>
-        <li>CFAR integration cost: +2,229 LUTs, +1,281 FFs, +1 BRAM, +3 DSPs. Backward-compatible: <code>host_cfar_enable</code> defaults to disabled.</li>
+        <li>MTI integration cost: +694 LUTs, +2,104 FFs, 0 BRAM, 0 DSPs. Backward-compatible: <code>host_mti_enable</code> and <code>host_dc_notch_width</code> default to disabled/off.</li>
-        <li>Detailed Build 24 engineering reports are on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build24/</code>.</li>
+        <li>Detailed Build 25 engineering reports are on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build25/</code>.</li>
         <li>The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.</li>
       </ul>
     </section>