+ Build 25 — 15-Point Engineering Report
+ Status: PASS — Production-safe bitstream generated
+ Date: 2026-03-20 | Commit: ed629e7 | Device: XC7A200T-2FBG484I | Vivado 2025.2
+
+
+ 1. Timing Summary
+
+
+ | Clock Domain | Period (ns) | WNS (ns) | WHS (ns) | WPWS (ns) | Status |
|---|
+
+ | clk_100m | 10.000 | +0.634 | +0.058 | +3.870 | PASS |
+ | clk_mmcm_out0 (400 MHz) | 2.500 | +0.304 | +0.115 | +0.684 | PASS |
+ | adc_dco_p | — | +0.904 | — | +0.361 | PASS |
+ | ft601_clk_in | 10.000 | +0.132 | +0.121 | +4.500 | PASS |
+ | clk_120m_dac | — | +0.773 | +0.151 | +3.666 | PASS |
+
+
+
TNS = 0.000 ns, THS = 0.000 ns across all domains. Zero failing endpoints. Overall WNS +0.132 ns (ft601_clk_in domain, USB FSM path). Overall WHS +0.058 ns.
+
+
+ 2. Utilization (Post-Route)
+
+
+ | Resource | Build 24 (CFAR) | Build 25 (MTI) | Available | Util% | Delta |
|---|
+
+ | Slice LUTs | 8,558 | 9,252 | 134,600 | 6.87% | +694 (+8.1%) |
+ | Slice Registers (FFs) | 10,384 | 12,488 | 269,200 | 4.64% | +2,104 (+20%) |
+ | Block RAM Tiles | 17 | 17 | 365 | 4.66% | 0 |
+ | RAMB36E1 | 12 | 12 | 365 | 3.29% | 0 |
+ | RAMB18E1 | 10 | 10 | 730 | 1.37% | 0 |
+ | LUT as Distributed RAM | — | 48 | 46,200 | 0.10% | — |
+ | DSP48E1 | 142 | 142 | 740 | 19.19% | 0 |
+ | Bonded IOBs | 178 | 178 | 285 | 62.46% | 0 |
+ | BUFGCTRL | 5 | 5 | 32 | 15.63% | 0 |
+ | MMCME2_ADV | 1 | 1 | 10 | 10.00% | 0 |
+
+
+
MTI canceller added +694 LUTs (distributed RAM for chirp delay line + subtraction logic + DC notch comparators) and +2,104 FFs (I/Q pipeline registers, saturation logic, notch width comparators). Zero BRAM and DSP impact — MTI uses distributed RAM and fabric arithmetic only.
+
+
+ 3. DSP48E1 Breakdown by Module
+
+
+ | Module | DSP48E1 | Notes |
|---|
+
+ | DDC (FIR I + FIR Q + CIC + NCO) | 117 | Dominant consumer: 47+47 FIR taps + 10+10 CIC + 2 DDC + 1 NCO |
+ | Matched Filter Processing Chain | 12 | 8 FFT butterflies + 4 freq-domain multiply |
+ | Doppler Processor + FFT | 10 | 8 FFT butterflies + 2 magnitude |
+ | CFAR Detector | 3 | alpha*noise multiply + GO/SO cross-multiply (pipelined) |
+ | MTI Canceller | 0 | Pure fabric arithmetic (subtraction + saturation) |
+ | Total | 142 | 19.19% of 740 available |
+
+
+
4. BRAM Breakdown by Module
+
+
+ | Module | RAMB36 | RAMB18 | Tiles | Notes |
|---|
+
+ | Doppler Processor | 4 | 0 | 4 | Range-Doppler accumulation buffers |
+ | Matched Filter (mf_dual) | 2 | 10 | 7 | Coefficient + I/Q data BRAMs |
+ | CFAR Detector | 1 | 0 | 1 | Magnitude buffer (2048×17 bits) |
+ | Transmitter (chirp mem) | 1 | 0 | 1 | Chirp waveform storage |
+ | FFT Engines (2×) | 4 | 0 | 4 | Twiddle factor + butterfly BRAMs |
+ | MTI Canceller | 0 | 0 | 0 | Uses distributed RAM (LUTs), not BRAM |
+ | Total | 12 | 10 | 17 | 4.66% of 365 tiles |
+
+
+
5. Power Estimate
+
+
+ | Category | Build 24 | Build 25 |
|---|
+
+ | Dynamic Power | 0.591 W | 0.590 W |
+ | Device Static | 0.163 W | 0.163 W |
+ | Total On-Chip | 0.754 W | 0.753 W |
+
+
+
Power is essentially unchanged (-1 mW). MTI logic is lightweight fabric arithmetic; DC notch is combinational zeroing with negligible dynamic power.
+
+
+ 6. Critical Path Analysis
+ The tightest path (WNS = +0.132 ns) is in the ft601_clk_in (100 MHz) domain: ft601_rxf input pad → 8 logic levels (IBUF + LUT1 + LUT3 + 4×LUT6 + LUT5) → usb_inst/FSM_sequential_current_state_reg[2]/D. This is the USB read FSM path and is unrelated to MTI or CFAR.
+ The clk_100m domain (where MTI, CFAR, and Doppler operate) has +0.634 ns slack — improved from Build 24's +0.287 ns. The MTI canceller adds no new critical paths.
+
+
+ 7. Post-Synthesis vs Post-Route Comparison
+
+
+ | Metric | Post-Synth | Post-Route (final) |
|---|
+
+ | WNS (setup) | +0.123 ns | +0.132 ns |
+ | WHS (hold) | -0.076 ns (29 violations) | +0.058 ns (0 violations) |
+ | LUTs | 9,363 | 9,252 |
+ | FFs | 12,537 | 12,488 |
+
+
+
Post-route phys_opt resolved all 29 hold violations and improved setup slack by 9 ps. LUT/FF count reduced slightly by optimization passes.
+
+
+ 8. DRC (Design Rule Checks)
+ 184 checks performed. 0 errors, 0 critical warnings. Same advisory/warning profile as Build 24 (DPIP-1, DPOP-1/2, REQP-1839/1840, RPBF-3 etc.). No new DRC issues from MTI integration.
+
+
+ 9. Methodology Report
+ Same methodology advisory profile as Build 24. No new methodology warnings from MTI or DC notch logic.
+
+
+ 10. Congestion
+ No congestion windows found above level 5. The design remains well-placed at 6.87% LUT utilization.
+
+
+ 11. Route Status
+
+ - Total logical nets: 34,325
+ - Routable nets: 24,510 — 24,510 fully routed (100%)
+ - Nets with routing errors: 0
+
+
+
+ 12. Hierarchical Utilization — MTI Module
+
+
+ | Instance | LUTs | FFs | BRAM | DSP | Notes |
|---|
+
+ | radar_system_top (total) | 9,252 | 12,488 | 17 | 142 | Full design |
+ | cfar_inst | 2,210 | 1,282 | 1 | 3 | CA-CFAR detector |
+ | rx_inst (receiver) | 6,731 | 10,703 | 10 | 139 | Full receiver chain |
+ | mti_inst | 544 | 2,082 | 0 | 0 | MTI canceller (new) |
+ | doppler_proc | 681 | 540 | 4 | 10 | Doppler processor |
+ | ddc | 676 | 2,959 | 0 | 117 | DDC subsystem |
+ | mf_dual | 2,439 | 4,796 | 7 | 12 | Matched filter |
+ | range_decim | 219 | 129 | 0 | 0 | Range bin decimator |
+ | usb_inst | 159 | 217 | 0 | 0 | USB data interface |
+ | tx_inst | 111 | 91 | 1 | 0 | Transmitter |
+
+
+
MTI canceller: 544 LUTs (0.40% device), 2,082 FFs (0.77% device), 0 BRAM, 0 DSP. The high FF count is from the chirp delay line (64 range bins × 16-bit I + 16-bit Q = 2,048 FFs for storage) implemented as distributed register file rather than BRAM.
+
+
+ 13. Build-Over-Build Comparison
+
+
+ | Metric | Build 21 (baseline) | Build 23 (failed) | Build 24 (CFAR) | Build 25 (MTI) |
|---|
+
+ | WNS (ns) | +0.156 | -0.309 | +0.179 | +0.132 |
+ | WHS (ns) | +0.064 | — | +0.056 | +0.058 |
+ | LUTs | 6,192 | 8,668 (synth) | 8,558 | 9,252 |
+ | FFs | 9,064 | 10,411 (synth) | 10,384 | 12,488 |
+ | BRAM Tiles | 16 | 17 (synth) | 17 | 17 |
+ | DSP48E1 | 139 | — | 142 | 142 |
+ | Power (W) | 0.732 | — | 0.754 | 0.753 |
+ | Bitstream | Safe | Unsafe | Safe | Safe |
+
+
+
14. MTI + DC Notch Integration Resource Cost
+
+
+ | Resource | MTI + DC Notch | % of Device | Notes |
|---|
+
+ | LUTs | ~694 | 0.52% | MTI: 544 LUTs (subtraction, saturation, mux). DC notch: ~150 LUTs (bin compare, data zeroing) in system_top. |
+ | FFs | ~2,104 | 0.78% | MTI: 2,082 FFs (chirp delay line 64×32-bit + control). DC notch: ~22 FFs (registered width, active flags). |
+ | BRAM | 0 | 0% | Chirp delay line fits in distributed registers (64 bins × 32 bits = 2,048 bits) |
+ | DSP48E1 | 0 | 0% | Subtraction uses fabric adders, no multiply needed |
+
+
+
Total MTI + DC notch cost: 0.52% of device LUTs, 0.78% of FFs. Very lightweight addition. Backward-compatible: host_mti_enable defaults to 0 (pass-through), host_dc_notch_width defaults to 0 (off).
+
+
+ 15. Verification Summary
+
+
+ | Test Suite | Tests | Checks | Status |
|---|
+
+ | FPGA regression (run_regression.sh) | 23 | — | 23/23 PASS |
+ | MTI standalone (tb_mti_canceller.v) | 11 | 29 | 29/29 PASS |
+ | CFAR standalone (tb_cfar_ca.v) | 14 | 23 | 23/23 PASS |
+ | Digital gain (tb_rx_gain_control.v) | — | 32 | 32/32 PASS |
+ | Threshold fallback (tb_threshold_detector.v) | — | 22 | 22/22 PASS |
+ | System E2E (tb_system_e2e.v, Group 14) | 13 | 67 | 67/67 PASS |
+ | Real-data co-sim: Range FFT | 1 | 1,024 | 1024/1024 exact |
+ | Real-data co-sim: Doppler | 1 | 2,056 | 2056/2056 exact |
+ | Real-data co-sim: Full-chain | 1 | 2,057 | 2057/2057 exact |
+ | MCU regression | 20 | — | 20/20 PASS |
+
+
+
5,310 individual data checks across all RTL test suites. Zero failures. MTI standalone test covers: pass-through, first-chirp mute, subtraction correctness, stationary target cancellation, moving target preservation, saturation (positive/negative), enable toggle, reset behavior, bin tracking, back-to-back chirps, and negative value handling.
+
+ Build 25 Artifacts
+
+ - Bitstream:
~/PLFM_RADAR_work/vivado_project/bitstream/radar_system_top_build25.bit (9.7 MB)
+ - Reports:
~/PLFM_RADAR_work/vivado_project/reports_build25/ (21 report files)
+ - Build log:
~/PLFM_RADAR_work/build25.log
+ - TCL script:
~/PLFM_RADAR_work/vivado_project/build25_mti.tcl
+
+ Note: TCL crashed at step 13/15 (extract_files missing parameter) after all reports were generated. Same non-critical scripting bug as Build 24.
+
+
Build 24 — 15-Point Engineering Report
@@ -280,7 +496,7 @@
| Production-target XDC | 9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc | Constraint source of truth for the production FPGA target | Tracked and validated after Build 16 cleanup port |
| FPGA programming flow | 9_Firmware/9_2_FPGA/scripts/program_fpga.tcl | Programs the device and reports DONE / INIT_COMPLETE / probes presence | Primary operator-facing programming script |
| Debug probe insertion flow | 9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl | Used when generating or refreshing debug-capable images | Keep matched with the selected debug bitstream |
- | FPGA regression runner | 9_Firmware/9_2_FPGA/run_regression.sh | Pre-arrival regression evidence for the tracked FPGA baseline | 22 / 22 passing on the current tracked branch (includes CFAR + E2E tests) |
+ | FPGA regression runner | 9_Firmware/9_2_FPGA/run_regression.sh | Pre-arrival regression evidence for the tracked FPGA baseline | 23 / 23 passing on the current tracked branch (includes CFAR + MTI + E2E tests) |
| MCU regression harness | 9_Firmware/9_1_Microcontroller/tests/Makefile | Pre-arrival firmware regression evidence before flashing hardware | 20 / 20 passing on the current tracked branch |
| Bring-up logging macros | 9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h | Defines the main first-power-on log vocabulary used over USART3 | Observation-only instrumentation layer |
| Board-day worksheet | docs/board-day-worksheet.html | Record pass/fail, measurements, and blockers during first sessions | Use with this page and the bring-up plan |
@@ -315,9 +531,9 @@
FPGA implementation analysis
- Status: Current engineering baseline — Build 24 (CFAR + pipeline fix)
- Build 24 is the current production baseline. Includes CA-CFAR detector integration (CA/GO/SO modes) with pipelined noise computation for timing closure. Full 15-point report above. WNS +0.179 ns (improved from Build 21's +0.156 ns due to phys_opt improvements). DSP count 142 (+3 for CFAR alpha and cross-multiply). BRAM 17 (+1 for CFAR magnitude buffer).
- Build 23 failed timing (WNS -0.309 ns) due to combinational critical path in CFAR noise computation. Root-caused and fixed by pipelining noise_sum_comb into a registered intermediate (noise_sum_reg), splitting the path across two clock cycles.
+ Status: Current engineering baseline — Build 25 (MTI + DC notch)
+ Build 25 is the current production baseline. Includes MTI canceller (2-pulse clutter cancellation) and DC notch filter on top of CA-CFAR detector. Full 15-point report above. WNS +0.132 ns, WHS +0.058 ns. DSP count 142 (unchanged). BRAM 17 (unchanged). LUTs 9,252 (+694 from Build 24). FFs 12,488 (+2,104). Power 0.753 W (unchanged).
+ Build 24 (v0.1.5-cfar) integrated CA-CFAR with pipelined noise computation. Build 23 failed timing (WNS -0.309 ns) due to combinational critical path — fixed by pipelining.
Build 21 (v0.1.4-build21) retained as pre-CFAR reference. Build 20 (v0.1.3-build20) and earlier retained for historical reference.
@@ -335,11 +551,11 @@
Report Currency Notice
- - The current routed production-target baseline is Build 24 with all timing constraints met. WNS +0.179 ns, WHS +0.056 ns, 142 DSP48E1, 17 BRAM, 0.754 W.
- - All architectural gaps are closed: Gap 1 (CFAR) integrated as CA-CFAR detector with CA/GO/SO modes. Gaps 2–7 were closed prior to Build 21.
- - FPGA regression: 22/22 pass (includes CFAR standalone + E2E CFAR config tests). MCU regression: 20/20 pass. Real-data co-sim: 3/3 exact match (5,137 data checks).
- - CFAR integration cost: +2,229 LUTs, +1,281 FFs, +1 BRAM, +3 DSPs. Backward-compatible:
host_cfar_enable defaults to disabled.
- - Detailed Build 24 engineering reports are on the remote Vivado host at
~/PLFM_RADAR_work/vivado_project/reports_build24/.
+ - The current routed production-target baseline is Build 25 with all timing constraints met. WNS +0.132 ns, WHS +0.058 ns, 142 DSP48E1, 17 BRAM, 0.753 W.
+ - All architectural gaps are closed: Gap 1 (CFAR) integrated as CA-CFAR detector with CA/GO/SO modes (Build 24). MTI canceller + DC notch filter added in Build 25. Gaps 2–7 were closed prior to Build 21.
+ - FPGA regression: 23/23 pass (includes CFAR + MTI + E2E tests). MCU regression: 20/20 pass. Real-data co-sim: 3/3 exact match (5,137 data checks).
+ - MTI integration cost: +694 LUTs, +2,104 FFs, 0 BRAM, 0 DSPs. Backward-compatible:
host_mti_enable and host_dc_notch_width default to disabled/off.
+ - Detailed Build 25 engineering reports are on the remote Vivado host at
~/PLFM_RADAR_work/vivado_project/reports_build25/.
- The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.