fix(rtl,constraints): change IBUFDS to IOSTANDARD DEFAULT for multi-target bank voltage compatibility

The IBUFDS primitives in ad9484_interface_400m.v hardcoded LVDS_25 and
DIFF_TERM TRUE, which overrode XDC constraints. On the XC7A50T (Bank 14
VCCO=3.3V), this caused a BIVC-1 DRC error: LVDS_25 requires VCCO=2.5V,
conflicting with adc_pwdn (LVCMOS33, VCCO=3.3V) in the same bank.

Changes:
- ad9484_interface_400m.v: IBUFDS parameters changed from LVDS_25/DIFF_TERM
  TRUE to DEFAULT/DIFF_TERM FALSE, delegating control to XDC per target
- xc7a50t_ftg256.xdc: Re-enable DIFF_TERM TRUE (safe now that RTL does not
  hardcode LVDS_25), update DRC Fix History with correct root cause

9_Firmware/9_2_FPGA/ad9484_interface_400m.v

@@ -20,12 +20,16 @@ wire [7:0] adc_data;
 wire adc_dco;
 
 // IBUFDS for each data bit
+// NOTE: IOSTANDARD and DIFF_TERM are set via XDC constraints, not RTL
+// parameters, to support multiple FPGA targets with different bank voltages:
+//   - XC7A200T (FBG484): Bank 14 VCCO = 2.5V → LVDS_25
+//   - XC7A50T  (FTG256): Bank 14 VCCO = 3.3V → LVDS_33
 genvar i;
 generate
     for (i = 0; i < 8; i = i + 1) begin : data_buffers
         IBUFDS #(
-            .DIFF_TERM("TRUE"),
-            .IOSTANDARD("LVDS_25")
+            .DIFF_TERM("FALSE"),    // Overridden by XDC DIFF_TERM property
+            .IOSTANDARD("DEFAULT")  // Overridden by XDC IOSTANDARD property
         ) ibufds_data (
             .O(adc_data[i]),
             .I(adc_d_p[i]),
@@ -36,8 +40,8 @@ endgenerate
 
 // IBUFDS for DCO
 IBUFDS #(
-    .DIFF_TERM("TRUE"),
-    .IOSTANDARD("LVDS_25") 
+    .DIFF_TERM("FALSE"),    // Overridden by XDC DIFF_TERM property
+    .IOSTANDARD("DEFAULT")  // Overridden by XDC IOSTANDARD property
 ) ibufds_dco (
     .O(adc_dco),
     .I(adc_dco_p),