From d50e51ada6937f5fe287b821333dba28bbcb2729 Mon Sep 17 00:00:00 2001 From: Jason <83615043+JJassonn69@users.noreply.github.com> Date: Tue, 7 Apr 2026 05:17:11 +0300 Subject: [PATCH] fix(rtl,constraints): change IBUFDS to IOSTANDARD DEFAULT for multi-target bank voltage compatibility The IBUFDS primitives in ad9484_interface_400m.v hardcoded LVDS_25 and DIFF_TERM TRUE, which overrode XDC constraints. On the XC7A50T (Bank 14 VCCO=3.3V), this caused a BIVC-1 DRC error: LVDS_25 requires VCCO=2.5V, conflicting with adc_pwdn (LVCMOS33, VCCO=3.3V) in the same bank. Changes: - ad9484_interface_400m.v: IBUFDS parameters changed from LVDS_25/DIFF_TERM TRUE to DEFAULT/DIFF_TERM FALSE, delegating control to XDC per target - xc7a50t_ftg256.xdc: Re-enable DIFF_TERM TRUE (safe now that RTL does not hardcode LVDS_25), update DRC Fix History with correct root cause --- 9_Firmware/9_2_FPGA/ad9484_interface_400m.v | 12 +++++++---- .../9_2_FPGA/constraints/xc7a50t_ftg256.xdc | 20 ++++++++----------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/9_Firmware/9_2_FPGA/ad9484_interface_400m.v b/9_Firmware/9_2_FPGA/ad9484_interface_400m.v index a12ec16..557ce12 100644 --- a/9_Firmware/9_2_FPGA/ad9484_interface_400m.v +++ b/9_Firmware/9_2_FPGA/ad9484_interface_400m.v @@ -20,12 +20,16 @@ wire [7:0] adc_data; wire adc_dco; // IBUFDS for each data bit +// NOTE: IOSTANDARD and DIFF_TERM are set via XDC constraints, not RTL +// parameters, to support multiple FPGA targets with different bank voltages: +// - XC7A200T (FBG484): Bank 14 VCCO = 2.5V → LVDS_25 +// - XC7A50T (FTG256): Bank 14 VCCO = 3.3V → LVDS_33 genvar i; generate for (i = 0; i < 8; i = i + 1) begin : data_buffers IBUFDS #( - .DIFF_TERM("TRUE"), - .IOSTANDARD("LVDS_25") + .DIFF_TERM("FALSE"), // Overridden by XDC DIFF_TERM property + .IOSTANDARD("DEFAULT") // Overridden by XDC IOSTANDARD property ) ibufds_data ( .O(adc_data[i]), .I(adc_d_p[i]), @@ -36,8 +40,8 @@ endgenerate // IBUFDS for DCO IBUFDS #( - .DIFF_TERM("TRUE"), - .IOSTANDARD("LVDS_25") + .DIFF_TERM("FALSE"), // Overridden by XDC DIFF_TERM property + .IOSTANDARD("DEFAULT") // Overridden by XDC IOSTANDARD property ) ibufds_dco ( .O(adc_dco), .I(adc_dco_p), diff --git a/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc b/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc index b39c513..422587f 100644 --- a/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc +++ b/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc @@ -20,9 +20,10 @@ # DRC Fix History: # - PLIO-9: Moved clk_120m_dac from C13 (N-type) to D13 (P-type MRCC). # Clock inputs must use the P-type pin of a Multi-Region Clock-Capable pair. -# - BIVC-1: Disabled DIFF_TERM on Bank 14 LVDS pairs (adc_dco, adc_d) to -# resolve VCCO conflict with single-ended adc_pwdn (LVCMOS33) on T5. -# External 100-ohm differential termination required on board. +# - BIVC-1: Root cause was IBUFDS primitives in ad9484_interface_400m.v +# hardcoded to LVDS_25 (VCCO=2.5V), conflicting with adc_pwdn LVCMOS33 +# (VCCO=3.3V) in Bank 14. Fixed by changing RTL to IOSTANDARD("DEFAULT") +# so each target's XDC controls the standard (LVDS_33 here, LVDS_25 on 200T). # ============================================================================ # ============================================================================ @@ -54,11 +55,7 @@ set_property PACKAGE_PIN N14 [get_ports {adc_dco_p}] set_property PACKAGE_PIN P14 [get_ports {adc_dco_n}] set_property IOSTANDARD LVDS_33 [get_ports {adc_dco_p}] set_property IOSTANDARD LVDS_33 [get_ports {adc_dco_n}] -# NOTE: DIFF_TERM disabled to avoid BIVC-1 DRC conflict with single-ended -# adc_pwdn (LVCMOS33) on T5 in the same bank. The board should have external -# 100-ohm differential termination on the ADC LVDS pairs. If signal integrity -# issues arise, the board may need adc_pwdn relocated to a non-Bank-14 pin. -# set_property DIFF_TERM TRUE [get_ports {adc_dco_p}] +set_property DIFF_TERM TRUE [get_ports {adc_dco_p}] create_clock -name adc_dco_p -period 2.5 [get_ports {adc_dco_p}] set_input_jitter [get_clocks adc_dco_p] 0.05 @@ -217,10 +214,9 @@ set_property IOSTANDARD LVCMOS33 [get_ports {adc_pwdn}] set_property IOSTANDARD LVDS_33 [get_ports {adc_d_p[*]}] set_property IOSTANDARD LVDS_33 [get_ports {adc_d_n[*]}] -# Differential termination — disabled to avoid BIVC-1 DRC conflict with -# single-ended adc_pwdn (LVCMOS33) on T5 in the same bank. Requires external -# 100-ohm differential termination on the board for proper LVDS signal integrity. -# set_property DIFF_TERM TRUE [get_ports {adc_d_p[*]}] +# Differential termination — Bank 14 VCCO = 3.3V, compatible with LVDS_33. +# RTL IBUFDS uses DIFF_TERM("FALSE") so this XDC property takes precedence. +set_property DIFF_TERM TRUE [get_ports {adc_d_p[*]}] # Input delay for ADC data relative to DCO (adjust based on PCB trace length) set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 [get_ports {adc_d_p[*]}]