Update docs for Build 20 (v0.1.3-build20) stable release + Gaps 3-7 status
- release-notes.html: Add commits for Gaps 3-5-7-4, tagged releases table, architectural gap status table, updated GitHub links - implementation-log.html: Add Build 20/19/18 timeline entries, Gap 3-4-5 milestones, updated quality/build history sections - reports.html: Update FPGA status to Build 20 baseline, MCU regression to 20/20, report currency notice with current gap status
This commit is contained in:
Jason
@@ -31,29 +31,37 @@
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<h2>Recent milestone timeline</h2>
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<div class="timeline">
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<article>
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<h3>Build 16 XDC cleanup validated on production target</h3>
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<p class="muted">Remote production XDC pass eliminated XDCB-5 warnings, collapsed the large TIMING-18 bucket to a single ft601_txe residue, and preserved timing at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.</p>
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<h3>Gap 4: USB Read Path wired with toggle CDC (e5d1b3c)</h3>
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<p class="muted">FT601 read FSM cmd_* outputs connected through toggle CDC to clk_100m command decode registers in radar_system_top.v. Host can now set radar mode, trigger chirps, set CFAR threshold, and control data streaming via USB. 3 new testbench groups (55 total checks). 18/18 FPGA regression.</p>
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</article>
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<article>
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<h3>Build 15 timing-clean integration baseline established</h3>
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<p class="muted">Production-target implementation completed with all timing constraints met after USB range-profile wiring and the CFAR sequential-assignment fix.</p>
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<h3>Build 20 tagged v0.1.3-build20 — new production baseline (c6103b3)</h3>
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<p class="muted">WNS improved 7x to +0.426 ns (from +0.062 ns in Build 18). Includes 400 MHz MMCM jitter cleaner, CIC comb DSP48E1 CREG pipeline, and XDC clock-name fix. All timing constraints met. 6,092 LUTs (4.5%), 9,024 FFs (3.4%), 16 BRAM (4.4%), 140 DSP48E1 (18.9%), 0.730 W.</p>
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</article>
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<article>
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<h3>USB range profile path wired to matched-filter output</h3>
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<p class="muted">The top-level Doppler placeholder was removed from the USB range-profile path and replaced with the real matched-filter range output propagated through the receiver chain.</p>
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<h3>Build 19 timing failure root-caused and fixed</h3>
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<p class="muted">Build 19 had WNS -0.011 ns due to conflicting XDC create_generated_clock preventing false-path application on CDC paths. Fixed by removing the conflicting constraint and using Vivado auto-generated clk_mmcm_out0.</p>
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</article>
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<article>
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<h3>Gap 3: Safety Architecture closed (f3bbf77)</h3>
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<p class="muted">Added IWDG watchdog configuration, Emergency_Stop PA rail cutoff, temperature max guard, periodic IDQ re-read, and emergency state ordering. 5 new MCU tests, 20/20 MCU regression pass.</p>
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</article>
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<article>
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<h3>Gap 5: BRAM async reset fixed (c87dce0)</h3>
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<p class="muted">Chirp memory loader BRAM async reset converted to synchronous reset pattern per Xilinx UG901 guidelines. Prevents BRAM inference failures on production target.</p>
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</article>
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<article>
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<h3>Build 18 tagged v0.1.2-build18 — prior production baseline</h3>
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<p class="muted">WNS +0.062 ns, WHS +0.059 ns. 6,088 LUTs, 8,946 FFs, 16 BRAM, 140 DSP48E1, 0.631 W. All timing met.</p>
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</article>
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<article>
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<h3>Firmware bug sweep closed with regression coverage</h3>
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<p class="muted">All 17 audited MCU firmware bugs were fixed, regression-tested, and pushed, including LO init ordering, SPI chip-select handling, PA calibration logic, TIM3 PWM bring-up, and stale diagnostic mismatches.</p>
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<p class="muted">All 17 audited MCU firmware bugs were fixed, regression-tested, and pushed, including LO init ordering, SPI chip-select handling, PA calibration logic, TIM3 PWM bring-up, and stale diagnostic mismatches. 20/20 MCU tests pass.</p>
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</article>
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<article>
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<h3>FPGA timing/resource cleanup phase completed</h3>
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<p class="muted">Chirp BRAM migration, Doppler DSP48 pipelining, CIC pipeline staging, matched-filter regression repair, and full FPGA regression brought the active baseline to 18/18 passing tests.</p>
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</article>
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<article>
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<h3>Build 13 frozen as earlier hardware candidate</h3>
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<p class="muted">Historical milestone retained for traceability: WNS +0.311 ns, TNS 0.000, WHS +0.060, THS 0.000 on the production target before the later DSP and integration work.</p>
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</article>
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</div>
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</section>
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@@ -61,19 +69,21 @@
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<article class="card">
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<h2>Codebase quality and verification upgrades</h2>
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<ul>
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<li>Added comprehensive DIAG instrumentation across MCU bring-up, LO, PA, USB, and safety paths before executing the bug-fix phase.</li>
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<li>Built an STM32 HAL/mock regression harness and closed the audited firmware bug list with MCU regression passing.</li>
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<li>Ran full FPGA regression with 18/18 passing suites, including matched filter, Doppler, CIC, CDC, USB, and system-top coverage.</li>
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<li>Migrated the chirp LUT path toward BRAM, added DSP48 and CIC pipeline staging, and validated that the active FPGA baseline still meets timing.</li>
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<li>FPGA regression: 18/18 passing suites covering matched filter, Doppler, CIC, CDC, USB (with read path), FFT, NCO, FIR, range decimator, mode controller, and system-top integration.</li>
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<li>MCU regression: 20/20 passing tests (15 bug-fix + 5 Gap-3 safety tests).</li>
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<li>Architectural gaps 3, 4, 5, 7 closed with full test coverage. Gaps 1, 2, 6 deferred to post-bring-up or pre-tuning.</li>
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<li>USB host-to-FPGA command path fully wired: read FSM, toggle CDC, command decode for mode/trigger/CFAR/stream control.</li>
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<li>Safety architecture: IWDG watchdog, emergency stop PA cutoff, temperature guard, IDQ re-read, state ordering.</li>
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</ul>
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</article>
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<article class="card">
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<h2>Debug and infrastructure improvements</h2>
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<h2>Build history and timing improvements</h2>
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<ul>
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<li>Completed Build 15 production-target analysis with timing, power, route, DRC, methodology, and CDC evidence captured in the internal engineering reports.</li>
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<li>Validated a remote-only Build 16 XDC cleanup pass that removed XDCB-5, reduced TIMING-18 to a single ft601_txe methodology residue, and preserved post-route timing.</li>
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<li>Kept separate Trenz development targets while prioritizing the in-stock TE0713 path for practical hardware execution.</li>
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<li>Preserved remote Vivado baselines so timing-clean builds can be compared before and after constraint-only experiments.</li>
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<li><strong>Build 20 (v0.1.3-build20)</strong>: Current production baseline. WNS +0.426 ns, WHS +0.058 ns. 400 MHz MMCM + CIC CREG pipeline. 0.730 W.</li>
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<li><strong>Build 19</strong>: Failed (WNS -0.011 ns). Root cause: conflicting XDC generated clock prevented false-path application.</li>
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<li><strong>Build 18 (v0.1.2-build18)</strong>: Prior baseline. WNS +0.062 ns, WHS +0.059 ns. 0.631 W.</li>
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<li><strong>Build 17 (v0.1.1-build17)</strong>: FIR DSP48 pipelining + matched filter BRAM migration.</li>
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<li>Remote Vivado build infrastructure on Ubuntu 24.04 with Vivado 2025.2, targeting XC7A200T-2FBG484I.</li>
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</ul>
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</article>
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</section>
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+53
-24
@@ -40,24 +40,34 @@
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</thead>
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<tbody>
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<tr>
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<td><code>2763b4b</code></td>
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<td>CFAR sequential fix and Build 15 analysis capture</td>
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<td>Replaced the clocked-block CFAR blocking assignment with sequential logic and published the Build 15 timing/DRC/methodology analysis baseline.</td>
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<td><code>e5d1b3c</code></td>
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<td>Gap 4 USB Read Path: host-to-FPGA command path with toggle CDC</td>
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<td>Wired FT601 read FSM cmd_* outputs through toggle CDC to clk_100m command decode registers. Host can now set radar mode, trigger chirps, set CFAR threshold, and control data streaming. 3 new TB test groups (55 checks). 18/18 FPGA regression.</td>
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</tr>
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<tr>
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<td><code>3fa26c9</code></td>
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<td>USB range profile wiring completed</td>
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<td>Removed the Doppler placeholder from the USB range path and propagated real matched-filter range data through the receiver/top-level interfaces.</td>
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<td><code>c6103b3</code> <strong>v0.1.3-build20</strong></td>
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<td>Gap 7 MMCM jitter cleaner + CIC CREG pipeline + XDC clock-name fix</td>
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<td>Added 400 MHz MMCM for ADC clock jitter cleaning, CIC comb DSP48E1 CREG pipeline, and fixed XDC conflicting generated clock. Build 20: WNS +0.426 ns (7x improvement over Build 18). All timing met.</td>
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</tr>
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<tr>
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<td><code>f4ff271</code></td>
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<td>Matched-filter regression repair</td>
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<td>Corrected golden-case <code>$readmemh</code> paths so the matched-filter regression returned to 40/40 passing.</td>
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<td><code>f3bbf77</code></td>
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<td>Gap 3 Safety Architecture</td>
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<td>IWDG watchdog, Emergency_Stop PA rail cutoff, temperature max guard, periodic IDQ re-read, emergency state ordering. 5 new MCU tests, 20/20 pass.</td>
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</tr>
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<tr>
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<td><code>463ebef</code></td>
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<td>CIC pipeline staging and regression runner</td>
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<td>Added CIC comb pipeline staging, simulation guards, and an FPGA regression runner to preserve timing while tightening verification.</td>
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<td><code>c87dce0</code></td>
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<td>Gap 5 BRAM async reset fix</td>
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<td>Fixed chirp memory loader BRAM async reset to use synchronous reset pattern per Xilinx UG901 guidelines.</td>
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</tr>
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<tr>
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<td><code>3b7afba</code> <strong>v0.1.2-build18</strong></td>
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<td>Build 18 production build</td>
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<td>Production baseline: WNS +0.062 ns, WHS +0.059 ns. 6,088 LUTs, 8,946 FFs, 16 BRAM, 140 DSP48E1, 0.631 W.</td>
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</tr>
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<tr>
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<td><code>ed6f79c</code> <strong>v0.1.1-build17</strong></td>
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<td>FIR DSP48 pipelining + matched filter BRAM migration</td>
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<td>Build 17 production build with DSP48 pipelining improvements.</td>
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</tr>
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<tr>
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<td><code>c466021</code></td>
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@@ -85,25 +95,44 @@
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Uncommitted validated work</h2>
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<h2>Tagged releases</h2>
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<ul>
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<li>Build 16 remote production-XDC cleanup has been validated in the remote Vivado workspace but is not yet represented by a git commit.</li>
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<li>The remote-only pass removed XDCB-5 warnings, reduced the large TIMING-18 bucket to a single <code>ft601_txe</code> methodology residue, and preserved timing at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.</li>
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<li>The surviving <code>ft601_txe</code> item currently behaves like a methodology residue on an async status-observation path rather than a proven unconstrained functional FT601 interface.</li>
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<li><strong>v0.1.3-build20</strong> (c6103b3) — Current production baseline. WNS +0.426 ns, all timing met. Includes Gaps 3, 5, 7.</li>
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<li><strong>v0.1.2-build18</strong> (3b7afba) — Prior production baseline. WNS +0.062 ns.</li>
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<li><strong>v0.1.1-build17</strong> (ed6f79c) — FIR DSP48 + BRAM migration build.</li>
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<li><strong>v0.1.0-bringup</strong> — Initial bring-up tag.</li>
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</ul>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Architectural gap status</h2>
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<div class="table-wrap">
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<table>
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<thead><tr><th>#</th><th>Gap</th><th>Status</th></tr></thead>
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<tbody>
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<tr><td>3</td><td>Safety Architecture</td><td>Done (f3bbf77)</td></tr>
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<tr><td>5</td><td>BRAM Async Reset</td><td>Done (c87dce0)</td></tr>
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<tr><td>7</td><td>400 MHz MMCM</td><td>Done (c6103b3, Build 20)</td></tr>
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<tr><td>4</td><td>USB Read Path</td><td>Done (e5d1b3c)</td></tr>
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<tr><td>2</td><td>GUI Settings</td><td>Next</td></tr>
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<tr><td>6</td><td>CDC-15 USB Buses</td><td>Post-bring-up</td></tr>
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<tr><td>1</td><td>CFAR Real Implementation</td><td>Post-bring-up</td></tr>
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</tbody>
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</table>
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</div>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Open in GitHub</h2>
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<ul>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/2763b4b" target="_blank" rel="noopener">2763b4b</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3fa26c9" target="_blank" rel="noopener">3fa26c9</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/f4ff271" target="_blank" rel="noopener">f4ff271</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/463ebef" target="_blank" rel="noopener">463ebef</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c466021" target="_blank" rel="noopener">c466021</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/49c9aa2" target="_blank" rel="noopener">49c9aa2</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3b32f67" target="_blank" rel="noopener">3b32f67</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3979693" target="_blank" rel="noopener">3979693</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/e5d1b3c" target="_blank" rel="noopener">e5d1b3c</a> Gap 4 USB Read Path</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c6103b3" target="_blank" rel="noopener">c6103b3</a> Gap 7 MMCM + CREG (v0.1.3-build20)</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/f3bbf77" target="_blank" rel="noopener">f3bbf77</a> Gap 3 Safety Architecture</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c87dce0" target="_blank" rel="noopener">c87dce0</a> Gap 5 BRAM Reset</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c466021" target="_blank" rel="noopener">c466021</a> Firmware bugs B12-B17</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/49c9aa2" target="_blank" rel="noopener">49c9aa2</a> SPI + FPGA timing</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3b32f67" target="_blank" rel="noopener">3b32f67</a> ADF4382A SPI</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3979693" target="_blank" rel="noopener">3979693</a> Initial 8-bug closure</li>
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</ul>
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</section>
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</main>
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+13
-11
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<section class="card" style="margin-top:0.8rem;">
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<h2>Current FPGA implementation status</h2>
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<ul>
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<li>Build 15 is the current detailed analysis baseline for the production XC7A200T target and completed with all timing constraints met.</li>
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<li>Build 16 was validated in the remote Vivado workspace as a constraint-cleanup pass: XDCB-5 warnings were removed, the large TIMING-18 bucket collapsed to a single <code>ft601_txe</code> methodology residue, and routed timing remained clean at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.</li>
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<li>The remaining <code>ft601_txe</code> methodology item currently behaves like an async-status-observation residue rather than a proven unconstrained functional FT601 path.</li>
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<li><strong>Build 20 (v0.1.3-build20)</strong> is the current production baseline for the XC7A200T target. All timing constraints met: WNS +0.426 ns, WHS +0.058 ns, WPWS +0.361 ns.</li>
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<li>Utilization: 6,092 LUTs (4.5%), 9,024 FFs (3.4%), 16 BRAM (4.4%), 140 DSP48E1 (18.9%), 0.730 W total power.</li>
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<li>Key improvements over Build 18: 400 MHz MMCM jitter cleaner, CIC comb DSP48E1 CREG pipeline, XDC clock-name fix. Setup slack improved 7x.</li>
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<li>Build 20 reports are available on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build20/</code>.</li>
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</ul>
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</section>
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@@ -57,7 +58,7 @@
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<tr><td>FPGA programming flow</td><td><code>9_Firmware/9_2_FPGA/scripts/program_fpga.tcl</code></td><td>Programs the device and reports DONE / INIT_COMPLETE / probes presence</td><td>Primary operator-facing programming script</td></tr>
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<tr><td>Debug probe insertion flow</td><td><code>9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl</code></td><td>Used when generating or refreshing debug-capable images</td><td>Keep matched with the selected debug bitstream</td></tr>
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<tr><td>FPGA regression runner</td><td><code>9_Firmware/9_2_FPGA/run_regression.sh</code></td><td>Pre-arrival regression evidence for the tracked FPGA baseline</td><td>18 / 18 passing on the current tracked branch</td></tr>
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<tr><td>MCU regression harness</td><td><code>9_Firmware/9_1_Microcontroller/tests/Makefile</code></td><td>Pre-arrival firmware regression evidence before flashing hardware</td><td>15 / 15 passing on the current tracked branch</td></tr>
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<tr><td>MCU regression harness</td><td><code>9_Firmware/9_1_Microcontroller/tests/Makefile</code></td><td>Pre-arrival firmware regression evidence before flashing hardware</td><td>20 / 20 passing on the current tracked branch</td></tr>
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<tr><td>Bring-up logging macros</td><td><code>9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h</code></td><td>Defines the main first-power-on log vocabulary used over USART3</td><td>Observation-only instrumentation layer</td></tr>
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<tr><td>Board-day worksheet</td><td><code>docs/board-day-worksheet.html</code></td><td>Record pass/fail, measurements, and blockers during first sessions</td><td>Use with this page and the bring-up plan</td></tr>
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<tr><td>Bring-up execution plan</td><td><code>docs/bring-up.html</code></td><td>Operator checklist, abort criteria, observability targets, and open risks</td><td>Primary readiness document</td></tr>
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@@ -91,9 +92,9 @@
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<section class="card" style="margin-top:0.8rem;">
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<h2>FPGA implementation analysis</h2>
|
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<p><span class="chip">Status: Current engineering baseline</span></p>
|
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<p class="muted">Primary detailed write-up: internal Build 15 implementation analysis captured timing, power, route status, DRC, methodology, CDC, and utilization for the production-target design after USB range wiring and CFAR cleanup.</p>
|
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<p class="muted">Follow-on Build 16 remote validation focused on production XDC cleanup only and confirmed no timing regression while reducing methodology noise substantially.</p>
|
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<p><span class="chip">Status: Current engineering baseline — Build 20 (v0.1.3-build20)</span></p>
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<p class="muted">Build 20 is the current production baseline. Full timing, utilization, power, DRC, methodology, CDC, and route reports are available on the remote Vivado host. Setup slack improved 7x from Build 18 (+0.062 ns to +0.426 ns) via MMCM jitter cleaner, CIC CREG pipeline, and XDC clock-name fix.</p>
|
||||
<p class="muted">Build 18 (v0.1.2-build18) retained as prior reference. Build 19 failed timing (WNS -0.011 ns) due to conflicting XDC generated clock, root-caused and fixed in Build 20.</p>
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||||
</section>
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||||
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<section class="card" style="margin-top:0.8rem;">
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@@ -110,10 +111,11 @@
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<section class="card" style="margin-top:0.8rem;">
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<h2>Report Currency Notice</h2>
|
||||
<ul>
|
||||
<li>The current routed production-target baseline is Build 15, with Build 16 used as a remote-only XDC cleanup validation pass.</li>
|
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<li>The latest public simulation PDF should be interpreted alongside the implementation log and release notes for the most accurate state of firmware bug closure and FPGA integration readiness.</li>
|
||||
<li>Detailed Build 15 and Build 16 engineering notes currently live in internal working reports and remote Vivado artifacts rather than this public docs directory.</li>
|
||||
<li>The artifact inventory above is intended to stabilize day-0 execution even when the detailed internal engineering reports stay outside the public docs site.</li>
|
||||
<li>The current routed production-target baseline is <strong>Build 20 (v0.1.3-build20)</strong> with all timing constraints met and 7x setup slack improvement over Build 18.</li>
|
||||
<li>Architectural gaps 3 (Safety), 4 (USB Read Path), 5 (BRAM Reset), and 7 (MMCM) are closed. Gaps 1 (CFAR), 2 (GUI), and 6 (CDC-15) remain for post-bring-up or pre-tuning.</li>
|
||||
<li>FPGA regression: 18/18 pass. MCU regression: 20/20 pass (15 bug-fix + 5 Gap-3 safety).</li>
|
||||
<li>Detailed Build 20 engineering reports are on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build20/</code>.</li>
|
||||
<li>The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.</li>
|
||||
</ul>
|
||||
</section>
|
||||
|
||||
|
||||
Reference in New Issue
Block a user