Update docs for Build 20 (v0.1.3-build20) stable release + Gaps 3-7 status
- release-notes.html: Add commits for Gaps 3-5-7-4, tagged releases table, architectural gap status table, updated GitHub links - implementation-log.html: Add Build 20/19/18 timeline entries, Gap 3-4-5 milestones, updated quality/build history sections - reports.html: Update FPGA status to Build 20 baseline, MCU regression to 20/20, report currency notice with current gap status
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Jason
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<td><code>2763b4b</code></td>
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<td>CFAR sequential fix and Build 15 analysis capture</td>
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<td>Replaced the clocked-block CFAR blocking assignment with sequential logic and published the Build 15 timing/DRC/methodology analysis baseline.</td>
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<td><code>e5d1b3c</code></td>
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<td>Gap 4 USB Read Path: host-to-FPGA command path with toggle CDC</td>
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<td>Wired FT601 read FSM cmd_* outputs through toggle CDC to clk_100m command decode registers. Host can now set radar mode, trigger chirps, set CFAR threshold, and control data streaming. 3 new TB test groups (55 checks). 18/18 FPGA regression.</td>
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<td><code>3fa26c9</code></td>
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<td>USB range profile wiring completed</td>
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<td>Removed the Doppler placeholder from the USB range path and propagated real matched-filter range data through the receiver/top-level interfaces.</td>
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<td><code>c6103b3</code> <strong>v0.1.3-build20</strong></td>
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<td>Gap 7 MMCM jitter cleaner + CIC CREG pipeline + XDC clock-name fix</td>
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<td>Added 400 MHz MMCM for ADC clock jitter cleaning, CIC comb DSP48E1 CREG pipeline, and fixed XDC conflicting generated clock. Build 20: WNS +0.426 ns (7x improvement over Build 18). All timing met.</td>
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<td><code>f4ff271</code></td>
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<td>Matched-filter regression repair</td>
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<td>Corrected golden-case <code>$readmemh</code> paths so the matched-filter regression returned to 40/40 passing.</td>
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<td><code>f3bbf77</code></td>
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<td>Gap 3 Safety Architecture</td>
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<td>IWDG watchdog, Emergency_Stop PA rail cutoff, temperature max guard, periodic IDQ re-read, emergency state ordering. 5 new MCU tests, 20/20 pass.</td>
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<td><code>463ebef</code></td>
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<td>CIC pipeline staging and regression runner</td>
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<td>Added CIC comb pipeline staging, simulation guards, and an FPGA regression runner to preserve timing while tightening verification.</td>
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<td><code>c87dce0</code></td>
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<td>Gap 5 BRAM async reset fix</td>
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<td>Fixed chirp memory loader BRAM async reset to use synchronous reset pattern per Xilinx UG901 guidelines.</td>
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<td><code>3b7afba</code> <strong>v0.1.2-build18</strong></td>
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<td>Build 18 production build</td>
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<td>Production baseline: WNS +0.062 ns, WHS +0.059 ns. 6,088 LUTs, 8,946 FFs, 16 BRAM, 140 DSP48E1, 0.631 W.</td>
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<td><code>ed6f79c</code> <strong>v0.1.1-build17</strong></td>
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<td>FIR DSP48 pipelining + matched filter BRAM migration</td>
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<td>Build 17 production build with DSP48 pipelining improvements.</td>
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<tr>
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<td><code>c466021</code></td>
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@@ -85,25 +95,44 @@
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Uncommitted validated work</h2>
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<h2>Tagged releases</h2>
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<ul>
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<li>Build 16 remote production-XDC cleanup has been validated in the remote Vivado workspace but is not yet represented by a git commit.</li>
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<li>The remote-only pass removed XDCB-5 warnings, reduced the large TIMING-18 bucket to a single <code>ft601_txe</code> methodology residue, and preserved timing at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.</li>
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<li>The surviving <code>ft601_txe</code> item currently behaves like a methodology residue on an async status-observation path rather than a proven unconstrained functional FT601 interface.</li>
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<li><strong>v0.1.3-build20</strong> (c6103b3) — Current production baseline. WNS +0.426 ns, all timing met. Includes Gaps 3, 5, 7.</li>
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<li><strong>v0.1.2-build18</strong> (3b7afba) — Prior production baseline. WNS +0.062 ns.</li>
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<li><strong>v0.1.1-build17</strong> (ed6f79c) — FIR DSP48 + BRAM migration build.</li>
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<li><strong>v0.1.0-bringup</strong> — Initial bring-up tag.</li>
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</ul>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Architectural gap status</h2>
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<div class="table-wrap">
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<table>
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<thead><tr><th>#</th><th>Gap</th><th>Status</th></tr></thead>
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<tbody>
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<tr><td>3</td><td>Safety Architecture</td><td>Done (f3bbf77)</td></tr>
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<tr><td>5</td><td>BRAM Async Reset</td><td>Done (c87dce0)</td></tr>
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<tr><td>7</td><td>400 MHz MMCM</td><td>Done (c6103b3, Build 20)</td></tr>
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<tr><td>4</td><td>USB Read Path</td><td>Done (e5d1b3c)</td></tr>
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<tr><td>2</td><td>GUI Settings</td><td>Next</td></tr>
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<tr><td>6</td><td>CDC-15 USB Buses</td><td>Post-bring-up</td></tr>
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<tr><td>1</td><td>CFAR Real Implementation</td><td>Post-bring-up</td></tr>
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</tbody>
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</table>
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</div>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Open in GitHub</h2>
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<ul>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/2763b4b" target="_blank" rel="noopener">2763b4b</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3fa26c9" target="_blank" rel="noopener">3fa26c9</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/f4ff271" target="_blank" rel="noopener">f4ff271</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/463ebef" target="_blank" rel="noopener">463ebef</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c466021" target="_blank" rel="noopener">c466021</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/49c9aa2" target="_blank" rel="noopener">49c9aa2</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3b32f67" target="_blank" rel="noopener">3b32f67</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3979693" target="_blank" rel="noopener">3979693</a></li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/e5d1b3c" target="_blank" rel="noopener">e5d1b3c</a> Gap 4 USB Read Path</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c6103b3" target="_blank" rel="noopener">c6103b3</a> Gap 7 MMCM + CREG (v0.1.3-build20)</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/f3bbf77" target="_blank" rel="noopener">f3bbf77</a> Gap 3 Safety Architecture</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c87dce0" target="_blank" rel="noopener">c87dce0</a> Gap 5 BRAM Reset</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c466021" target="_blank" rel="noopener">c466021</a> Firmware bugs B12-B17</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/49c9aa2" target="_blank" rel="noopener">49c9aa2</a> SPI + FPGA timing</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3b32f67" target="_blank" rel="noopener">3b32f67</a> ADF4382A SPI</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3979693" target="_blank" rel="noopener">3979693</a> Initial 8-bug closure</li>
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</ul>
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</section>
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</main>
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