add TE0713 heartbeat bring-up artifact
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Jason
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<!doctype markdown>
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# TE0713/TE0701 heartbeat bring-up artifact
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- Date: 2026-03-21
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- Target: Trenz `TE0713-03-82C46-A` on `TE0701-06`
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- Top module: `radar_system_top_te0713_dev`
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- Constraint file: `9_Firmware/9_2_FPGA/constraints/te0713_te0701_minimal.xdc`
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- Bitstream: `docs/artifacts/te0713-te0701-heartbeat-2026-03-21.bit`
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Build result:
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- Vivado: `2025.2`
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- Implementation: `write_bitstream Complete!`
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- DRC: `0 Errors`
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- WNS: `+17.863 ns`
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- WHS: `+0.265 ns`
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Purpose:
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- Lowest-risk first-power image for `TE0713 + TE0701`
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- Verifies FPGA configuration, primary clock path, and heartbeat/status outputs before FT601 or radar-path bring-up
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Board-day usage:
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- Program this image first
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- Confirm JTAG enumeration and successful configuration
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- Verify heartbeat/status activity before moving to FT601 or higher-risk integrations
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Build origin:
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- Built remotely on `livepeerservice.ddns.net`
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- Vivado path: `/mnt/bcache/Xilinx/Vivado/2025.2/Vivado/bin/vivado`
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+4
-4
@@ -44,7 +44,7 @@
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</tr>
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</thead>
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<tbody>
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<tr><td>1</td><td>Freeze known-good firmware and bitstream baselines</td><td>Tracked commit, named artifact set, and repeatable programming flow are available</td><td>Git commit, bitstream path, reports, programming TCL</td></tr>
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<tr><td>1</td><td>Freeze known-good firmware and bitstream baselines</td><td>Tracked commit, named artifact set, and repeatable programming flow are available</td><td>Git commit, bitstream path, reports, programming TCL; current heartbeat image at <code>docs/artifacts/te0713-te0701-heartbeat-2026-03-21.bit</code></td></tr>
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<tr><td>2</td><td>Preserve clean implementation constraints</td><td>Positive WNS/WHS/WPWS, XDCB-5 cleared, only documented methodology residue remains</td><td>Timing summary and methodology report</td></tr>
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<tr><td>3</td><td>Keep regressions green before board arrival</td><td>MCU host tests and FPGA regression/integration suites pass on the tracked tree</td><td>15/15 MCU and 18/18 FPGA logs</td></tr>
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<tr><td>4</td><td>Make first-power-on behavior observable</td><td>Clock, LO, beamformer, PA, and USB status can be identified from logs or status outputs</td><td>DIAG coverage, status fields, ILA/debug plan</td></tr>
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@@ -111,7 +111,7 @@
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<h2>Required artifacts before hardware arrives</h2>
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<ul>
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<li>Named firmware baseline commit and build instructions for the MCU image.</li>
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<li>Named FPGA baseline bitstream and matching `.ltx` probes file for debug sessions.</li>
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<li>Named FPGA baseline bitstream and matching `.ltx` probes file for debug sessions; current low-risk heartbeat artifact is <code>docs/artifacts/te0713-te0701-heartbeat-2026-03-21.bit</code>.</li>
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<li>Current production-target XDC, timing summary, and methodology report.</li>
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<li>Programming and debug TCL scripts for baseline and debug images.</li>
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<li>Regression evidence for the tracked branch: MCU host suite and FPGA regression/integration suite.</li>
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@@ -122,7 +122,7 @@
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<article class="card">
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<h2>Host-side tools and workflows</h2>
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<ul>
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<li>JTAG programming workflow using the checked-in Vivado TCL scripts.</li>
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<li>JTAG programming workflow using the checked-in Vivado TCL scripts and the TE0713 heartbeat baseline built on 2026-03-21.</li>
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<li>Serial capture on USART3 with timestamps preserved for bring-up logs.</li>
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<li>FT601 or host-side USB capture/decoder workflow to validate framing and payload stability.</li>
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<li>ILA capture workflow for raw ADC, DDC, matched-filter, and USB-domain checkpoints.</li>
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@@ -148,7 +148,7 @@
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<tr><td>RF control-path realism</td><td>Firmware sequencing and diagnostics improved, but LO sync, phase behavior, and beamformer control still require physical validation.</td><td>Use readback-first bring-up and do not assume analog behavior from simulation or logs alone.</td></tr>
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<tr><td>Prototype-grade top-level functional assumptions</td><td>The active FPGA baseline is regression-clean, but some radar-function behavior still needs real-board confirmation under actual I/O conditions.</td><td>Validate each data-path stage incrementally with ILA and host captures before full streaming claims.</td></tr>
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<tr><td>PA calibration boundaries</td><td>IDQ calibration logic is much safer than before, but real-device convergence and margin limits are not yet board-proven.</td><td>Use conservative limits, observe every channel, and stop on abnormal current or non-convergent channels.</td></tr>
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<tr><td>Board-specific integration unknowns</td><td>Carrier/module interaction, rails, clocks, and connector assumptions remain partially unproven until first assembly.</td><td>Begin with lowest-risk heartbeat and configuration checks before enabling higher-energy subsystems.</td></tr>
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<tr><td>Board-specific integration unknowns</td><td>Carrier/module interaction, rails, clocks, and connector assumptions remain partially unproven until first assembly.</td><td>Begin with the tracked TE0713/TE0701 heartbeat image and configuration checks before enabling higher-energy subsystems.</td></tr>
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</tbody>
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</table>
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</div>
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@@ -39,6 +39,11 @@
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</tr>
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</thead>
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<tbody>
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<tr>
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<td><code>TBD</code> <strong>v0.1.7-te0713-heartbeat</strong></td>
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<td>TE0713/TE0701 minimal heartbeat bring-up bitstream</td>
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<td>Created a low-risk bring-up artifact for the Trenz TE0713 + TE0701 stack using <code>radar_system_top_te0713_dev</code> and <code>te0713_te0701_minimal.xdc</code>. Remote Vivado 2025.2 build completed with DRC 0 errors, WNS +17.863 ns, WHS +0.265 ns. Intended as the first board-day image before FT601 arrival and before any radar-path integration.</td>
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</tr>
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<tr>
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<td><code>ed629e7</code> <strong>v0.1.6-mti</strong></td>
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<td>Build 25: MTI canceller + DC notch filter integration</td>
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@@ -132,6 +137,7 @@
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<section class="card" style="margin-top:0.8rem;">
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<h2>Tagged releases</h2>
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<ul>
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<li><strong>v0.1.7-te0713-heartbeat</strong> — TE0713/TE0701 first-power baseline. Minimal heartbeat top, DRC clean, WNS +17.863 ns, WHS +0.265 ns. Artifact tracked at <code>docs/artifacts/te0713-te0701-heartbeat-2026-03-21.bit</code>.</li>
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<li><strong>v0.1.6-mti</strong> (ed629e7) — Current production baseline. WNS +0.132 ns, WHS +0.058 ns. MTI canceller + DC notch filter. 9,252 LUTs, 12,488 FFs, 142 DSP48E1, 17 BRAM. 0.753 W.</li>
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<li><strong>v0.1.5-cfar</strong> (075ae1e) — Prior production baseline. WNS +0.179 ns. CA-CFAR detector (CA/GO/SO modes) with pipelined noise computation.</li>
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<li><strong>v0.1.4-prod-fixes</strong> (e93bc33) — 7 production fixes + real-data co-sim framework. WNS same as Build 21 (simulation-only changes).</li>
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