Expand GitHub Pages into full engineering documentation site

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<!doctype html>
<html lang="en">
<head>
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1">
<title>AERIS-10 Docs | Architecture</title>
<link rel="stylesheet" href="assets/style.css">
</head>
<body>
<header class="topbar">
<div class="container nav">
<a class="brand" href="index.html">AERIS-10 Docs</a>
<nav>
<a href="architecture.html">Architecture</a>
<a href="implementation-log.html">Implementation Log</a>
<a href="bring-up.html">Bring-Up</a>
<a href="reports.html">Reports</a>
</nav>
</div>
</header>
<main class="container page">
<section class="hero">
<p class="eyebrow">System View</p>
<h1>Architecture and Data Path</h1>
<p>Hardware and firmware structure for the current XC7A200T implementation and bring-up targets.</p>
</section>
<section class="grid-2">
<article class="card">
<h2>Top-level processing flow</h2>
<div class="table-wrap">
<table>
<thead>
<tr>
<th>Stage</th>
<th>Module Focus</th>
<th>Notes</th>
</tr>
</thead>
<tbody>
<tr>
<td>ADC capture</td>
<td>AD9484 interface + CDC edge</td>
<td>400 MHz sampling domain, synchronized into processing pipeline.</td>
</tr>
<tr>
<td>DDC</td>
<td>NCO + CIC + FIR</td>
<td>I/Q conversion and decimation for baseband-ready stream.</td>
</tr>
<tr>
<td>Matched filter</td>
<td>FFT-based chain</td>
<td>Synthesis branch is golden for hardware-equivalent co-sim.</td>
</tr>
<tr>
<td>Range/Doppler</td>
<td>Range bin decimator + Doppler FFT</td>
<td>32 chirps/frame, 64 range bins, deterministic frame outputs.</td>
</tr>
<tr>
<td>Host path</td>
<td>FT601 interface</td>
<td>USB streaming with framing and soak validation in bring-up.</td>
</tr>
</tbody>
</table>
</div>
</article>
<article class="card">
<h2>Current target split strategy</h2>
<ul>
<li>Production target remains <code>xc7a200t-2fbg484i</code> with full board constraints.</li>
<li>TE0712/TE0701 and TE0713/TE0701 use dedicated top wrappers and dedicated XDC files.</li>
<li>Board-specific pinouts are isolated from core DSP modules to avoid accidental cross-target regression.</li>
<li>Bring-up sequence starts from minimal heartbeat top, then steps into full signal chain validation.</li>
</ul>
</article>
</section>
<section class="card" style="margin-top:0.8rem;">
<h2>Reference block diagram</h2>
<img class="diagram" src="assets/img/RADAR_V6.jpg" alt="AERIS-10 system architecture diagram">
<p class="muted">Diagram snapshot from AERIS-10 project architecture.</p>
</section>
</main>
<footer class="footer">
<div class="container"><p>Architecture is updated as bring-up and integration milestones complete.</p></div>
</footer>
</body>
</html>
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<!doctype html>
<html lang="en">
<head>
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1">
<title>AERIS-10 Docs | Bring-Up</title>
<link rel="stylesheet" href="assets/style.css">
</head>
<body>
<header class="topbar">
<div class="container nav">
<a class="brand" href="index.html">AERIS-10 Docs</a>
<nav>
<a href="architecture.html">Architecture</a>
<a href="implementation-log.html">Implementation Log</a>
<a href="bring-up.html">Bring-Up</a>
<a href="reports.html">Reports</a>
</nav>
</div>
</header>
<main class="container page">
<section class="hero">
<p class="eyebrow">Execution Checklist</p>
<h1>Hardware Bring-Up Plan</h1>
<p>Operational sequence and pass/fail gates for Day-1 and post-Day-1 validation.</p>
</section>
<section class="card" style="margin-top:0.8rem;">
<h2>Bring-up gates</h2>
<div class="table-wrap">
<table>
<thead>
<tr>
<th>Step</th>
<th>Objective</th>
<th>Pass Criteria</th>
</tr>
</thead>
<tbody>
<tr><td>1</td><td>Program baseline bitstream</td><td>JTAG detect + successful configuration</td></tr>
<tr><td>2</td><td>Clock/reset sanity</td><td>Stable clocks and deterministic reset release</td></tr>
<tr><td>3</td><td>ADC front-end</td><td>Valid raw data visible in ILA on expected clock</td></tr>
<tr><td>4</td><td>DDC verification</td><td>Expected valid strobe and non-zero I/Q outputs</td></tr>
<tr><td>5</td><td>Matched filter stage</td><td>Range profile valid asserted and segment flow correct</td></tr>
<tr><td>6</td><td>Range/Doppler pipeline</td><td>Deterministic frame outputs with full bin coverage</td></tr>
<tr><td>7</td><td>USB host link</td><td>Sustained transfer and stable framing over soak window</td></tr>
<tr><td>8</td><td>Thermal/power screen</td><td>No rail anomalies or thermal runaway under load</td></tr>
</tbody>
</table>
</div>
</section>
<section class="grid-2" style="margin-top:0.8rem;">
<article class="card">
<h2>Day-1 quick sequence</h2>
<ol>
<li>Mount SoM on carrier and verify supply/jumper defaults.</li>
<li>Program minimal heartbeat top for immediate hardware liveness check.</li>
<li>Program debug bitstream and attach LTX for ILA sessions.</li>
<li>Capture first ADC and DDC traces, compare with expected signatures.</li>
</ol>
</article>
<article class="card">
<h2>Risk controls</h2>
<ul>
<li>Keep production target untouched; use split dev targets for carrier-specific pinouts.</li>
<li>Do not rely on RTL hierarchical net names in post-synth debug scripts.</li>
<li>Run timing/CDC/exceptions checks after every target migration update.</li>
<li>Use a repeatable program-capture checklist to detect intermittent reset/clock issues.</li>
</ul>
</article>
</section>
</main>
<footer class="footer">
<div class="container"><p>This checklist is the operational source of truth for hardware execution.</p></div>
</footer>
</body>
</html>
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<!doctype html>
<html lang="en">
<head>
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1">
<title>AERIS-10 Docs | Implementation Log</title>
<link rel="stylesheet" href="assets/style.css">
</head>
<body>
<header class="topbar">
<div class="container nav">
<a class="brand" href="index.html">AERIS-10 Docs</a>
<nav>
<a href="architecture.html">Architecture</a>
<a href="implementation-log.html">Implementation Log</a>
<a href="bring-up.html">Bring-Up</a>
<a href="reports.html">Reports</a>
</nav>
</div>
</header>
<main class="container page">
<section class="hero">
<p class="eyebrow">Engineering Journal</p>
<h1>Implementation Timeline and Improvements</h1>
<p>Consolidated record of key firmware, timing, debug and infrastructure changes.</p>
</section>
<section class="card" style="margin-top:0.8rem;">
<h2>Recent milestone timeline</h2>
<div class="timeline">
<article>
<h3>Build 13 frozen as hardware candidate</h3>
<p class="muted">WNS +0.311 ns, TNS 0.000, WHS +0.060, THS 0.000 on production target.</p>
</article>
<article>
<h3>CDC analysis completed with waivers</h3>
<p class="muted">5 critical warnings verified as false positives and documented as waivers.</p>
</article>
<article>
<h3>ILA insertion flow hardened</h3>
<p class="muted">Added net discovery pass, deferred core creation, and Vivado 2025.2 MU_CNT handling.</p>
</article>
<article>
<h3>Bring-up scripts and bitstreams generated</h3>
<p class="muted">Baseline + debug bitstreams, programming script, and ILA capture script prepared.</p>
</article>
<article>
<h3>Target split for Trenz development path</h3>
<p class="muted">Added TE0712 and TE0713 separate top wrappers/XDC/build scripts to isolate pinout differences.</p>
</article>
</div>
</section>
<section class="grid-2" style="margin-top:0.8rem;">
<article class="card">
<h2>Codebase quality and verification upgrades</h2>
<ul>
<li>Expanded simulation and co-simulation coverage with golden comparison workflows.</li>
<li>Formal verification executed across critical modules with passing results.</li>
<li>Improved reset strategy in key blocks to reduce async-reset related methodology warnings.</li>
<li>Renamed latency buffer module for maintainability and consistent references.</li>
</ul>
</article>
<article class="card">
<h2>Debug and infrastructure improvements</h2>
<ul>
<li>Post-synthesis net-name mapping documented to avoid brittle ILA net paths.</li>
<li>Generated both no-ILA and ILA debug bitstreams for staged bring-up.</li>
<li>Added dedicated scripts for TE0712/TE0713 split builds.</li>
<li>Created community issue to crowdsource compatible hardware test execution.</li>
</ul>
</article>
</section>
</main>
<footer class="footer">
<div class="container"><p>Update this page at each major commit or bring-up gate.</p></div>
</footer>
</body>
</html>
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<head>
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1">
<title>AERIS-10 Simulation Reports</title>
<style>
:root {
--bg: #0f172a;
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</style>
<title>AERIS-10 Engineering Docs</title>
<link rel="stylesheet" href="assets/style.css">
</head>
<body>
<main class="wrap">
<header class="topbar">
<div class="container nav">
<a class="brand" href="index.html">AERIS-10 Docs</a>
<nav>
<a href="architecture.html">Architecture</a>
<a href="implementation-log.html">Implementation Log</a>
<a href="bring-up.html">Bring-Up</a>
<a href="reports.html">Reports</a>
</nav>
</div>
</header>
<main class="container page">
<section class="hero">
<h1>AERIS-10 Public Simulation Reports</h1>
<p class="sub">GitHub Pages landing for antenna and Python simulation report artifacts.</p>
<p class="eyebrow">Open-Source Phased Array Radar</p>
<h1>Engineering Documentation Site</h1>
<p>This site tracks architecture, FPGA improvements, timing closure outcomes, and hardware bring-up readiness for AERIS-10.</p>
<div class="cta-row">
<a class="button" href="implementation-log.html">View Change Timeline</a>
<a class="button ghost" href="bring-up.html">Open Bring-Up Checklist</a>
</div>
</section>
<section class="grid">
<article class="card">
<h2>Antenna Simulation Report</h2>
<p class="meta">Document: <code>AERIS_Antenna_Report.pdf</code></p>
<div class="btns">
<a class="btn" href="AERIS_Antenna_Report.pdf" target="_blank" rel="noopener">Open PDF</a>
<a class="btn alt" href="AERIS_Antenna_Report.pdf" download>Download</a>
</div>
<section class="stats-grid">
<article class="card stat">
<h2>Build 13 Timing</h2>
<p class="metric">WNS +0.311 ns</p>
<p class="muted">TNS 0.000, WHS +0.060, THS 0.000</p>
</article>
<article class="card">
<h2>Python Simulation Report</h2>
<p class="meta">Document: <code>AERIS_Simulation_Report.pdf</code></p>
<div class="btns">
<a class="btn" href="AERIS_Simulation_Report.pdf" target="_blank" rel="noopener">Open PDF</a>
<a class="btn alt" href="AERIS_Simulation_Report.pdf" download>Download</a>
</div>
<article class="card stat">
<h2>Regression Status</h2>
<p class="metric">13 / 13 Suites</p>
<p class="muted">Integration golden match: 2048 / 2048</p>
</article>
<article class="card stat">
<h2>Debug Instrumentation</h2>
<p class="metric">4 ILA Cores</p>
<p class="muted">92 probe bits, 4096 depth</p>
</article>
<article class="card stat">
<h2>Current Phase</h2>
<p class="metric">Hardware Bring-Up</p>
<p class="muted">TE0712/TE0713 split targets prepared</p>
</article>
</section>
<p class="foot">Tip: In GitHub, enable Pages on the <code>main</code> branch with source folder <code>/docs</code>.</p>
<section class="grid-2">
<article class="card">
<h2>What changed recently</h2>
<ul>
<li>Closed timing on XC7A200T target and froze Build 13 candidate.</li>
<li>Added CDC waivers for 5 verified false positives.</li>
<li>Created resilient ILA insertion flow with post-synthesis net discovery.</li>
<li>Generated baseline and debug bitstreams for bring-up.</li>
<li>Added TE0712/TE0701 and TE0713/TE0701 split build targets.</li>
</ul>
</article>
<article class="card">
<h2>Documentation Map</h2>
<ul>
<li><a href="architecture.html">System and FPGA Architecture</a></li>
<li><a href="implementation-log.html">Detailed Engineering Change Log</a></li>
<li><a href="bring-up.html">Hardware Bring-Up Plan and Exit Criteria</a></li>
<li><a href="reports.html">Antenna/Python reports and generated artifacts</a></li>
</ul>
</article>
</section>
</main>
<footer class="footer">
<div class="container">
<p>AERIS-10 documentation published via GitHub Pages from <code>/docs</code>.</p>
</div>
</footer>
</body>
</html>
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<!doctype html>
<html lang="en">
<head>
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1">
<title>AERIS-10 Docs | Reports</title>
<link rel="stylesheet" href="assets/style.css">
</head>
<body>
<header class="topbar">
<div class="container nav">
<a class="brand" href="index.html">AERIS-10 Docs</a>
<nav>
<a href="architecture.html">Architecture</a>
<a href="implementation-log.html">Implementation Log</a>
<a href="bring-up.html">Bring-Up</a>
<a href="reports.html">Reports</a>
</nav>
</div>
</header>
<main class="container page">
<section class="hero">
<p class="eyebrow">Artifacts</p>
<h1>Published Reports and Visuals</h1>
<p>Central access point for antenna simulations, Python simulation outputs, and visuals.</p>
</section>
<section class="grid-2" style="margin-top:0.8rem;">
<article class="card">
<h2>Antenna Simulation Report</h2>
<p class="muted">File: <code>AERIS_Antenna_Report.pdf</code></p>
<p>
<a class="button" href="AERIS_Antenna_Report.pdf" target="_blank" rel="noopener">Open PDF</a>
<a class="button ghost" href="AERIS_Antenna_Report.pdf" download>Download</a>
</p>
</article>
<article class="card">
<h2>Python Simulation Report</h2>
<p class="muted">File: <code>AERIS_Simulation_Report.pdf</code></p>
<p>
<a class="button" href="AERIS_Simulation_Report.pdf" target="_blank" rel="noopener">Open PDF</a>
<a class="button ghost" href="AERIS_Simulation_Report.pdf" download>Download</a>
</p>
</article>
</section>
<section class="card" style="margin-top:0.8rem;">
<h2>Antenna concept snapshot</h2>
<img class="diagram" src="assets/img/Antenna_Array.jpg" alt="Antenna array concept">
</section>
</main>
<footer class="footer">
<div class="container"><p>Add future report artifacts here to keep public references stable.</p></div>
</footer>
</body>
</html>