diff --git a/docs/architecture.html b/docs/architecture.html new file mode 100644 index 0000000..7edc2ef --- /dev/null +++ b/docs/architecture.html @@ -0,0 +1,94 @@ + + + + + + AERIS-10 Docs | Architecture + + + +
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+ AERIS-10 Docs + +
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System View

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Architecture and Data Path

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Hardware and firmware structure for the current XC7A200T implementation and bring-up targets.

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Top-level processing flow

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StageModule FocusNotes
ADC captureAD9484 interface + CDC edge400 MHz sampling domain, synchronized into processing pipeline.
DDCNCO + CIC + FIRI/Q conversion and decimation for baseband-ready stream.
Matched filterFFT-based chainSynthesis branch is golden for hardware-equivalent co-sim.
Range/DopplerRange bin decimator + Doppler FFT32 chirps/frame, 64 range bins, deterministic frame outputs.
Host pathFT601 interfaceUSB streaming with framing and soak validation in bring-up.
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Current target split strategy

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  • Production target remains xc7a200t-2fbg484i with full board constraints.
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  • TE0712/TE0701 and TE0713/TE0701 use dedicated top wrappers and dedicated XDC files.
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  • Board-specific pinouts are isolated from core DSP modules to avoid accidental cross-target regression.
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  • Bring-up sequence starts from minimal heartbeat top, then steps into full signal chain validation.
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Reference block diagram

+ AERIS-10 system architecture diagram +

Diagram snapshot from AERIS-10 project architecture.

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+ + + + diff --git a/docs/assets/img/Antenna_Array.jpg b/docs/assets/img/Antenna_Array.jpg new file mode 100644 index 0000000..50327b1 Binary files /dev/null and b/docs/assets/img/Antenna_Array.jpg differ diff --git a/docs/assets/img/RADAR_V6.jpg b/docs/assets/img/RADAR_V6.jpg new file mode 100644 index 0000000..e3be847 Binary files /dev/null and b/docs/assets/img/RADAR_V6.jpg differ diff --git a/docs/assets/style.css b/docs/assets/style.css new file mode 100644 index 0000000..a32dc4f --- /dev/null +++ b/docs/assets/style.css @@ -0,0 +1,205 @@ +:root { + --bg: #0b1220; + --bg-soft: #10192b; + --card: #162235; + --text: #e6edf6; + --muted: #9fb0c7; + --accent: #06b6d4; + --accent-2: #22c55e; + --border: #2a3a52; +} + +* { box-sizing: border-box; } + +body { + margin: 0; + color: var(--text); + background: radial-gradient(1200px 700px at 10% -10%, #1a2740 0, var(--bg) 52%); + font-family: "Segoe UI", Tahoma, Geneva, Verdana, sans-serif; + line-height: 1.5; +} + +a { color: #7dd3fc; } +a:hover { color: #bae6fd; } + +.container { + width: min(1120px, calc(100% - 2rem)); + margin: 0 auto; +} + +.topbar { + position: sticky; + top: 0; + z-index: 20; + background: rgba(8, 15, 28, 0.9); + border-bottom: 1px solid var(--border); + backdrop-filter: blur(6px); +} + +.nav { + display: flex; + align-items: center; + justify-content: space-between; + min-height: 62px; + gap: 1rem; +} + +.brand { + color: var(--text); + text-decoration: none; + font-weight: 700; + letter-spacing: 0.2px; +} + +.nav nav { + display: flex; + flex-wrap: wrap; + gap: 0.8rem; +} + +.nav nav a { + color: var(--muted); + text-decoration: none; + padding: 0.35rem 0.55rem; + border-radius: 8px; +} + +.nav nav a:hover { + color: var(--text); + background: #1b2a43; +} + +.page { + padding: 2.2rem 0 3.4rem; +} + +.hero { + background: linear-gradient(140deg, #0f1a2e, #111e35 55%, #0f172a); + border: 1px solid var(--border); + border-radius: 14px; + padding: 1.4rem; +} + +.eyebrow { + margin: 0; + color: #67e8f9; + text-transform: uppercase; + letter-spacing: 0.12em; + font-size: 0.76rem; +} + +h1 { margin: 0.4rem 0 0.6rem; line-height: 1.2; } +h2 { margin: 0 0 0.5rem; line-height: 1.25; } +h3 { margin: 0.2rem 0 0.5rem; } + +.cta-row { + display: flex; + flex-wrap: wrap; + gap: 0.7rem; + margin-top: 1rem; +} + +.button { + display: inline-block; + text-decoration: none; + color: #00141a; + background: linear-gradient(135deg, var(--accent), #38bdf8); + border-radius: 9px; + padding: 0.55rem 0.9rem; + font-weight: 700; +} + +.button.ghost { + color: var(--text); + background: #0e1728; + border: 1px solid var(--border); +} + +.stats-grid { + margin-top: 1rem; + display: grid; + gap: 0.8rem; + grid-template-columns: repeat(auto-fit, minmax(220px, 1fr)); +} + +.grid-2 { + margin-top: 1rem; + display: grid; + gap: 0.8rem; + grid-template-columns: repeat(auto-fit, minmax(280px, 1fr)); +} + +.card { + background: var(--card); + border: 1px solid var(--border); + border-radius: 12px; + padding: 1rem; +} + +.stat .metric { + margin: 0.1rem 0 0.25rem; + font-size: 1.3rem; + font-weight: 700; +} + +.muted { color: var(--muted); } + +ul { margin: 0.4rem 0 0; padding-left: 1.1rem; } +li { margin-bottom: 0.35rem; } + +.table-wrap { overflow-x: auto; } + +table { + width: 100%; + border-collapse: collapse; + margin-top: 0.5rem; + font-size: 0.94rem; +} + +th, td { + border: 1px solid var(--border); + padding: 0.55rem; + text-align: left; + vertical-align: top; +} + +th { background: #1b2b46; } + +.chip { + display: inline-block; + padding: 0.2rem 0.55rem; + border-radius: 999px; + font-size: 0.76rem; + border: 1px solid var(--border); + color: var(--muted); +} + +.timeline { + display: grid; + gap: 0.55rem; +} + +.timeline article { + background: #122037; + border: 1px solid var(--border); + border-radius: 10px; + padding: 0.75rem; +} + +.diagram { + width: 100%; + border: 1px solid var(--border); + border-radius: 12px; + background: #0d1527; +} + +.footer { + border-top: 1px solid var(--border); + color: var(--muted); + padding: 1rem 0 2rem; +} + +@media (max-width: 700px) { + .nav { align-items: flex-start; padding: 0.5rem 0; } + .nav nav { gap: 0.35rem; } +} diff --git a/docs/bring-up.html b/docs/bring-up.html new file mode 100644 index 0000000..9b72742 --- /dev/null +++ b/docs/bring-up.html @@ -0,0 +1,80 @@ + + + + + + AERIS-10 Docs | Bring-Up + + + +
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+ AERIS-10 Docs + +
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+

Execution Checklist

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Hardware Bring-Up Plan

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Operational sequence and pass/fail gates for Day-1 and post-Day-1 validation.

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Bring-up gates

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StepObjectivePass Criteria
1Program baseline bitstreamJTAG detect + successful configuration
2Clock/reset sanityStable clocks and deterministic reset release
3ADC front-endValid raw data visible in ILA on expected clock
4DDC verificationExpected valid strobe and non-zero I/Q outputs
5Matched filter stageRange profile valid asserted and segment flow correct
6Range/Doppler pipelineDeterministic frame outputs with full bin coverage
7USB host linkSustained transfer and stable framing over soak window
8Thermal/power screenNo rail anomalies or thermal runaway under load
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Day-1 quick sequence

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  1. Mount SoM on carrier and verify supply/jumper defaults.
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  2. Program minimal heartbeat top for immediate hardware liveness check.
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  3. Program debug bitstream and attach LTX for ILA sessions.
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  4. Capture first ADC and DDC traces, compare with expected signatures.
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Risk controls

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  • Keep production target untouched; use split dev targets for carrier-specific pinouts.
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  • Do not rely on RTL hierarchical net names in post-synth debug scripts.
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  • Run timing/CDC/exceptions checks after every target migration update.
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  • Use a repeatable program-capture checklist to detect intermittent reset/clock issues.
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+ + + + diff --git a/docs/implementation-log.html b/docs/implementation-log.html new file mode 100644 index 0000000..d60b1e5 --- /dev/null +++ b/docs/implementation-log.html @@ -0,0 +1,81 @@ + + + + + + AERIS-10 Docs | Implementation Log + + + +
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+ AERIS-10 Docs + +
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Engineering Journal

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Implementation Timeline and Improvements

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Consolidated record of key firmware, timing, debug and infrastructure changes.

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Recent milestone timeline

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Build 13 frozen as hardware candidate

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WNS +0.311 ns, TNS 0.000, WHS +0.060, THS 0.000 on production target.

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CDC analysis completed with waivers

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5 critical warnings verified as false positives and documented as waivers.

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ILA insertion flow hardened

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Added net discovery pass, deferred core creation, and Vivado 2025.2 MU_CNT handling.

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Bring-up scripts and bitstreams generated

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Baseline + debug bitstreams, programming script, and ILA capture script prepared.

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Target split for Trenz development path

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Added TE0712 and TE0713 separate top wrappers/XDC/build scripts to isolate pinout differences.

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Codebase quality and verification upgrades

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  • Expanded simulation and co-simulation coverage with golden comparison workflows.
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  • Formal verification executed across critical modules with passing results.
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  • Improved reset strategy in key blocks to reduce async-reset related methodology warnings.
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  • Renamed latency buffer module for maintainability and consistent references.
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Debug and infrastructure improvements

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  • Post-synthesis net-name mapping documented to avoid brittle ILA net paths.
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  • Generated both no-ILA and ILA debug bitstreams for staged bring-up.
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  • Added dedicated scripts for TE0712/TE0713 split builds.
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  • Created community issue to crowdsource compatible hardware test execution.
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+ + + + diff --git a/docs/index.html b/docs/index.html index 2e71375..78ec600 100644 --- a/docs/index.html +++ b/docs/index.html @@ -3,119 +3,83 @@ - AERIS-10 Simulation Reports - + AERIS-10 Engineering Docs + -
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+ AERIS-10 Docs + +
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AERIS-10 Public Simulation Reports

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GitHub Pages landing for antenna and Python simulation report artifacts.

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Open-Source Phased Array Radar

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Engineering Documentation Site

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This site tracks architecture, FPGA improvements, timing closure outcomes, and hardware bring-up readiness for AERIS-10.

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+ View Change Timeline + Open Bring-Up Checklist +
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Antenna Simulation Report

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Document: AERIS_Antenna_Report.pdf

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- Open PDF - Download -
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Build 13 Timing

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WNS +0.311 ns

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TNS 0.000, WHS +0.060, THS 0.000

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Python Simulation Report

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Document: AERIS_Simulation_Report.pdf

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- Open PDF - Download -
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Regression Status

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13 / 13 Suites

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Integration golden match: 2048 / 2048

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Debug Instrumentation

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4 ILA Cores

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92 probe bits, 4096 depth

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Current Phase

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Hardware Bring-Up

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TE0712/TE0713 split targets prepared

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Tip: In GitHub, enable Pages on the main branch with source folder /docs.

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What changed recently

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  • Closed timing on XC7A200T target and froze Build 13 candidate.
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  • Added CDC waivers for 5 verified false positives.
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  • Created resilient ILA insertion flow with post-synthesis net discovery.
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  • Generated baseline and debug bitstreams for bring-up.
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  • Added TE0712/TE0701 and TE0713/TE0701 split build targets.
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+ + diff --git a/docs/reports.html b/docs/reports.html new file mode 100644 index 0000000..001a680 --- /dev/null +++ b/docs/reports.html @@ -0,0 +1,58 @@ + + + + + + AERIS-10 Docs | Reports + + + +
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+ AERIS-10 Docs + +
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Artifacts

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Published Reports and Visuals

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Central access point for antenna simulations, Python simulation outputs, and visuals.

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+

Antenna Simulation Report

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File: AERIS_Antenna_Report.pdf

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+ Open PDF + Download +

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Python Simulation Report

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File: AERIS_Simulation_Report.pdf

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+ Open PDF + Download +

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Antenna concept snapshot

+ Antenna array concept +
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