fix(xdc): add hold false_path for ADC IDDR + reorganize build scripts by target
- Add set_false_path -hold for source-synchronous ADC IDDR paths in adc_clk_mmcm.xdc (eliminates 8 hold violations from build 12) - Add DDR falling-edge input delay constraints to xc7a50t_ftg256.xdc (parity with 200T XDC) - Reorganize scripts/ into target subdirectories: 50t/, 200t/, te0712/, te0713/, utils/ so users can run the correct build for their hardware - Delete obsolete build scripts (build17-20) superseded by build_50t/200t - Update project_root paths in all moved scripts (.. -> ../..)
This commit is contained in:
Jason
@@ -62,12 +62,24 @@ set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_mmcm_out0]
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set_false_path -through [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED]
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# --------------------------------------------------------------------------
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# Hold waiver for BUFIO→MMCM domain transfer (if Vivado flags hold violations)
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# Hold waiver for source-synchronous ADC capture (BUFIO-clocked IDDR)
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# --------------------------------------------------------------------------
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# The existing hold waiver for BUFIO source-synchronous capture stays:
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# set_false_path -hold -from [get_ports {adc_d_p[*]}] -to [get_clocks adc_dco_p]
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# The AD9484 ADC provides a source-synchronous interface: data (adc_d_p/n)
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# and clock (adc_dco_p/n) are output from the same chip with matched timing.
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# On the PCB, data and DCO traces are length-matched.
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#
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# The MMCM BUFG re-registration of IDDR outputs: since BUFIO and MMCM output
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# are derived from the same IBUFDS source, hold is inherently met (MMCM adds
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# insertion delay). If Vivado flags hold violations on this transfer, uncomment:
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# set_false_path -hold -from [get_clocks adc_dco_p] -to [get_clocks clk_mmcm_out0]
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# Inside the FPGA, the DCO clock path goes through IBUFDS → BUFIO, adding
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# ~2.2ns of insertion delay (IBUFDS 0.9ns + routing 0.6ns + BUFIO 1.3ns).
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# The data path goes through IBUFDS only (~0.85ns), arriving at the IDDR
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# ~1.4ns before the clock. Vivado's hold analysis sees the data "changing"
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# before the clock edge and reports WHS = -1.955ns.
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#
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# This is correct internal behavior: the BUFIO clock intentionally arrives
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# after the data. The IDDR captures on the BUFIO edge, by which time the
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# data is stable. Hold timing is guaranteed by the external PCB layout
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# (ADC data valid window centered on DCO edge), not by FPGA clock tree
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# delays. Vivado's STA model cannot account for this external relationship.
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#
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# Waiving hold on these 8 paths (adc_d_p[0..7] → IDDR) is standard practice
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# for source-synchronous LVDS ADC interfaces using BUFIO capture.
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set_false_path -hold -from [get_ports {adc_d_p[*]}] -to [get_clocks adc_dco_p]
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@@ -255,8 +255,11 @@ set_property IOSTANDARD LVDS_25 [get_ports {adc_d_n[*]}]
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set_property DIFF_TERM TRUE [get_ports {adc_d_p[*]}]
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# Input delay for ADC data relative to DCO (adjust based on PCB trace length)
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# DDR interface: constrain both rising and falling clock edges
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set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 [get_ports {adc_d_p[*]}]
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set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_d_p[*]}]
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set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
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set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
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# ============================================================================
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# FT601 USB 3.0 INTERFACE — ACTIVE: NO PHYSICAL CONNECTIONS
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+6
-34
@@ -1,42 +1,14 @@
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################################################################################
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# build21_fft_e2e.tcl
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# build_200t.tcl — XC7A200T Dev Board Build
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# AERIS-10 Build for the 200T development board (FBG484)
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#
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# AERIS-10 Build 21: FFT Optimizations + E2E RTL Fixes
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# Target: XC7A200T-2FBG484I
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# Design: radar_system_top
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# Base: Build 20 (v0.1.3-build20, WNS +0.426 ns)
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#
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# Changes vs Build 20:
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# - fft_engine.v: merged SHIFT state into WRITE (5→4 cycle butterfly,
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# 20% throughput gain). Twiddle index uses barrel-shift instead of
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# multiplier (frees 1 DSP48).
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# - plfm_chirp_controller.v: TX/RX mixer enables now mutually exclusive
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# by FSM state (Fix #4).
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# - usb_data_interface.v: stream control reset default 3'b001 (range-only),
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# doppler/cfar data_pending sticky flags, write FSM triggers on
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# range_valid only (Fix #5).
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# - radar_receiver_final.v: STM32 toggle signal inputs for mode-00,
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# dynamic frame detection via host_chirps_per_elev.
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# - radar_system_top.v: STM32 toggle wiring to receiver instance.
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# - chirp_memory_loader_param.v: explicit readmemh range for short chirp.
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#
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# Expected impact:
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# - DSP48E1: 140 → 139 (−1 from barrel-shift twiddle, +0 net from
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# FFT multiplier removal; CIC CREG DSPs unchanged)
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# - LUT/FF: slight increase from USB data_pending logic + receiver
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# toggle inputs. Slight decrease from FFT state removal.
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# - Timing: should remain positive (Build 20 had +0.426 ns WNS).
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# Gap 2 build (pre-FFT-opt) had +0.078 ns WNS with similar RTL.
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#
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# Generates ALL reports required for the 15-point Vivado TCL Build Report.
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#
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# Usage:
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# vivado -mode batch -source build21_fft_e2e.tcl \
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# -log build/build21.log \
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# -journal build/build21.jou
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#
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# Author: auto-generated for Jason Stone
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# Date: 2026-03-20
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# cd 9_Firmware/9_2_FPGA
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# vivado -mode batch -source scripts/200t/build_200t.tcl \
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# -log build/build.log -journal build/build.jou
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################################################################################
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# ==============================================================================
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@@ -45,7 +17,7 @@
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set project_name "aeris10_radar"
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set script_dir [file dirname [file normalize [info script]]]
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set project_root [file normalize [file join $script_dir ".."]]
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set project_root [file normalize [file join $script_dir "../.."]]
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set project_dir [file join $project_root "build"]
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set rtl_dir $project_root
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set top_module "radar_system_top"
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+6
-2
@@ -1,11 +1,15 @@
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################################################################################
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# build_50t_test.tcl — XC7A50T Production Build
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# build_50t.tcl — XC7A50T Production Build
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# Builds the AERIS-10 design targeting the production 50T (FTG256) board
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#
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# Usage:
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# cd 9_Firmware/9_2_FPGA
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# vivado -mode batch -source scripts/50t/build_50t.tcl 2>&1 | tee build_50t/vivado.log
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################################################################################
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set project_name "aeris10_radar_50t"
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set script_dir [file dirname [file normalize [info script]]]
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set project_root [file normalize [file join $script_dir ".."]]
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set project_root [file normalize [file join $script_dir "../.."]]
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set project_dir [file join $project_root "build_50t"]
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set rtl_dir $project_root
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set fpga_part "xc7a50tftg256-2"
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@@ -1,460 +0,0 @@
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################################################################################
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# build17_production.tcl
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#
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# AERIS-10 Build 17: Full Production Build + Comprehensive Report Suite
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# Target: XC7A200T-2FBG484I
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# Design: radar_system_top
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# Tag: v0.1.0-bringup (commit 8ca6d99)
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#
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# Generates ALL reports required for the 15-point Vivado TCL Build Report
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# Analysis Checklist:
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# 1. Run Status (synth/opt/place/route completion)
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# 2. Timing Summary (WNS/TNS/WHS)
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# 3. Clock Analysis (report_clocks)
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# 4. Utilization Report (LUT/FF/BRAM/DSP)
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# 5. Power Report (dynamic/static/thermal)
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# 6. DRC (Design Rule Check)
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# 7. IO and Constraints (report_io, unconstrained ports)
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# 8. Congestion Analysis (report_design_analysis -congestion)
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# 9. Route Status (unrouted nets)
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# 10. Critical Paths (report_timing -max_paths 20)
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# 11. QoR Summary (report_qor_summary)
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# 12. Incremental Compile comparison (timing vs Build 16)
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# 13. Log File Scan (captured in build log)
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# 14. Bitstream Generation (write_bitstream)
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# 15. Final Signoff Criteria (all above combined)
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#
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# Usage:
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# vivado -mode batch -source build17_production.tcl \
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# -log build/build17.log \
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# -journal build/build17.jou
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#
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# Author: auto-generated for Jason Stone
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# Date: 2026-03-19
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################################################################################
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# ==============================================================================
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# 0. Configuration
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# ==============================================================================
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set project_name "aeris10_radar"
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set script_dir [file dirname [file normalize [info script]]]
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set project_root [file normalize [file join $script_dir ".."]]
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set project_dir [file join $project_root "build"]
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set rtl_dir $project_root
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set top_module "radar_system_top"
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set fpga_part "xc7a200tfbg484-2"
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set report_dir "${project_dir}/reports_build17"
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set sim_dir "${project_dir}/sim"
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set bitstream_dir "${project_dir}/bitstream"
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set build_tag "build17"
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file mkdir $report_dir
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file mkdir $sim_dir
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file mkdir $bitstream_dir
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# Record start time
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set build_start [clock seconds]
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set build_timestamp [clock format $build_start -format {%Y-%m-%d %H:%M:%S}]
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puts "================================================================"
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puts " AERIS-10 Build 17: Full Production Build"
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puts " Target: $fpga_part"
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puts " Top: $top_module"
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puts " Reports: $report_dir"
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puts " Started: $build_timestamp"
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puts "================================================================"
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# ==============================================================================
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# 1. Project Creation + Source Files
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# ==============================================================================
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create_project $project_name $project_dir -part $fpga_part -force
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set_property target_language Verilog [current_project]
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# --- Add RTL sources ---
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set rtl_files [list \
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"${rtl_dir}/ad9484_interface_400m.v" \
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"${rtl_dir}/cdc_modules.v" \
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"${rtl_dir}/chirp_memory_loader_param.v" \
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"${rtl_dir}/cic_decimator_4x_enhanced.v" \
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"${rtl_dir}/dac_interface_single.v" \
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"${rtl_dir}/ddc_400m.v" \
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"${rtl_dir}/ddc_input_interface.v" \
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"${rtl_dir}/doppler_processor.v" \
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"${rtl_dir}/edge_detector.v" \
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"${rtl_dir}/fir_lowpass.v" \
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"${rtl_dir}/frequency_matched_filter.v" \
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"${rtl_dir}/latency_buffer.v" \
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"${rtl_dir}/matched_filter_multi_segment.v" \
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"${rtl_dir}/matched_filter_processing_chain.v" \
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"${rtl_dir}/nco_400m_enhanced.v" \
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"${rtl_dir}/plfm_chirp_controller.v" \
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"${rtl_dir}/radar_mode_controller.v" \
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"${rtl_dir}/radar_receiver_final.v" \
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"${rtl_dir}/radar_system_top.v" \
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"${rtl_dir}/radar_transmitter.v" \
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"${rtl_dir}/range_bin_decimator.v" \
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"${rtl_dir}/rx_gain_control.v" \
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"${rtl_dir}/mti_canceller.v" \
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"${rtl_dir}/cfar_ca.v" \
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"${rtl_dir}/fpga_self_test.v" \
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"${rtl_dir}/usb_data_interface.v" \
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"${rtl_dir}/xfft_16.v" \
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"${rtl_dir}/fft_engine.v" \
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"${rtl_dir}/adc_clk_mmcm.v" \
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]
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set file_count 0
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foreach f $rtl_files {
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if {[file exists $f]} {
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add_files -norecurse $f
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incr file_count
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} else {
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puts " WARNING: RTL file not found: $f"
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}
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}
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puts " Added $file_count RTL files"
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# Add .mem files for BRAM initialization
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set mem_files [glob -nocomplain "${rtl_dir}/*.mem"]
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foreach f $mem_files {
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add_files -norecurse $f
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puts " Added MEM: [file tail $f]"
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}
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|
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# Add constraints
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add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"]
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set_property top $top_module [current_fileset]
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set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
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# ==============================================================================
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# 2. Synthesis
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# ==============================================================================
|
||||
|
||||
puts ""
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||||
puts "================================================================"
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puts " Phase 1/5: Synthesis"
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puts "================================================================"
|
||||
|
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set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY rebuilt [get_runs synth_1]
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set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_1]
|
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set synth_start [clock seconds]
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launch_runs synth_1 -jobs 8
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wait_on_run synth_1
|
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set synth_elapsed [expr {[clock seconds] - $synth_start}]
|
||||
|
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set synth_status [get_property STATUS [get_runs synth_1]]
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puts " Synthesis status: $synth_status"
|
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puts " Synthesis time: ${synth_elapsed}s ([expr {$synth_elapsed/60}]m [expr {$synth_elapsed%60}]s)"
|
||||
|
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if {[string match "*ERROR*" $synth_status] || [string match "*FAILED*" $synth_status]} {
|
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puts "CRITICAL: SYNTHESIS FAILED — aborting build"
|
||||
close_project
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Post-synth timing (for comparison)
|
||||
open_run synth_1 -name synth_1
|
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report_timing_summary -delay_type min_max -max_paths 10 -file "${report_dir}/01_timing_post_synth.rpt"
|
||||
report_utilization -file "${report_dir}/01_utilization_post_synth.rpt"
|
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close_design
|
||||
|
||||
# ==============================================================================
|
||||
# 3. Implementation (opt → place → phys_opt → route → post_route_phys_opt)
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 2/5: Implementation"
|
||||
puts "================================================================"
|
||||
|
||||
# Aggressive directives for best timing
|
||||
set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
|
||||
set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE ExtraTimingOpt [get_runs impl_1]
|
||||
set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
||||
set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
|
||||
set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
||||
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
|
||||
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
||||
|
||||
set impl_start [clock seconds]
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
set impl_elapsed [expr {[clock seconds] - $impl_start}]
|
||||
|
||||
set impl_status [get_property STATUS [get_runs impl_1]]
|
||||
puts " Implementation status: $impl_status"
|
||||
puts " Implementation time: ${impl_elapsed}s ([expr {$impl_elapsed/60}]m [expr {$impl_elapsed%60}]s)"
|
||||
|
||||
if {![string match "*Complete*" $impl_status] && ![string match "*write_bitstream*" $impl_status]} {
|
||||
puts "CRITICAL: IMPLEMENTATION FAILED: $impl_status"
|
||||
close_project
|
||||
exit 1
|
||||
}
|
||||
|
||||
# ==============================================================================
|
||||
# 4. Bitstream Generation
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 3/5: Bitstream Generation"
|
||||
puts "================================================================"
|
||||
|
||||
set bit_start [clock seconds]
|
||||
# Handle case where Vivado auto-proceeds to write_bitstream after impl
|
||||
if {[catch {launch_runs impl_1 -to_step write_bitstream -jobs 8} launch_err]} {
|
||||
puts " Note: write_bitstream may already be in progress: $launch_err"
|
||||
}
|
||||
wait_on_run impl_1
|
||||
set bit_elapsed [expr {[clock seconds] - $bit_start}]
|
||||
puts " Bitstream time: ${bit_elapsed}s"
|
||||
|
||||
# Copy bitstream to known location
|
||||
set bit_src "${project_dir}/aeris10_radar.runs/impl_1/${top_module}.bit"
|
||||
if {[file exists $bit_src]} {
|
||||
file copy -force $bit_src "${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||||
puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||||
puts " Size: [file size $bit_src] bytes"
|
||||
} else {
|
||||
puts " WARNING: Bitstream file not found at $bit_src"
|
||||
}
|
||||
|
||||
# ==============================================================================
|
||||
# 5. Comprehensive Report Generation
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 4/5: Report Generation (15-point checklist)"
|
||||
puts "================================================================"
|
||||
|
||||
# Open the routed design for reporting
|
||||
open_run impl_1 -name impl_1
|
||||
|
||||
# --- Checklist Item 2: Timing Summary ---
|
||||
puts " [2/15] Timing Summary..."
|
||||
report_timing_summary -delay_type min_max -max_paths 100 \
|
||||
-report_unconstrained \
|
||||
-file "${report_dir}/02_timing_summary.rpt"
|
||||
|
||||
# --- Checklist Item 3: Clock Analysis ---
|
||||
puts " [3/15] Clock Analysis..."
|
||||
report_clocks -file "${report_dir}/03_clocks.rpt"
|
||||
report_clock_interaction -delay_type min_max \
|
||||
-file "${report_dir}/03_clock_interaction.rpt"
|
||||
report_clock_networks -file "${report_dir}/03_clock_networks.rpt"
|
||||
|
||||
# --- Checklist Item 4: Utilization ---
|
||||
puts " [4/15] Utilization..."
|
||||
report_utilization -file "${report_dir}/04_utilization.rpt"
|
||||
report_utilization -hierarchical -file "${report_dir}/04_utilization_hierarchical.rpt"
|
||||
|
||||
# --- Checklist Item 5: Power ---
|
||||
puts " [5/15] Power Report..."
|
||||
report_power -file "${report_dir}/05_power.rpt"
|
||||
|
||||
# --- Checklist Item 6: DRC ---
|
||||
puts " [6/15] DRC..."
|
||||
report_drc -file "${report_dir}/06_drc.rpt"
|
||||
|
||||
# --- Checklist Item 7: IO and Constraints ---
|
||||
puts " [7/15] IO Report..."
|
||||
report_io -file "${report_dir}/07_io.rpt"
|
||||
report_timing -from [all_inputs] -to [all_outputs] -max_paths 20 \
|
||||
-file "${report_dir}/07_io_timing.rpt"
|
||||
|
||||
# --- Checklist Item 8: Congestion Analysis ---
|
||||
puts " [8/15] Congestion Analysis..."
|
||||
report_design_analysis -congestion -file "${report_dir}/08_congestion.rpt"
|
||||
|
||||
# --- Checklist Item 9: Route Status ---
|
||||
puts " [9/15] Route Status..."
|
||||
report_route_status -file "${report_dir}/09_route_status.rpt"
|
||||
|
||||
# --- Checklist Item 10: Critical Paths ---
|
||||
puts " [10/15] Critical Paths..."
|
||||
report_timing -max_paths 20 -sort_by slack -nworst 5 \
|
||||
-file "${report_dir}/10_critical_paths_setup.rpt"
|
||||
report_timing -delay_type min -max_paths 20 -sort_by slack -nworst 5 \
|
||||
-file "${report_dir}/10_critical_paths_hold.rpt"
|
||||
report_high_fanout_nets -timing -load_type -max_nets 20 \
|
||||
-file "${report_dir}/10_high_fanout_nets.rpt"
|
||||
|
||||
# --- Checklist Item 11: QoR Summary ---
|
||||
puts " [11/15] QoR Summary..."
|
||||
report_design_analysis -timing -file "${report_dir}/11_design_analysis_timing.rpt"
|
||||
report_design_analysis -logic_level_distribution -file "${report_dir}/11_logic_level_dist.rpt"
|
||||
report_methodology -file "${report_dir}/11_methodology.rpt"
|
||||
|
||||
# --- Checklist Item 12: CDC Analysis ---
|
||||
puts " [12/15] CDC Analysis..."
|
||||
report_cdc -details -file "${report_dir}/12_cdc.rpt"
|
||||
|
||||
# --- Checklist Item 13: Log Scan (captured separately in build log) ---
|
||||
puts " [13/15] Log scan — see build17.log"
|
||||
|
||||
# --- Additional reports ---
|
||||
puts " \[extra\] Generating additional diagnostic reports..."
|
||||
|
||||
# Check_timing for completeness
|
||||
report_exceptions -file "${report_dir}/13_exceptions.rpt"
|
||||
check_timing -verbose -file "${report_dir}/13_check_timing.rpt"
|
||||
|
||||
# Compile configuration summary into a single text file
|
||||
set summary_fh [open "${report_dir}/00_build17_summary.txt" w]
|
||||
puts $summary_fh "================================================================"
|
||||
puts $summary_fh " AERIS-10 Build 17 — Production Build Summary"
|
||||
puts $summary_fh "================================================================"
|
||||
puts $summary_fh ""
|
||||
puts $summary_fh "Build Tag: $build_tag"
|
||||
puts $summary_fh "Build Timestamp: $build_timestamp"
|
||||
puts $summary_fh "FPGA Part: $fpga_part"
|
||||
puts $summary_fh "Top Module: $top_module"
|
||||
puts $summary_fh "RTL Files: $file_count"
|
||||
puts $summary_fh "Synth Status: $synth_status"
|
||||
puts $summary_fh "Synth Time: ${synth_elapsed}s"
|
||||
puts $summary_fh "Impl Status: $impl_status"
|
||||
puts $summary_fh "Impl Time: ${impl_elapsed}s"
|
||||
puts $summary_fh "Bitstream Time: ${bit_elapsed}s"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Extract key timing numbers — use catch to handle empty STATS properties
|
||||
# (Vivado 2025.2 may return empty strings after write_bitstream auto-launch)
|
||||
puts $summary_fh "--- Timing ---"
|
||||
if {[catch {set wns [get_property STATS.WNS [current_design]]}] || $wns eq ""} { set wns "N/A" }
|
||||
if {[catch {set tns [get_property STATS.TNS [current_design]]}] || $tns eq ""} { set tns "N/A" }
|
||||
if {[catch {set whs [get_property STATS.WHS [current_design]]}] || $whs eq ""} { set whs "N/A" }
|
||||
if {[catch {set ths [get_property STATS.THS [current_design]]}] || $ths eq ""} { set ths "N/A" }
|
||||
if {[catch {set fail_ep [get_property STATS.TPWS [current_design]]}] || $fail_ep eq ""} { set fail_ep "N/A" }
|
||||
puts $summary_fh " WNS: $wns ns"
|
||||
puts $summary_fh " TNS: $tns ns"
|
||||
puts $summary_fh " WHS: $whs ns"
|
||||
puts $summary_fh " THS: $ths ns"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Extract utilization
|
||||
puts $summary_fh "--- Utilization ---"
|
||||
set lut_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.LUT.*}]]
|
||||
set ff_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.FF.*}]]
|
||||
set bram_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ BMEM.*}]]
|
||||
set dsp_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ MULT.DSP.*}]]
|
||||
puts $summary_fh " LUTs: $lut_used / 134600"
|
||||
puts $summary_fh " FFs: $ff_used / 269200"
|
||||
puts $summary_fh " BRAM: $bram_used cells"
|
||||
puts $summary_fh " DSP: $dsp_used cells"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Route status
|
||||
set unrouted [llength [get_nets -hierarchical -filter {ROUTE_STATUS == UNROUTED}]]
|
||||
puts $summary_fh "--- Route ---"
|
||||
puts $summary_fh " Unrouted nets: $unrouted"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Bitstream
|
||||
if {[file exists $bit_src]} {
|
||||
puts $summary_fh "--- Bitstream ---"
|
||||
puts $summary_fh " File: ${top_module}_${build_tag}.bit"
|
||||
puts $summary_fh " Size: [file size $bit_src] bytes"
|
||||
} else {
|
||||
puts $summary_fh "--- Bitstream ---"
|
||||
puts $summary_fh " WARNING: NOT GENERATED"
|
||||
}
|
||||
puts $summary_fh ""
|
||||
|
||||
# Signoff
|
||||
puts $summary_fh "--- Final Signoff ---"
|
||||
set signoff_pass 1
|
||||
if {![string is double -strict $wns]} {
|
||||
puts $summary_fh " WARN: WNS = N/A (timing stats unavailable — check reports)"
|
||||
} elseif {$wns < 0} {
|
||||
puts $summary_fh " FAIL: WNS = $wns (negative slack)"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: WNS = $wns ns (no setup violations)"
|
||||
}
|
||||
if {![string is double -strict $whs]} {
|
||||
puts $summary_fh " WARN: WHS = N/A (timing stats unavailable — check reports)"
|
||||
} elseif {$whs < 0} {
|
||||
puts $summary_fh " FAIL: WHS = $whs (hold violation)"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: WHS = $whs ns (no hold violations)"
|
||||
}
|
||||
if {![string is double -strict $tns]} {
|
||||
puts $summary_fh " WARN: TNS = N/A (timing stats unavailable — check reports)"
|
||||
} elseif {$tns != 0} {
|
||||
puts $summary_fh " FAIL: TNS = $tns (total negative slack)"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: TNS = 0 ns"
|
||||
}
|
||||
if {$unrouted > 0} {
|
||||
puts $summary_fh " FAIL: $unrouted unrouted nets"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: All nets routed"
|
||||
}
|
||||
if {[file exists $bit_src]} {
|
||||
puts $summary_fh " PASS: Bitstream generated"
|
||||
} else {
|
||||
puts $summary_fh " FAIL: No bitstream"
|
||||
set signoff_pass 0
|
||||
}
|
||||
puts $summary_fh ""
|
||||
if {$signoff_pass} {
|
||||
puts $summary_fh " *** SIGNOFF: PASS ***"
|
||||
} else {
|
||||
puts $summary_fh " *** SIGNOFF: FAIL ***"
|
||||
}
|
||||
|
||||
close $summary_fh
|
||||
puts " Summary written to: ${report_dir}/00_build17_summary.txt"
|
||||
|
||||
# ==============================================================================
|
||||
# 6. SDF + Timing Netlist (for post-route simulation)
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 5/5: SDF + Timing Netlist"
|
||||
puts "================================================================"
|
||||
|
||||
write_verilog -force -mode timesim "${sim_dir}/post_impl_timesim.v"
|
||||
write_sdf -force "${sim_dir}/post_impl_timesim.sdf"
|
||||
|
||||
close_design
|
||||
open_run synth_1 -name synth_1
|
||||
write_verilog -force -mode funcsim "${sim_dir}/post_synth_funcsim.v"
|
||||
|
||||
# ==============================================================================
|
||||
# Done
|
||||
# ==============================================================================
|
||||
|
||||
set build_total [expr {[clock seconds] - $build_start}]
|
||||
set build_end [clock format [clock seconds] -format {%Y-%m-%d %H:%M:%S}]
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " BUILD 17 COMPLETE"
|
||||
puts "================================================================"
|
||||
puts " Started: $build_timestamp"
|
||||
puts " Finished: $build_end"
|
||||
puts " Total time: ${build_total}s ([expr {$build_total/60}]m [expr {$build_total%60}]s)"
|
||||
puts " Synth: ${synth_elapsed}s"
|
||||
puts " Impl: ${impl_elapsed}s"
|
||||
puts " Bitstream: ${bit_elapsed}s"
|
||||
puts " Reports: $report_dir"
|
||||
puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||||
puts " WNS: $wns ns | WHS: $whs ns | TNS: $tns ns"
|
||||
if {$signoff_pass} {
|
||||
puts " SIGNOFF: PASS"
|
||||
} else {
|
||||
puts " SIGNOFF: FAIL"
|
||||
}
|
||||
puts "================================================================"
|
||||
|
||||
close_project
|
||||
puts "Done."
|
||||
@@ -1,470 +0,0 @@
|
||||
################################################################################
|
||||
# build18_production.tcl
|
||||
#
|
||||
# AERIS-10 Build 18: Post-Optimization Production Build
|
||||
# Target: XC7A200T-2FBG484I
|
||||
# Design: radar_system_top
|
||||
# Tag: v0.1.1-build17 + FIR DSP48 pipelining + matched filter BRAM migration
|
||||
#
|
||||
# Changes vs Build 17:
|
||||
# - FIR DSP48 BREG+MREG pipelining (fixes 68 DPIP-1 + 35 DPOP-2 warnings)
|
||||
# - Matched filter input buffer migrated from register arrays to BRAM
|
||||
# (~33K FF savings expected, +2 BRAM18 used)
|
||||
# - Fixed: report_exceptions Vivado 2025.2 syntax (catch block)
|
||||
#
|
||||
# Generates ALL reports required for the 15-point Vivado TCL Build Report
|
||||
# Analysis Checklist:
|
||||
# 1. Run Status (synth/opt/place/route completion)
|
||||
# 2. Timing Summary (WNS/TNS/WHS)
|
||||
# 3. Clock Analysis (report_clocks)
|
||||
# 4. Utilization Report (LUT/FF/BRAM/DSP)
|
||||
# 5. Power Report (dynamic/static/thermal)
|
||||
# 6. DRC (Design Rule Check)
|
||||
# 7. IO and Constraints (report_io, unconstrained ports)
|
||||
# 8. Congestion Analysis (report_design_analysis -congestion)
|
||||
# 9. Route Status (unrouted nets)
|
||||
# 10. Critical Paths (report_timing -max_paths 20)
|
||||
# 11. QoR Summary (report_qor_summary)
|
||||
# 12. CDC Analysis
|
||||
# 13. Log File Scan (captured in build log)
|
||||
# 14. Bitstream Generation (write_bitstream)
|
||||
# 15. Final Signoff Criteria (all above combined)
|
||||
#
|
||||
# Usage:
|
||||
# vivado -mode batch -source build18_production.tcl \
|
||||
# -log build/build18.log \
|
||||
# -journal build/build18.jou
|
||||
#
|
||||
# Author: auto-generated for Jason Stone
|
||||
# Date: 2026-03-19
|
||||
################################################################################
|
||||
|
||||
# ==============================================================================
|
||||
# 0. Configuration
|
||||
# ==============================================================================
|
||||
|
||||
set project_name "aeris10_radar"
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
set project_root [file normalize [file join $script_dir ".."]]
|
||||
set project_dir [file join $project_root "build"]
|
||||
set rtl_dir $project_root
|
||||
set top_module "radar_system_top"
|
||||
set fpga_part "xc7a200tfbg484-2"
|
||||
set report_dir "${project_dir}/reports_build18"
|
||||
set sim_dir "${project_dir}/sim"
|
||||
set bitstream_dir "${project_dir}/bitstream"
|
||||
set build_tag "build18"
|
||||
|
||||
file mkdir $report_dir
|
||||
file mkdir $sim_dir
|
||||
file mkdir $bitstream_dir
|
||||
|
||||
# Record start time
|
||||
set build_start [clock seconds]
|
||||
set build_timestamp [clock format $build_start -format {%Y-%m-%d %H:%M:%S}]
|
||||
|
||||
puts "================================================================"
|
||||
puts " AERIS-10 Build 18: Post-Optimization Production Build"
|
||||
puts " Target: $fpga_part"
|
||||
puts " Top: $top_module"
|
||||
puts " Reports: $report_dir"
|
||||
puts " Started: $build_timestamp"
|
||||
puts "================================================================"
|
||||
|
||||
# ==============================================================================
|
||||
# 1. Project Creation + Source Files
|
||||
# ==============================================================================
|
||||
|
||||
create_project $project_name $project_dir -part $fpga_part -force
|
||||
set_property target_language Verilog [current_project]
|
||||
|
||||
# --- Add RTL sources ---
|
||||
set rtl_files [list \
|
||||
"${rtl_dir}/ad9484_interface_400m.v" \
|
||||
"${rtl_dir}/cdc_modules.v" \
|
||||
"${rtl_dir}/chirp_memory_loader_param.v" \
|
||||
"${rtl_dir}/cic_decimator_4x_enhanced.v" \
|
||||
"${rtl_dir}/dac_interface_single.v" \
|
||||
"${rtl_dir}/ddc_400m.v" \
|
||||
"${rtl_dir}/ddc_input_interface.v" \
|
||||
"${rtl_dir}/doppler_processor.v" \
|
||||
"${rtl_dir}/edge_detector.v" \
|
||||
"${rtl_dir}/fir_lowpass.v" \
|
||||
"${rtl_dir}/frequency_matched_filter.v" \
|
||||
"${rtl_dir}/latency_buffer.v" \
|
||||
"${rtl_dir}/matched_filter_multi_segment.v" \
|
||||
"${rtl_dir}/matched_filter_processing_chain.v" \
|
||||
"${rtl_dir}/nco_400m_enhanced.v" \
|
||||
"${rtl_dir}/plfm_chirp_controller.v" \
|
||||
"${rtl_dir}/radar_mode_controller.v" \
|
||||
"${rtl_dir}/radar_receiver_final.v" \
|
||||
"${rtl_dir}/radar_system_top.v" \
|
||||
"${rtl_dir}/radar_transmitter.v" \
|
||||
"${rtl_dir}/range_bin_decimator.v" \
|
||||
"${rtl_dir}/rx_gain_control.v" \
|
||||
"${rtl_dir}/mti_canceller.v" \
|
||||
"${rtl_dir}/cfar_ca.v" \
|
||||
"${rtl_dir}/fpga_self_test.v" \
|
||||
"${rtl_dir}/usb_data_interface.v" \
|
||||
"${rtl_dir}/xfft_16.v" \
|
||||
"${rtl_dir}/fft_engine.v" \
|
||||
"${rtl_dir}/adc_clk_mmcm.v" \
|
||||
]
|
||||
|
||||
set file_count 0
|
||||
foreach f $rtl_files {
|
||||
if {[file exists $f]} {
|
||||
add_files -norecurse $f
|
||||
incr file_count
|
||||
} else {
|
||||
puts " WARNING: RTL file not found: $f"
|
||||
}
|
||||
}
|
||||
puts " Added $file_count RTL files"
|
||||
|
||||
# Add .mem files for BRAM initialization
|
||||
set mem_files [glob -nocomplain "${rtl_dir}/*.mem"]
|
||||
foreach f $mem_files {
|
||||
add_files -norecurse $f
|
||||
puts " Added MEM: [file tail $f]"
|
||||
}
|
||||
|
||||
# Add constraints
|
||||
add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"]
|
||||
set_property top $top_module [current_fileset]
|
||||
set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
|
||||
|
||||
# ==============================================================================
|
||||
# 2. Synthesis
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 1/5: Synthesis"
|
||||
puts "================================================================"
|
||||
|
||||
set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY rebuilt [get_runs synth_1]
|
||||
set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_1]
|
||||
|
||||
set synth_start [clock seconds]
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
set synth_elapsed [expr {[clock seconds] - $synth_start}]
|
||||
|
||||
set synth_status [get_property STATUS [get_runs synth_1]]
|
||||
puts " Synthesis status: $synth_status"
|
||||
puts " Synthesis time: ${synth_elapsed}s ([expr {$synth_elapsed/60}]m [expr {$synth_elapsed%60}]s)"
|
||||
|
||||
if {[string match "*ERROR*" $synth_status] || [string match "*FAILED*" $synth_status]} {
|
||||
puts "CRITICAL: SYNTHESIS FAILED — aborting build"
|
||||
close_project
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Post-synth timing (for comparison)
|
||||
open_run synth_1 -name synth_1
|
||||
report_timing_summary -delay_type min_max -max_paths 10 -file "${report_dir}/01_timing_post_synth.rpt"
|
||||
report_utilization -file "${report_dir}/01_utilization_post_synth.rpt"
|
||||
close_design
|
||||
|
||||
# ==============================================================================
|
||||
# 3. Implementation (opt → place → phys_opt → route → post_route_phys_opt)
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 2/5: Implementation"
|
||||
puts "================================================================"
|
||||
|
||||
# Aggressive directives for best timing
|
||||
set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
|
||||
set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE ExtraTimingOpt [get_runs impl_1]
|
||||
set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
||||
set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
|
||||
set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
||||
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
|
||||
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
||||
|
||||
set impl_start [clock seconds]
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
set impl_elapsed [expr {[clock seconds] - $impl_start}]
|
||||
|
||||
set impl_status [get_property STATUS [get_runs impl_1]]
|
||||
puts " Implementation status: $impl_status"
|
||||
puts " Implementation time: ${impl_elapsed}s ([expr {$impl_elapsed/60}]m [expr {$impl_elapsed%60}]s)"
|
||||
|
||||
if {![string match "*Complete*" $impl_status] && ![string match "*write_bitstream*" $impl_status]} {
|
||||
puts "CRITICAL: IMPLEMENTATION FAILED: $impl_status"
|
||||
close_project
|
||||
exit 1
|
||||
}
|
||||
|
||||
# ==============================================================================
|
||||
# 4. Bitstream Generation
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 3/5: Bitstream Generation"
|
||||
puts "================================================================"
|
||||
|
||||
set bit_start [clock seconds]
|
||||
# Handle case where Vivado auto-proceeds to write_bitstream after impl
|
||||
if {[catch {launch_runs impl_1 -to_step write_bitstream -jobs 8} launch_err]} {
|
||||
puts " Note: write_bitstream may already be in progress: $launch_err"
|
||||
}
|
||||
wait_on_run impl_1
|
||||
set bit_elapsed [expr {[clock seconds] - $bit_start}]
|
||||
puts " Bitstream time: ${bit_elapsed}s"
|
||||
|
||||
# Copy bitstream to known location
|
||||
set bit_src "${project_dir}/aeris10_radar.runs/impl_1/${top_module}.bit"
|
||||
if {[file exists $bit_src]} {
|
||||
file copy -force $bit_src "${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||||
puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||||
puts " Size: [file size $bit_src] bytes"
|
||||
} else {
|
||||
puts " WARNING: Bitstream file not found at $bit_src"
|
||||
}
|
||||
|
||||
# ==============================================================================
|
||||
# 5. Comprehensive Report Generation
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 4/5: Report Generation (15-point checklist)"
|
||||
puts "================================================================"
|
||||
|
||||
# Open the routed design for reporting
|
||||
open_run impl_1 -name impl_1
|
||||
|
||||
# --- Checklist Item 2: Timing Summary ---
|
||||
puts " [2/15] Timing Summary..."
|
||||
report_timing_summary -delay_type min_max -max_paths 100 \
|
||||
-report_unconstrained \
|
||||
-file "${report_dir}/02_timing_summary.rpt"
|
||||
|
||||
# --- Checklist Item 3: Clock Analysis ---
|
||||
puts " [3/15] Clock Analysis..."
|
||||
report_clocks -file "${report_dir}/03_clocks.rpt"
|
||||
report_clock_interaction -delay_type min_max \
|
||||
-file "${report_dir}/03_clock_interaction.rpt"
|
||||
report_clock_networks -file "${report_dir}/03_clock_networks.rpt"
|
||||
|
||||
# --- Checklist Item 4: Utilization ---
|
||||
puts " [4/15] Utilization..."
|
||||
report_utilization -file "${report_dir}/04_utilization.rpt"
|
||||
report_utilization -hierarchical -file "${report_dir}/04_utilization_hierarchical.rpt"
|
||||
|
||||
# --- Checklist Item 5: Power ---
|
||||
puts " [5/15] Power Report..."
|
||||
report_power -file "${report_dir}/05_power.rpt"
|
||||
|
||||
# --- Checklist Item 6: DRC ---
|
||||
puts " [6/15] DRC..."
|
||||
report_drc -file "${report_dir}/06_drc.rpt"
|
||||
|
||||
# --- Checklist Item 7: IO and Constraints ---
|
||||
puts " [7/15] IO Report..."
|
||||
report_io -file "${report_dir}/07_io.rpt"
|
||||
report_timing -from [all_inputs] -to [all_outputs] -max_paths 20 \
|
||||
-file "${report_dir}/07_io_timing.rpt"
|
||||
|
||||
# --- Checklist Item 8: Congestion Analysis ---
|
||||
puts " [8/15] Congestion Analysis..."
|
||||
report_design_analysis -congestion -file "${report_dir}/08_congestion.rpt"
|
||||
|
||||
# --- Checklist Item 9: Route Status ---
|
||||
puts " [9/15] Route Status..."
|
||||
report_route_status -file "${report_dir}/09_route_status.rpt"
|
||||
|
||||
# --- Checklist Item 10: Critical Paths ---
|
||||
puts " [10/15] Critical Paths..."
|
||||
report_timing -max_paths 20 -sort_by slack -nworst 5 \
|
||||
-file "${report_dir}/10_critical_paths_setup.rpt"
|
||||
report_timing -delay_type min -max_paths 20 -sort_by slack -nworst 5 \
|
||||
-file "${report_dir}/10_critical_paths_hold.rpt"
|
||||
report_high_fanout_nets -timing -load_type -max_nets 20 \
|
||||
-file "${report_dir}/10_high_fanout_nets.rpt"
|
||||
|
||||
# --- Checklist Item 11: QoR Summary ---
|
||||
puts " [11/15] QoR Summary..."
|
||||
report_design_analysis -timing -file "${report_dir}/11_design_analysis_timing.rpt"
|
||||
report_design_analysis -logic_level_distribution -file "${report_dir}/11_logic_level_dist.rpt"
|
||||
report_methodology -file "${report_dir}/11_methodology.rpt"
|
||||
|
||||
# --- Checklist Item 12: CDC Analysis ---
|
||||
puts " [12/15] CDC Analysis..."
|
||||
report_cdc -details -file "${report_dir}/12_cdc.rpt"
|
||||
|
||||
# --- Checklist Item 13: Log Scan (captured separately in build log) ---
|
||||
puts " [13/15] Log scan — see build18.log"
|
||||
|
||||
# --- Additional reports ---
|
||||
puts " \[extra\] Generating additional diagnostic reports..."
|
||||
|
||||
# Check_timing for completeness
|
||||
# report_exceptions can fail in Vivado 2025.2 — wrap in catch
|
||||
if {[catch {report_exceptions -file "${report_dir}/13_exceptions.rpt"} err]} {
|
||||
puts " WARNING: report_exceptions failed: $err"
|
||||
puts " (Known Vivado 2025.2 issue — non-critical)"
|
||||
}
|
||||
check_timing -verbose -file "${report_dir}/13_check_timing.rpt"
|
||||
|
||||
# Compile configuration summary into a single text file
|
||||
set summary_fh [open "${report_dir}/00_build18_summary.txt" w]
|
||||
puts $summary_fh "================================================================"
|
||||
puts $summary_fh " AERIS-10 Build 18 — Post-Optimization Production Build Summary"
|
||||
puts $summary_fh "================================================================"
|
||||
puts $summary_fh ""
|
||||
puts $summary_fh "Build Tag: $build_tag"
|
||||
puts $summary_fh "Build Timestamp: $build_timestamp"
|
||||
puts $summary_fh "FPGA Part: $fpga_part"
|
||||
puts $summary_fh "Top Module: $top_module"
|
||||
puts $summary_fh "RTL Files: $file_count"
|
||||
puts $summary_fh "Synth Status: $synth_status"
|
||||
puts $summary_fh "Synth Time: ${synth_elapsed}s"
|
||||
puts $summary_fh "Impl Status: $impl_status"
|
||||
puts $summary_fh "Impl Time: ${impl_elapsed}s"
|
||||
puts $summary_fh "Bitstream Time: ${bit_elapsed}s"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Extract key timing numbers — use catch to handle empty STATS properties
|
||||
# (Vivado 2025.2 may return empty strings after write_bitstream auto-launch)
|
||||
puts $summary_fh "--- Timing ---"
|
||||
if {[catch {set wns [get_property STATS.WNS [current_design]]}] || $wns eq ""} { set wns "N/A" }
|
||||
if {[catch {set tns [get_property STATS.TNS [current_design]]}] || $tns eq ""} { set tns "N/A" }
|
||||
if {[catch {set whs [get_property STATS.WHS [current_design]]}] || $whs eq ""} { set whs "N/A" }
|
||||
if {[catch {set ths [get_property STATS.THS [current_design]]}] || $ths eq ""} { set ths "N/A" }
|
||||
if {[catch {set fail_ep [get_property STATS.TPWS [current_design]]}] || $fail_ep eq ""} { set fail_ep "N/A" }
|
||||
puts $summary_fh " WNS: $wns ns"
|
||||
puts $summary_fh " TNS: $tns ns"
|
||||
puts $summary_fh " WHS: $whs ns"
|
||||
puts $summary_fh " THS: $ths ns"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Extract utilization
|
||||
puts $summary_fh "--- Utilization ---"
|
||||
set lut_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.LUT.*}]]
|
||||
set ff_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.FF.*}]]
|
||||
set bram_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ BMEM.*}]]
|
||||
set dsp_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ MULT.DSP.*}]]
|
||||
puts $summary_fh " LUTs: $lut_used / 134600"
|
||||
puts $summary_fh " FFs: $ff_used / 269200"
|
||||
puts $summary_fh " BRAM: $bram_used cells"
|
||||
puts $summary_fh " DSP: $dsp_used cells"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Route status
|
||||
set unrouted [llength [get_nets -hierarchical -filter {ROUTE_STATUS == UNROUTED}]]
|
||||
puts $summary_fh "--- Route ---"
|
||||
puts $summary_fh " Unrouted nets: $unrouted"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Bitstream
|
||||
if {[file exists $bit_src]} {
|
||||
puts $summary_fh "--- Bitstream ---"
|
||||
puts $summary_fh " File: ${top_module}_${build_tag}.bit"
|
||||
puts $summary_fh " Size: [file size $bit_src] bytes"
|
||||
} else {
|
||||
puts $summary_fh "--- Bitstream ---"
|
||||
puts $summary_fh " WARNING: NOT GENERATED"
|
||||
}
|
||||
puts $summary_fh ""
|
||||
|
||||
# Signoff
|
||||
puts $summary_fh "--- Final Signoff ---"
|
||||
set signoff_pass 1
|
||||
if {![string is double -strict $wns]} {
|
||||
puts $summary_fh " WARN: WNS = N/A (timing stats unavailable — check reports)"
|
||||
} elseif {$wns < 0} {
|
||||
puts $summary_fh " FAIL: WNS = $wns (negative slack)"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: WNS = $wns ns (no setup violations)"
|
||||
}
|
||||
if {![string is double -strict $whs]} {
|
||||
puts $summary_fh " WARN: WHS = N/A (timing stats unavailable — check reports)"
|
||||
} elseif {$whs < 0} {
|
||||
puts $summary_fh " FAIL: WHS = $whs (hold violation)"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: WHS = $whs ns (no hold violations)"
|
||||
}
|
||||
if {![string is double -strict $tns]} {
|
||||
puts $summary_fh " WARN: TNS = N/A (timing stats unavailable — check reports)"
|
||||
} elseif {$tns != 0} {
|
||||
puts $summary_fh " FAIL: TNS = $tns (total negative slack)"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: TNS = 0 ns"
|
||||
}
|
||||
if {$unrouted > 0} {
|
||||
puts $summary_fh " FAIL: $unrouted unrouted nets"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: All nets routed"
|
||||
}
|
||||
if {[file exists $bit_src]} {
|
||||
puts $summary_fh " PASS: Bitstream generated"
|
||||
} else {
|
||||
puts $summary_fh " FAIL: No bitstream"
|
||||
set signoff_pass 0
|
||||
}
|
||||
puts $summary_fh ""
|
||||
if {$signoff_pass} {
|
||||
puts $summary_fh " *** SIGNOFF: PASS ***"
|
||||
} else {
|
||||
puts $summary_fh " *** SIGNOFF: FAIL ***"
|
||||
}
|
||||
|
||||
close $summary_fh
|
||||
puts " Summary written to: ${report_dir}/00_build18_summary.txt"
|
||||
|
||||
# ==============================================================================
|
||||
# 6. SDF + Timing Netlist (for post-route simulation)
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 5/5: SDF + Timing Netlist"
|
||||
puts "================================================================"
|
||||
|
||||
write_verilog -force -mode timesim "${sim_dir}/post_impl_timesim.v"
|
||||
write_sdf -force "${sim_dir}/post_impl_timesim.sdf"
|
||||
|
||||
close_design
|
||||
open_run synth_1 -name synth_1
|
||||
write_verilog -force -mode funcsim "${sim_dir}/post_synth_funcsim.v"
|
||||
|
||||
# ==============================================================================
|
||||
# Done
|
||||
# ==============================================================================
|
||||
|
||||
set build_total [expr {[clock seconds] - $build_start}]
|
||||
set build_end [clock format [clock seconds] -format {%Y-%m-%d %H:%M:%S}]
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " BUILD 18 COMPLETE"
|
||||
puts "================================================================"
|
||||
puts " Started: $build_timestamp"
|
||||
puts " Finished: $build_end"
|
||||
puts " Total time: ${build_total}s ([expr {$build_total/60}]m [expr {$build_total%60}]s)"
|
||||
puts " Synth: ${synth_elapsed}s"
|
||||
puts " Impl: ${impl_elapsed}s"
|
||||
puts " Bitstream: ${bit_elapsed}s"
|
||||
puts " Reports: $report_dir"
|
||||
puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||||
puts " WNS: $wns ns | WHS: $whs ns | TNS: $tns ns"
|
||||
if {$signoff_pass} {
|
||||
puts " SIGNOFF: PASS"
|
||||
} else {
|
||||
puts " SIGNOFF: FAIL"
|
||||
}
|
||||
puts "================================================================"
|
||||
|
||||
close_project
|
||||
puts "Done."
|
||||
@@ -1,493 +0,0 @@
|
||||
################################################################################
|
||||
# build19_mmcm.tcl
|
||||
#
|
||||
# AERIS-10 Build 19: MMCM Jitter-Cleaning on ADC 400 MHz Clock (Gap 7)
|
||||
# Target: XC7A200T-2FBG484I
|
||||
# Design: radar_system_top
|
||||
# Tag: v0.1.2-build18 + adc_clk_mmcm jitter cleaning wrapper
|
||||
#
|
||||
# Changes vs Build 18:
|
||||
# - NEW MODULE: adc_clk_mmcm.v — MMCME2_ADV jitter-cleaning wrapper
|
||||
# - MODIFIED: ad9484_interface_400m.v — BUFG replaced with MMCM path,
|
||||
# reset gated on mmcm_locked
|
||||
# - NEW XDC: adc_clk_mmcm.xdc — generated clock rename, CDC false paths
|
||||
#
|
||||
# Expected impact:
|
||||
# - WNS improvement: +20-40 ps (reduced clock uncertainty from jitter cleaning)
|
||||
# - MMCME2 usage: 0 → 1 (of 10 available)
|
||||
# - BUFG usage: 4 → 5 (of 32 available; feedback BUFG inside MMCM wrapper)
|
||||
#
|
||||
# Generates ALL reports required for the 15-point Vivado TCL Build Report.
|
||||
#
|
||||
# Usage:
|
||||
# vivado -mode batch -source build19_mmcm.tcl \
|
||||
# -log build/build19.log \
|
||||
# -journal build/build19.jou
|
||||
#
|
||||
# Author: auto-generated for Jason Stone
|
||||
# Date: 2026-03-19
|
||||
################################################################################
|
||||
|
||||
# ==============================================================================
|
||||
# 0. Configuration
|
||||
# ==============================================================================
|
||||
|
||||
set project_name "aeris10_radar"
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
set project_root [file normalize [file join $script_dir ".."]]
|
||||
set project_dir [file join $project_root "build"]
|
||||
set rtl_dir $project_root
|
||||
set top_module "radar_system_top"
|
||||
set fpga_part "xc7a200tfbg484-2"
|
||||
set report_dir "${project_dir}/reports_build19"
|
||||
set sim_dir "${project_dir}/sim"
|
||||
set bitstream_dir "${project_dir}/bitstream"
|
||||
set build_tag "build19"
|
||||
|
||||
file mkdir $report_dir
|
||||
file mkdir $sim_dir
|
||||
file mkdir $bitstream_dir
|
||||
|
||||
# Record start time
|
||||
set build_start [clock seconds]
|
||||
set build_timestamp [clock format $build_start -format {%Y-%m-%d %H:%M:%S}]
|
||||
|
||||
puts "================================================================"
|
||||
puts " AERIS-10 Build 19: MMCM Jitter-Cleaning (Gap 7)"
|
||||
puts " Target: $fpga_part"
|
||||
puts " Top: $top_module"
|
||||
puts " Reports: $report_dir"
|
||||
puts " Started: $build_timestamp"
|
||||
puts "================================================================"
|
||||
|
||||
# ==============================================================================
|
||||
# 1. Project Creation + Source Files
|
||||
# ==============================================================================
|
||||
|
||||
create_project $project_name $project_dir -part $fpga_part -force
|
||||
set_property target_language Verilog [current_project]
|
||||
|
||||
# --- Add RTL sources ---
|
||||
# NOTE: adc_clk_mmcm.v is NEW for Build 19 (Gap 7 MMCM wrapper)
|
||||
set rtl_files [list \
|
||||
"${rtl_dir}/adc_clk_mmcm.v" \
|
||||
"${rtl_dir}/ad9484_interface_400m.v" \
|
||||
"${rtl_dir}/cdc_modules.v" \
|
||||
"${rtl_dir}/chirp_memory_loader_param.v" \
|
||||
"${rtl_dir}/cic_decimator_4x_enhanced.v" \
|
||||
"${rtl_dir}/dac_interface_single.v" \
|
||||
"${rtl_dir}/ddc_400m.v" \
|
||||
"${rtl_dir}/ddc_input_interface.v" \
|
||||
"${rtl_dir}/doppler_processor.v" \
|
||||
"${rtl_dir}/edge_detector.v" \
|
||||
"${rtl_dir}/fir_lowpass.v" \
|
||||
"${rtl_dir}/frequency_matched_filter.v" \
|
||||
"${rtl_dir}/latency_buffer.v" \
|
||||
"${rtl_dir}/matched_filter_multi_segment.v" \
|
||||
"${rtl_dir}/matched_filter_processing_chain.v" \
|
||||
"${rtl_dir}/nco_400m_enhanced.v" \
|
||||
"${rtl_dir}/plfm_chirp_controller.v" \
|
||||
"${rtl_dir}/radar_mode_controller.v" \
|
||||
"${rtl_dir}/radar_receiver_final.v" \
|
||||
"${rtl_dir}/radar_system_top.v" \
|
||||
"${rtl_dir}/radar_transmitter.v" \
|
||||
"${rtl_dir}/range_bin_decimator.v" \
|
||||
"${rtl_dir}/rx_gain_control.v" \
|
||||
"${rtl_dir}/mti_canceller.v" \
|
||||
"${rtl_dir}/cfar_ca.v" \
|
||||
"${rtl_dir}/fpga_self_test.v" \
|
||||
"${rtl_dir}/usb_data_interface.v" \
|
||||
"${rtl_dir}/xfft_16.v" \
|
||||
"${rtl_dir}/fft_engine.v" \
|
||||
]
|
||||
|
||||
set file_count 0
|
||||
foreach f $rtl_files {
|
||||
if {[file exists $f]} {
|
||||
add_files -norecurse $f
|
||||
incr file_count
|
||||
} else {
|
||||
puts " WARNING: RTL file not found: $f"
|
||||
}
|
||||
}
|
||||
puts " Added $file_count RTL files"
|
||||
|
||||
# Add .mem files for BRAM initialization
|
||||
set mem_files [glob -nocomplain "${rtl_dir}/*.mem"]
|
||||
foreach f $mem_files {
|
||||
add_files -norecurse $f
|
||||
puts " Added MEM: [file tail $f]"
|
||||
}
|
||||
|
||||
# Add constraints — main production XDC + MMCM supplementary XDC
|
||||
add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"]
|
||||
add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "adc_clk_mmcm.xdc"]
|
||||
|
||||
set_property top $top_module [current_fileset]
|
||||
set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
|
||||
|
||||
# ==============================================================================
|
||||
# 2. Synthesis
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 1/5: Synthesis"
|
||||
puts "================================================================"
|
||||
|
||||
set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY rebuilt [get_runs synth_1]
|
||||
set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_1]
|
||||
|
||||
set synth_start [clock seconds]
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
set synth_elapsed [expr {[clock seconds] - $synth_start}]
|
||||
|
||||
set synth_status [get_property STATUS [get_runs synth_1]]
|
||||
puts " Synthesis status: $synth_status"
|
||||
puts " Synthesis time: ${synth_elapsed}s ([expr {$synth_elapsed/60}]m [expr {$synth_elapsed%60}]s)"
|
||||
|
||||
if {[string match "*ERROR*" $synth_status] || [string match "*FAILED*" $synth_status]} {
|
||||
puts "CRITICAL: SYNTHESIS FAILED — aborting build"
|
||||
close_project
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Post-synth timing (for comparison)
|
||||
open_run synth_1 -name synth_1
|
||||
report_timing_summary -delay_type min_max -max_paths 10 -file "${report_dir}/01_timing_post_synth.rpt"
|
||||
report_utilization -file "${report_dir}/01_utilization_post_synth.rpt"
|
||||
close_design
|
||||
|
||||
# ==============================================================================
|
||||
# 3. Implementation (opt → place → phys_opt → route → post_route_phys_opt)
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 2/5: Implementation"
|
||||
puts "================================================================"
|
||||
|
||||
# Aggressive directives for best timing
|
||||
set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
|
||||
set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE ExtraTimingOpt [get_runs impl_1]
|
||||
set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
||||
set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
|
||||
set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
||||
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
|
||||
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
||||
|
||||
set impl_start [clock seconds]
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
set impl_elapsed [expr {[clock seconds] - $impl_start}]
|
||||
|
||||
set impl_status [get_property STATUS [get_runs impl_1]]
|
||||
puts " Implementation status: $impl_status"
|
||||
puts " Implementation time: ${impl_elapsed}s ([expr {$impl_elapsed/60}]m [expr {$impl_elapsed%60}]s)"
|
||||
|
||||
if {![string match "*Complete*" $impl_status] && ![string match "*write_bitstream*" $impl_status]} {
|
||||
puts "CRITICAL: IMPLEMENTATION FAILED: $impl_status"
|
||||
close_project
|
||||
exit 1
|
||||
}
|
||||
|
||||
# ==============================================================================
|
||||
# 4. Bitstream Generation
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 3/5: Bitstream Generation"
|
||||
puts "================================================================"
|
||||
|
||||
set bit_start [clock seconds]
|
||||
# Handle case where Vivado auto-proceeds to write_bitstream after impl
|
||||
if {[catch {launch_runs impl_1 -to_step write_bitstream -jobs 8} launch_err]} {
|
||||
puts " Note: write_bitstream may already be in progress: $launch_err"
|
||||
}
|
||||
wait_on_run impl_1
|
||||
set bit_elapsed [expr {[clock seconds] - $bit_start}]
|
||||
puts " Bitstream time: ${bit_elapsed}s"
|
||||
|
||||
# Copy bitstream to known location
|
||||
set bit_src "${project_dir}/aeris10_radar.runs/impl_1/${top_module}.bit"
|
||||
if {[file exists $bit_src]} {
|
||||
file copy -force $bit_src "${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||||
puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||||
puts " Size: [file size $bit_src] bytes"
|
||||
} else {
|
||||
puts " WARNING: Bitstream file not found at $bit_src"
|
||||
}
|
||||
|
||||
# ==============================================================================
|
||||
# 5. Comprehensive Report Generation
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 4/5: Report Generation (15-point checklist)"
|
||||
puts "================================================================"
|
||||
|
||||
# Open the routed design for reporting
|
||||
open_run impl_1 -name impl_1
|
||||
|
||||
# --- Checklist Item 2: Timing Summary ---
|
||||
puts " [2/15] Timing Summary..."
|
||||
report_timing_summary -delay_type min_max -max_paths 100 \
|
||||
-report_unconstrained \
|
||||
-file "${report_dir}/02_timing_summary.rpt"
|
||||
|
||||
# --- Checklist Item 3: Clock Analysis ---
|
||||
puts " [3/15] Clock Analysis..."
|
||||
report_clocks -file "${report_dir}/03_clocks.rpt"
|
||||
report_clock_interaction -delay_type min_max \
|
||||
-file "${report_dir}/03_clock_interaction.rpt"
|
||||
report_clock_networks -file "${report_dir}/03_clock_networks.rpt"
|
||||
|
||||
# --- Checklist Item 4: Utilization ---
|
||||
puts " [4/15] Utilization..."
|
||||
report_utilization -file "${report_dir}/04_utilization.rpt"
|
||||
report_utilization -hierarchical -file "${report_dir}/04_utilization_hierarchical.rpt"
|
||||
|
||||
# --- Checklist Item 5: Power ---
|
||||
puts " [5/15] Power Report..."
|
||||
report_power -file "${report_dir}/05_power.rpt"
|
||||
|
||||
# --- Checklist Item 6: DRC ---
|
||||
puts " [6/15] DRC..."
|
||||
report_drc -file "${report_dir}/06_drc.rpt"
|
||||
|
||||
# --- Checklist Item 7: IO and Constraints ---
|
||||
puts " [7/15] IO Report..."
|
||||
report_io -file "${report_dir}/07_io.rpt"
|
||||
report_timing -from [all_inputs] -to [all_outputs] -max_paths 20 \
|
||||
-file "${report_dir}/07_io_timing.rpt"
|
||||
|
||||
# --- Checklist Item 8: Congestion Analysis ---
|
||||
puts " [8/15] Congestion Analysis..."
|
||||
report_design_analysis -congestion -file "${report_dir}/08_congestion.rpt"
|
||||
|
||||
# --- Checklist Item 9: Route Status ---
|
||||
puts " [9/15] Route Status..."
|
||||
report_route_status -file "${report_dir}/09_route_status.rpt"
|
||||
|
||||
# --- Checklist Item 10: Critical Paths ---
|
||||
puts " [10/15] Critical Paths..."
|
||||
report_timing -max_paths 20 -sort_by slack -nworst 5 \
|
||||
-file "${report_dir}/10_critical_paths_setup.rpt"
|
||||
report_timing -delay_type min -max_paths 20 -sort_by slack -nworst 5 \
|
||||
-file "${report_dir}/10_critical_paths_hold.rpt"
|
||||
report_high_fanout_nets -timing -load_type -max_nets 20 \
|
||||
-file "${report_dir}/10_high_fanout_nets.rpt"
|
||||
|
||||
# --- Checklist Item 11: QoR Summary ---
|
||||
puts " [11/15] QoR Summary..."
|
||||
report_design_analysis -timing -file "${report_dir}/11_design_analysis_timing.rpt"
|
||||
report_design_analysis -logic_level_distribution -file "${report_dir}/11_logic_level_dist.rpt"
|
||||
report_methodology -file "${report_dir}/11_methodology.rpt"
|
||||
|
||||
# --- Checklist Item 12: CDC Analysis ---
|
||||
puts " [12/15] CDC Analysis..."
|
||||
report_cdc -details -file "${report_dir}/12_cdc.rpt"
|
||||
|
||||
# --- Checklist Item 13: Log Scan (captured separately in build log) ---
|
||||
puts " [13/15] Log scan — see build19.log"
|
||||
|
||||
# --- Additional reports ---
|
||||
puts " \[extra\] Generating additional diagnostic reports..."
|
||||
|
||||
# report_exceptions can fail in Vivado 2025.2 — wrap in catch
|
||||
if {[catch {report_exceptions -file "${report_dir}/13_exceptions.rpt"} err]} {
|
||||
puts " WARNING: report_exceptions failed: $err"
|
||||
puts " (Known Vivado 2025.2 issue — non-critical)"
|
||||
}
|
||||
check_timing -verbose -file "${report_dir}/13_check_timing.rpt"
|
||||
|
||||
# Compile configuration summary into a single text file
|
||||
set summary_fh [open "${report_dir}/00_build19_summary.txt" w]
|
||||
puts $summary_fh "================================================================"
|
||||
puts $summary_fh " AERIS-10 Build 19 — MMCM Jitter-Cleaning (Gap 7) Summary"
|
||||
puts $summary_fh "================================================================"
|
||||
puts $summary_fh ""
|
||||
puts $summary_fh "Build Tag: $build_tag"
|
||||
puts $summary_fh "Build Timestamp: $build_timestamp"
|
||||
puts $summary_fh "FPGA Part: $fpga_part"
|
||||
puts $summary_fh "Top Module: $top_module"
|
||||
puts $summary_fh "RTL Files: $file_count"
|
||||
puts $summary_fh "Synth Status: $synth_status"
|
||||
puts $summary_fh "Synth Time: ${synth_elapsed}s"
|
||||
puts $summary_fh "Impl Status: $impl_status"
|
||||
puts $summary_fh "Impl Time: ${impl_elapsed}s"
|
||||
puts $summary_fh "Bitstream Time: ${bit_elapsed}s"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Extract key timing numbers — use catch to handle empty STATS properties
|
||||
# (Vivado 2025.2 may return empty strings after write_bitstream auto-launch)
|
||||
puts $summary_fh "--- Timing ---"
|
||||
if {[catch {set wns [get_property STATS.WNS [current_design]]}] || $wns eq ""} { set wns "N/A" }
|
||||
if {[catch {set tns [get_property STATS.TNS [current_design]]}] || $tns eq ""} { set tns "N/A" }
|
||||
if {[catch {set whs [get_property STATS.WHS [current_design]]}] || $whs eq ""} { set whs "N/A" }
|
||||
if {[catch {set ths [get_property STATS.THS [current_design]]}] || $ths eq ""} { set ths "N/A" }
|
||||
if {[catch {set fail_ep [get_property STATS.TPWS [current_design]]}] || $fail_ep eq ""} { set fail_ep "N/A" }
|
||||
puts $summary_fh " WNS: $wns ns"
|
||||
puts $summary_fh " TNS: $tns ns"
|
||||
puts $summary_fh " WHS: $whs ns"
|
||||
puts $summary_fh " THS: $ths ns"
|
||||
puts $summary_fh ""
|
||||
puts $summary_fh " Build 18 Baseline: WNS = +0.062 ns, WHS = +0.059 ns"
|
||||
if {[string is double -strict $wns]} {
|
||||
puts $summary_fh " Delta WNS: [expr {$wns - 0.062}] ns"
|
||||
} else {
|
||||
puts $summary_fh " Delta WNS: N/A (timing stats unavailable)"
|
||||
}
|
||||
if {[string is double -strict $whs]} {
|
||||
puts $summary_fh " Delta WHS: [expr {$whs - 0.059}] ns"
|
||||
} else {
|
||||
puts $summary_fh " Delta WHS: N/A (timing stats unavailable)"
|
||||
}
|
||||
puts $summary_fh ""
|
||||
|
||||
# Extract utilization
|
||||
puts $summary_fh "--- Utilization ---"
|
||||
set lut_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.LUT.*}]]
|
||||
set ff_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.FF.*}]]
|
||||
set bram_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ BMEM.*}]]
|
||||
set dsp_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ MULT.DSP.*}]]
|
||||
puts $summary_fh " LUTs: $lut_used / 134600"
|
||||
puts $summary_fh " FFs: $ff_used / 269200"
|
||||
puts $summary_fh " BRAM: $bram_used cells"
|
||||
puts $summary_fh " DSP: $dsp_used cells"
|
||||
puts $summary_fh ""
|
||||
puts $summary_fh " Build 18 Baseline: LUTs=6088, FFs=8946, BRAM=16, DSP=140"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Route status
|
||||
set unrouted [llength [get_nets -hierarchical -filter {ROUTE_STATUS == UNROUTED}]]
|
||||
puts $summary_fh "--- Route ---"
|
||||
puts $summary_fh " Unrouted nets: $unrouted"
|
||||
puts $summary_fh ""
|
||||
|
||||
# MMCM usage (new for Build 19)
|
||||
puts $summary_fh "--- MMCM Usage (Gap 7) ---"
|
||||
set mmcm_count [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLOCK.MMCM.*}]]
|
||||
puts $summary_fh " MMCME2 used: $mmcm_count / 10"
|
||||
puts $summary_fh " Expected: 1 (adc_clk_mmcm jitter cleaner)"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Bitstream
|
||||
if {[file exists $bit_src]} {
|
||||
puts $summary_fh "--- Bitstream ---"
|
||||
puts $summary_fh " File: ${top_module}_${build_tag}.bit"
|
||||
puts $summary_fh " Size: [file size $bit_src] bytes"
|
||||
} else {
|
||||
puts $summary_fh "--- Bitstream ---"
|
||||
puts $summary_fh " WARNING: NOT GENERATED"
|
||||
}
|
||||
puts $summary_fh ""
|
||||
|
||||
# Signoff
|
||||
puts $summary_fh "--- Final Signoff ---"
|
||||
set signoff_pass 1
|
||||
if {![string is double -strict $wns]} {
|
||||
puts $summary_fh " WARN: WNS = N/A (timing stats unavailable — check reports)"
|
||||
} elseif {$wns < 0} {
|
||||
puts $summary_fh " FAIL: WNS = $wns (negative slack)"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: WNS = $wns ns (no setup violations)"
|
||||
}
|
||||
if {![string is double -strict $whs]} {
|
||||
puts $summary_fh " WARN: WHS = N/A (timing stats unavailable — check reports)"
|
||||
} elseif {$whs < 0} {
|
||||
puts $summary_fh " FAIL: WHS = $whs (hold violation)"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: WHS = $whs ns (no hold violations)"
|
||||
}
|
||||
if {![string is double -strict $tns]} {
|
||||
puts $summary_fh " WARN: TNS = N/A (timing stats unavailable — check reports)"
|
||||
} elseif {$tns != 0} {
|
||||
puts $summary_fh " FAIL: TNS = $tns (total negative slack)"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: TNS = 0 ns"
|
||||
}
|
||||
if {$unrouted > 0} {
|
||||
puts $summary_fh " FAIL: $unrouted unrouted nets"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: All nets routed"
|
||||
}
|
||||
if {[file exists $bit_src]} {
|
||||
puts $summary_fh " PASS: Bitstream generated"
|
||||
} else {
|
||||
puts $summary_fh " FAIL: No bitstream"
|
||||
set signoff_pass 0
|
||||
}
|
||||
puts $summary_fh ""
|
||||
|
||||
# Timing regression check vs Build 18
|
||||
if {[string is double -strict $wns] && $wns < 0.062} {
|
||||
puts $summary_fh " *** WARNING: WNS REGRESSED vs Build 18 (was +0.062 ns, now $wns ns) ***"
|
||||
puts $summary_fh " *** Consider reverting MMCM changes per revert-safety policy ***"
|
||||
}
|
||||
if {[string is double -strict $whs] && $whs < 0.059} {
|
||||
puts $summary_fh " *** WARNING: WHS REGRESSED vs Build 18 (was +0.059 ns, now $whs ns) ***"
|
||||
}
|
||||
|
||||
if {$signoff_pass} {
|
||||
puts $summary_fh " *** SIGNOFF: PASS ***"
|
||||
} else {
|
||||
puts $summary_fh " *** SIGNOFF: FAIL ***"
|
||||
}
|
||||
|
||||
close $summary_fh
|
||||
puts " Summary written to: ${report_dir}/00_build19_summary.txt"
|
||||
|
||||
# ==============================================================================
|
||||
# 6. SDF + Timing Netlist (for post-route simulation)
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 5/5: SDF + Timing Netlist"
|
||||
puts "================================================================"
|
||||
|
||||
write_verilog -force -mode timesim "${sim_dir}/post_impl_timesim.v"
|
||||
write_sdf -force "${sim_dir}/post_impl_timesim.sdf"
|
||||
|
||||
close_design
|
||||
open_run synth_1 -name synth_1
|
||||
write_verilog -force -mode funcsim "${sim_dir}/post_synth_funcsim.v"
|
||||
|
||||
# ==============================================================================
|
||||
# Done
|
||||
# ==============================================================================
|
||||
|
||||
set build_total [expr {[clock seconds] - $build_start}]
|
||||
set build_end [clock format [clock seconds] -format {%Y-%m-%d %H:%M:%S}]
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " BUILD 19 COMPLETE"
|
||||
puts "================================================================"
|
||||
puts " Started: $build_timestamp"
|
||||
puts " Finished: $build_end"
|
||||
puts " Total time: ${build_total}s ([expr {$build_total/60}]m [expr {$build_total%60}]s)"
|
||||
puts " Synth: ${synth_elapsed}s"
|
||||
puts " Impl: ${impl_elapsed}s"
|
||||
puts " Bitstream: ${bit_elapsed}s"
|
||||
puts " Reports: $report_dir"
|
||||
puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||||
puts " WNS: $wns ns | WHS: $whs ns | TNS: $tns ns"
|
||||
puts " Build 18 baseline: WNS +0.062 | WHS +0.059"
|
||||
if {$signoff_pass} {
|
||||
puts " SIGNOFF: PASS"
|
||||
} else {
|
||||
puts " SIGNOFF: FAIL"
|
||||
}
|
||||
puts "================================================================"
|
||||
|
||||
close_project
|
||||
puts "Done."
|
||||
@@ -1,501 +0,0 @@
|
||||
################################################################################
|
||||
# build20_mmcm_creg.tcl
|
||||
#
|
||||
# AERIS-10 Build 20: MMCM XDC Clock-Name Fix + CIC Comb CREG Pipeline
|
||||
# Target: XC7A200T-2FBG484I
|
||||
# Design: radar_system_top
|
||||
# Tag: v0.1.2-build18 + MMCM (Gap 7) + XDC fix + CIC CREG
|
||||
#
|
||||
# Changes vs Build 19:
|
||||
# - FIX: adc_clk_mmcm.xdc — removed conflicting create_generated_clock
|
||||
# (clk_400m_mmcm), replaced all references with Vivado auto-generated
|
||||
# clk_mmcm_out0. This fixes the CDC false path that wasn't applying
|
||||
# to the actual clk_mmcm_out0→clk_100m crossing (Build 19 WNS -0.011).
|
||||
# - NEW: cic_decimator_4x_enhanced.v — explicit DSP48E1 for comb[0] with
|
||||
# CREG=1/AREG=1/BREG=1/PREG=1. Absorbs the integrator_sampled_comb
|
||||
# fabric register into DSP48 C-port pipeline, eliminating 0.643 ns
|
||||
# fabric→DSP route delay (Build 18 tightest path, WNS +0.062).
|
||||
#
|
||||
# Expected impact:
|
||||
# - WNS: should be >> +0.062 ns (CREG eliminates Build 18 critical path,
|
||||
# XDC fix properly applies CDC false path)
|
||||
# - DSP48E1: 140 → 142 (+2: one per CIC I/Q channel for comb_0_dsp)
|
||||
# - LUT/FF: ~same (CREG replaces fabric FDREs with DSP internal registers)
|
||||
#
|
||||
# Generates ALL reports required for the 15-point Vivado TCL Build Report.
|
||||
#
|
||||
# Usage:
|
||||
# vivado -mode batch -source build20_mmcm_creg.tcl \
|
||||
# -log build/build20.log \
|
||||
# -journal build/build20.jou
|
||||
#
|
||||
# Author: auto-generated for Jason Stone
|
||||
# Date: 2026-03-19
|
||||
################################################################################
|
||||
|
||||
# ==============================================================================
|
||||
# 0. Configuration
|
||||
# ==============================================================================
|
||||
|
||||
set project_name "aeris10_radar"
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
set project_root [file normalize [file join $script_dir ".."]]
|
||||
set project_dir [file join $project_root "build"]
|
||||
set rtl_dir $project_root
|
||||
set top_module "radar_system_top"
|
||||
set fpga_part "xc7a200tfbg484-2"
|
||||
set report_dir "${project_dir}/reports_build20"
|
||||
set sim_dir "${project_dir}/sim"
|
||||
set bitstream_dir "${project_dir}/bitstream"
|
||||
set build_tag "build20"
|
||||
|
||||
file mkdir $report_dir
|
||||
file mkdir $sim_dir
|
||||
file mkdir $bitstream_dir
|
||||
|
||||
# Record start time
|
||||
set build_start [clock seconds]
|
||||
set build_timestamp [clock format $build_start -format {%Y-%m-%d %H:%M:%S}]
|
||||
|
||||
puts "================================================================"
|
||||
puts " AERIS-10 Build 20: MMCM XDC Fix + CIC CREG Pipeline"
|
||||
puts " Target: $fpga_part"
|
||||
puts " Top: $top_module"
|
||||
puts " Reports: $report_dir"
|
||||
puts " Started: $build_timestamp"
|
||||
puts "================================================================"
|
||||
|
||||
# ==============================================================================
|
||||
# 1. Project Creation + Source Files
|
||||
# ==============================================================================
|
||||
|
||||
create_project $project_name $project_dir -part $fpga_part -force
|
||||
set_property target_language Verilog [current_project]
|
||||
|
||||
# --- Add RTL sources ---
|
||||
set rtl_files [list \
|
||||
"${rtl_dir}/adc_clk_mmcm.v" \
|
||||
"${rtl_dir}/ad9484_interface_400m.v" \
|
||||
"${rtl_dir}/cdc_modules.v" \
|
||||
"${rtl_dir}/chirp_memory_loader_param.v" \
|
||||
"${rtl_dir}/cic_decimator_4x_enhanced.v" \
|
||||
"${rtl_dir}/dac_interface_single.v" \
|
||||
"${rtl_dir}/ddc_400m.v" \
|
||||
"${rtl_dir}/ddc_input_interface.v" \
|
||||
"${rtl_dir}/doppler_processor.v" \
|
||||
"${rtl_dir}/edge_detector.v" \
|
||||
"${rtl_dir}/fir_lowpass.v" \
|
||||
"${rtl_dir}/frequency_matched_filter.v" \
|
||||
"${rtl_dir}/latency_buffer.v" \
|
||||
"${rtl_dir}/matched_filter_multi_segment.v" \
|
||||
"${rtl_dir}/matched_filter_processing_chain.v" \
|
||||
"${rtl_dir}/nco_400m_enhanced.v" \
|
||||
"${rtl_dir}/plfm_chirp_controller.v" \
|
||||
"${rtl_dir}/radar_mode_controller.v" \
|
||||
"${rtl_dir}/radar_receiver_final.v" \
|
||||
"${rtl_dir}/radar_system_top.v" \
|
||||
"${rtl_dir}/radar_transmitter.v" \
|
||||
"${rtl_dir}/range_bin_decimator.v" \
|
||||
"${rtl_dir}/rx_gain_control.v" \
|
||||
"${rtl_dir}/mti_canceller.v" \
|
||||
"${rtl_dir}/cfar_ca.v" \
|
||||
"${rtl_dir}/fpga_self_test.v" \
|
||||
"${rtl_dir}/usb_data_interface.v" \
|
||||
"${rtl_dir}/xfft_16.v" \
|
||||
"${rtl_dir}/fft_engine.v" \
|
||||
]
|
||||
|
||||
set file_count 0
|
||||
foreach f $rtl_files {
|
||||
if {[file exists $f]} {
|
||||
add_files -norecurse $f
|
||||
incr file_count
|
||||
} else {
|
||||
puts " WARNING: RTL file not found: $f"
|
||||
}
|
||||
}
|
||||
puts " Added $file_count RTL files"
|
||||
|
||||
# Add .mem files for BRAM initialization
|
||||
set mem_files [glob -nocomplain "${rtl_dir}/*.mem"]
|
||||
foreach f $mem_files {
|
||||
add_files -norecurse $f
|
||||
puts " Added MEM: [file tail $f]"
|
||||
}
|
||||
|
||||
# Add constraints — main production XDC + MMCM supplementary XDC (FIXED)
|
||||
add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"]
|
||||
add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "adc_clk_mmcm.xdc"]
|
||||
|
||||
set_property top $top_module [current_fileset]
|
||||
set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
|
||||
|
||||
# ==============================================================================
|
||||
# 2. Synthesis
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 1/5: Synthesis"
|
||||
puts "================================================================"
|
||||
|
||||
set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY rebuilt [get_runs synth_1]
|
||||
set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_1]
|
||||
|
||||
set synth_start [clock seconds]
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
set synth_elapsed [expr {[clock seconds] - $synth_start}]
|
||||
|
||||
set synth_status [get_property STATUS [get_runs synth_1]]
|
||||
puts " Synthesis status: $synth_status"
|
||||
puts " Synthesis time: ${synth_elapsed}s ([expr {$synth_elapsed/60}]m [expr {$synth_elapsed%60}]s)"
|
||||
|
||||
if {[string match "*ERROR*" $synth_status] || [string match "*FAILED*" $synth_status]} {
|
||||
puts "CRITICAL: SYNTHESIS FAILED — aborting build"
|
||||
close_project
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Post-synth timing (for comparison)
|
||||
open_run synth_1 -name synth_1
|
||||
report_timing_summary -delay_type min_max -max_paths 10 -file "${report_dir}/01_timing_post_synth.rpt"
|
||||
report_utilization -file "${report_dir}/01_utilization_post_synth.rpt"
|
||||
close_design
|
||||
|
||||
# ==============================================================================
|
||||
# 3. Implementation (opt → place → phys_opt → route → post_route_phys_opt)
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 2/5: Implementation"
|
||||
puts "================================================================"
|
||||
|
||||
# Aggressive directives for best timing
|
||||
set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
|
||||
set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE ExtraTimingOpt [get_runs impl_1]
|
||||
set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
||||
set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
|
||||
set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
||||
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
|
||||
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
|
||||
|
||||
set impl_start [clock seconds]
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
set impl_elapsed [expr {[clock seconds] - $impl_start}]
|
||||
|
||||
set impl_status [get_property STATUS [get_runs impl_1]]
|
||||
puts " Implementation status: $impl_status"
|
||||
puts " Implementation time: ${impl_elapsed}s ([expr {$impl_elapsed/60}]m [expr {$impl_elapsed%60}]s)"
|
||||
|
||||
if {![string match "*Complete*" $impl_status] && ![string match "*write_bitstream*" $impl_status]} {
|
||||
puts "CRITICAL: IMPLEMENTATION FAILED: $impl_status"
|
||||
close_project
|
||||
exit 1
|
||||
}
|
||||
|
||||
# ==============================================================================
|
||||
# 4. Bitstream Generation
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 3/5: Bitstream Generation"
|
||||
puts "================================================================"
|
||||
|
||||
set bit_start [clock seconds]
|
||||
# Handle case where Vivado auto-proceeds to write_bitstream after impl
|
||||
if {[catch {launch_runs impl_1 -to_step write_bitstream -jobs 8} launch_err]} {
|
||||
puts " Note: write_bitstream may already be in progress: $launch_err"
|
||||
}
|
||||
wait_on_run impl_1
|
||||
set bit_elapsed [expr {[clock seconds] - $bit_start}]
|
||||
puts " Bitstream time: ${bit_elapsed}s"
|
||||
|
||||
# Copy bitstream to known location
|
||||
set bit_src "${project_dir}/aeris10_radar.runs/impl_1/${top_module}.bit"
|
||||
if {[file exists $bit_src]} {
|
||||
file copy -force $bit_src "${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||||
puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||||
puts " Size: [file size $bit_src] bytes"
|
||||
} else {
|
||||
puts " WARNING: Bitstream file not found at $bit_src"
|
||||
}
|
||||
|
||||
# ==============================================================================
|
||||
# 5. Comprehensive Report Generation
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 4/5: Report Generation (15-point checklist)"
|
||||
puts "================================================================"
|
||||
|
||||
# Open the routed design for reporting
|
||||
open_run impl_1 -name impl_1
|
||||
|
||||
# --- Checklist Item 2: Timing Summary ---
|
||||
puts " [2/15] Timing Summary..."
|
||||
report_timing_summary -delay_type min_max -max_paths 100 \
|
||||
-report_unconstrained \
|
||||
-file "${report_dir}/02_timing_summary.rpt"
|
||||
|
||||
# --- Checklist Item 3: Clock Analysis ---
|
||||
puts " [3/15] Clock Analysis..."
|
||||
report_clocks -file "${report_dir}/03_clocks.rpt"
|
||||
report_clock_interaction -delay_type min_max \
|
||||
-file "${report_dir}/03_clock_interaction.rpt"
|
||||
report_clock_networks -file "${report_dir}/03_clock_networks.rpt"
|
||||
|
||||
# --- Checklist Item 4: Utilization ---
|
||||
puts " [4/15] Utilization..."
|
||||
report_utilization -file "${report_dir}/04_utilization.rpt"
|
||||
report_utilization -hierarchical -file "${report_dir}/04_utilization_hierarchical.rpt"
|
||||
|
||||
# --- Checklist Item 5: Power ---
|
||||
puts " [5/15] Power Report..."
|
||||
report_power -file "${report_dir}/05_power.rpt"
|
||||
|
||||
# --- Checklist Item 6: DRC ---
|
||||
puts " [6/15] DRC..."
|
||||
report_drc -file "${report_dir}/06_drc.rpt"
|
||||
|
||||
# --- Checklist Item 7: IO and Constraints ---
|
||||
puts " [7/15] IO Report..."
|
||||
report_io -file "${report_dir}/07_io.rpt"
|
||||
report_timing -from [all_inputs] -to [all_outputs] -max_paths 20 \
|
||||
-file "${report_dir}/07_io_timing.rpt"
|
||||
|
||||
# --- Checklist Item 8: Congestion Analysis ---
|
||||
puts " [8/15] Congestion Analysis..."
|
||||
report_design_analysis -congestion -file "${report_dir}/08_congestion.rpt"
|
||||
|
||||
# --- Checklist Item 9: Route Status ---
|
||||
puts " [9/15] Route Status..."
|
||||
report_route_status -file "${report_dir}/09_route_status.rpt"
|
||||
|
||||
# --- Checklist Item 10: Critical Paths ---
|
||||
puts " [10/15] Critical Paths..."
|
||||
report_timing -max_paths 20 -sort_by slack -nworst 5 \
|
||||
-file "${report_dir}/10_critical_paths_setup.rpt"
|
||||
report_timing -delay_type min -max_paths 20 -sort_by slack -nworst 5 \
|
||||
-file "${report_dir}/10_critical_paths_hold.rpt"
|
||||
report_high_fanout_nets -timing -load_type -max_nets 20 \
|
||||
-file "${report_dir}/10_high_fanout_nets.rpt"
|
||||
|
||||
# --- Checklist Item 11: QoR Summary ---
|
||||
puts " [11/15] QoR Summary..."
|
||||
report_design_analysis -timing -file "${report_dir}/11_design_analysis_timing.rpt"
|
||||
report_design_analysis -logic_level_distribution -file "${report_dir}/11_logic_level_dist.rpt"
|
||||
report_methodology -file "${report_dir}/11_methodology.rpt"
|
||||
|
||||
# --- Checklist Item 12: CDC Analysis ---
|
||||
puts " [12/15] CDC Analysis..."
|
||||
report_cdc -details -file "${report_dir}/12_cdc.rpt"
|
||||
|
||||
# --- Checklist Item 13: Log Scan (captured separately in build log) ---
|
||||
puts " [13/15] Log scan — see build20.log"
|
||||
|
||||
# --- Additional reports ---
|
||||
puts " \[extra\] Generating additional diagnostic reports..."
|
||||
|
||||
# report_exceptions can fail in Vivado 2025.2 — wrap in catch
|
||||
if {[catch {report_exceptions -file "${report_dir}/13_exceptions.rpt"} err]} {
|
||||
puts " WARNING: report_exceptions failed: $err"
|
||||
puts " (Known Vivado 2025.2 issue — non-critical)"
|
||||
}
|
||||
check_timing -verbose -file "${report_dir}/13_check_timing.rpt"
|
||||
|
||||
# Compile configuration summary into a single text file
|
||||
set summary_fh [open "${report_dir}/00_build20_summary.txt" w]
|
||||
puts $summary_fh "================================================================"
|
||||
puts $summary_fh " AERIS-10 Build 20 — MMCM XDC Fix + CIC CREG Pipeline"
|
||||
puts $summary_fh "================================================================"
|
||||
puts $summary_fh ""
|
||||
puts $summary_fh "Build Tag: $build_tag"
|
||||
puts $summary_fh "Build Timestamp: $build_timestamp"
|
||||
puts $summary_fh "FPGA Part: $fpga_part"
|
||||
puts $summary_fh "Top Module: $top_module"
|
||||
puts $summary_fh "RTL Files: $file_count"
|
||||
puts $summary_fh "Synth Status: $synth_status"
|
||||
puts $summary_fh "Synth Time: ${synth_elapsed}s"
|
||||
puts $summary_fh "Impl Status: $impl_status"
|
||||
puts $summary_fh "Impl Time: ${impl_elapsed}s"
|
||||
puts $summary_fh "Bitstream Time: ${bit_elapsed}s"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Extract key timing numbers — use catch to handle empty STATS properties
|
||||
# (Vivado 2025.2 may return empty strings after write_bitstream auto-launch)
|
||||
puts $summary_fh "--- Timing ---"
|
||||
if {[catch {set wns [get_property STATS.WNS [current_design]]}] || $wns eq ""} { set wns "N/A" }
|
||||
if {[catch {set tns [get_property STATS.TNS [current_design]]}] || $tns eq ""} { set tns "N/A" }
|
||||
if {[catch {set whs [get_property STATS.WHS [current_design]]}] || $whs eq ""} { set whs "N/A" }
|
||||
if {[catch {set ths [get_property STATS.THS [current_design]]}] || $ths eq ""} { set ths "N/A" }
|
||||
if {[catch {set fail_ep [get_property STATS.TPWS [current_design]]}] || $fail_ep eq ""} { set fail_ep "N/A" }
|
||||
puts $summary_fh " WNS: $wns ns"
|
||||
puts $summary_fh " TNS: $tns ns"
|
||||
puts $summary_fh " WHS: $whs ns"
|
||||
puts $summary_fh " THS: $ths ns"
|
||||
puts $summary_fh ""
|
||||
puts $summary_fh " Build 18 Baseline: WNS = +0.062 ns, WHS = +0.059 ns"
|
||||
puts $summary_fh " Build 19 (FAILED): WNS = -0.011 ns, WHS = +0.055 ns"
|
||||
if {[string is double -strict $wns]} {
|
||||
puts $summary_fh " Delta WNS vs B18: [expr {$wns - 0.062}] ns"
|
||||
} else {
|
||||
puts $summary_fh " Delta WNS vs B18: N/A (timing stats unavailable)"
|
||||
}
|
||||
if {[string is double -strict $whs]} {
|
||||
puts $summary_fh " Delta WHS vs B18: [expr {$whs - 0.059}] ns"
|
||||
} else {
|
||||
puts $summary_fh " Delta WHS vs B18: N/A (timing stats unavailable)"
|
||||
}
|
||||
puts $summary_fh ""
|
||||
|
||||
# Extract utilization
|
||||
puts $summary_fh "--- Utilization ---"
|
||||
set lut_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.LUT.*}]]
|
||||
set ff_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.FF.*}]]
|
||||
set bram_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ BMEM.*}]]
|
||||
set dsp_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ MULT.DSP.*}]]
|
||||
puts $summary_fh " LUTs: $lut_used / 134600"
|
||||
puts $summary_fh " FFs: $ff_used / 269200"
|
||||
puts $summary_fh " BRAM: $bram_used cells"
|
||||
puts $summary_fh " DSP: $dsp_used cells"
|
||||
puts $summary_fh ""
|
||||
puts $summary_fh " Build 18 Baseline: LUTs=6088, FFs=8946, BRAM=16, DSP=140"
|
||||
puts $summary_fh " Build 19: LUTs=6093, FFs=8949, BRAM=16, DSP=140"
|
||||
puts $summary_fh " Expected Build 20: DSP=142 (+2 for comb_0_dsp I/Q)"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Route status
|
||||
set unrouted [llength [get_nets -hierarchical -filter {ROUTE_STATUS == UNROUTED}]]
|
||||
puts $summary_fh "--- Route ---"
|
||||
puts $summary_fh " Unrouted nets: $unrouted"
|
||||
puts $summary_fh ""
|
||||
|
||||
# MMCM usage
|
||||
puts $summary_fh "--- MMCM Usage (Gap 7) ---"
|
||||
set mmcm_count [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLOCK.MMCM.*}]]
|
||||
puts $summary_fh " MMCME2 used: $mmcm_count / 10"
|
||||
puts $summary_fh " Expected: 1 (adc_clk_mmcm jitter cleaner)"
|
||||
puts $summary_fh ""
|
||||
|
||||
# Bitstream
|
||||
if {[file exists $bit_src]} {
|
||||
puts $summary_fh "--- Bitstream ---"
|
||||
puts $summary_fh " File: ${top_module}_${build_tag}.bit"
|
||||
puts $summary_fh " Size: [file size $bit_src] bytes"
|
||||
} else {
|
||||
puts $summary_fh "--- Bitstream ---"
|
||||
puts $summary_fh " WARNING: NOT GENERATED"
|
||||
}
|
||||
puts $summary_fh ""
|
||||
|
||||
# Signoff
|
||||
puts $summary_fh "--- Final Signoff ---"
|
||||
set signoff_pass 1
|
||||
if {![string is double -strict $wns]} {
|
||||
puts $summary_fh " WARN: WNS = N/A (timing stats unavailable — check reports)"
|
||||
} elseif {$wns < 0} {
|
||||
puts $summary_fh " FAIL: WNS = $wns (negative slack)"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: WNS = $wns ns (no setup violations)"
|
||||
}
|
||||
if {![string is double -strict $whs]} {
|
||||
puts $summary_fh " WARN: WHS = N/A (timing stats unavailable — check reports)"
|
||||
} elseif {$whs < 0} {
|
||||
puts $summary_fh " FAIL: WHS = $whs (hold violation)"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: WHS = $whs ns (no hold violations)"
|
||||
}
|
||||
if {![string is double -strict $tns]} {
|
||||
puts $summary_fh " WARN: TNS = N/A (timing stats unavailable — check reports)"
|
||||
} elseif {$tns != 0} {
|
||||
puts $summary_fh " FAIL: TNS = $tns (total negative slack)"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: TNS = 0 ns"
|
||||
}
|
||||
if {$unrouted > 0} {
|
||||
puts $summary_fh " FAIL: $unrouted unrouted nets"
|
||||
set signoff_pass 0
|
||||
} else {
|
||||
puts $summary_fh " PASS: All nets routed"
|
||||
}
|
||||
if {[file exists $bit_src]} {
|
||||
puts $summary_fh " PASS: Bitstream generated"
|
||||
} else {
|
||||
puts $summary_fh " FAIL: No bitstream"
|
||||
set signoff_pass 0
|
||||
}
|
||||
puts $summary_fh ""
|
||||
|
||||
# Timing regression check vs Build 18
|
||||
if {[string is double -strict $wns] && $wns < 0.062} {
|
||||
puts $summary_fh " *** WARNING: WNS REGRESSED vs Build 18 (was +0.062 ns, now $wns ns) ***"
|
||||
puts $summary_fh " *** Review critical paths — CREG fix may not have helped ***"
|
||||
}
|
||||
if {[string is double -strict $whs] && $whs < 0.059} {
|
||||
puts $summary_fh " *** WARNING: WHS REGRESSED vs Build 18 (was +0.059 ns, now $whs ns) ***"
|
||||
}
|
||||
|
||||
if {$signoff_pass} {
|
||||
puts $summary_fh " *** SIGNOFF: PASS ***"
|
||||
} else {
|
||||
puts $summary_fh " *** SIGNOFF: FAIL ***"
|
||||
}
|
||||
|
||||
close $summary_fh
|
||||
puts " Summary written to: ${report_dir}/00_build20_summary.txt"
|
||||
|
||||
# ==============================================================================
|
||||
# 6. SDF + Timing Netlist (for post-route simulation)
|
||||
# ==============================================================================
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " Phase 5/5: SDF + Timing Netlist"
|
||||
puts "================================================================"
|
||||
|
||||
write_verilog -force -mode timesim "${sim_dir}/post_impl_timesim.v"
|
||||
write_sdf -force "${sim_dir}/post_impl_timesim.sdf"
|
||||
|
||||
close_design
|
||||
open_run synth_1 -name synth_1
|
||||
write_verilog -force -mode funcsim "${sim_dir}/post_synth_funcsim.v"
|
||||
|
||||
# ==============================================================================
|
||||
# Done
|
||||
# ==============================================================================
|
||||
|
||||
set build_total [expr {[clock seconds] - $build_start}]
|
||||
set build_end [clock format [clock seconds] -format {%Y-%m-%d %H:%M:%S}]
|
||||
|
||||
puts ""
|
||||
puts "================================================================"
|
||||
puts " BUILD 20 COMPLETE"
|
||||
puts "================================================================"
|
||||
puts " Started: $build_timestamp"
|
||||
puts " Finished: $build_end"
|
||||
puts " Total time: ${build_total}s ([expr {$build_total/60}]m [expr {$build_total%60}]s)"
|
||||
puts " Synth: ${synth_elapsed}s"
|
||||
puts " Impl: ${impl_elapsed}s"
|
||||
puts " Bitstream: ${bit_elapsed}s"
|
||||
puts " Reports: $report_dir"
|
||||
puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||||
puts " WNS: $wns ns | WHS: $whs ns | TNS: $tns ns"
|
||||
puts " Build 18 baseline: WNS +0.062 | WHS +0.059"
|
||||
puts " Build 19 (failed): WNS -0.011 | WHS +0.055"
|
||||
if {$signoff_pass} {
|
||||
puts " SIGNOFF: PASS"
|
||||
} else {
|
||||
puts " SIGNOFF: FAIL"
|
||||
}
|
||||
puts "================================================================"
|
||||
|
||||
close_project
|
||||
puts "Done."
|
||||
+1
-1
@@ -11,7 +11,7 @@
|
||||
# pins and placeholder LED/status pins.
|
||||
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
set project_root [file normalize [file join $script_dir ".."]]
|
||||
set project_root [file normalize [file join $script_dir "../.."]]
|
||||
|
||||
set project_name "aeris10_te0712_dev"
|
||||
set build_dir [file join $project_root "vivado_te0712_dev"]
|
||||
+1
-1
@@ -6,7 +6,7 @@
|
||||
# vivado -mode batch -source scripts/build_te0713_dev.tcl
|
||||
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
set project_root [file normalize [file join $script_dir ".."]]
|
||||
set project_root [file normalize [file join $script_dir "../.."]]
|
||||
|
||||
set project_name "aeris10_te0713_dev"
|
||||
set build_dir [file join $project_root "vivado_te0713_dev"]
|
||||
+1
-1
@@ -3,7 +3,7 @@
|
||||
# Vivado batch build for Trenz TE0713/TE0701 with UMFT601X-B over FMC LPC.
|
||||
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
set project_root [file normalize [file join $script_dir ".."]]
|
||||
set project_root [file normalize [file join $script_dir "../.."]]
|
||||
|
||||
set project_name "aeris10_te0713_umft601x_dev"
|
||||
set build_dir [file join $project_root "vivado_te0713_umft601x_dev"]
|
||||
+1
-1
@@ -35,7 +35,7 @@
|
||||
set default_server "localhost"
|
||||
set default_port 3121
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
set project_root [file normalize [file join $script_dir ".."]]
|
||||
set project_root [file normalize [file join $script_dir "../.."]]
|
||||
set default_ltx [file join $project_root "build" "aeris10_radar.runs" "impl_ila" "radar_system_top.ltx"]
|
||||
set default_output_base [file join $project_root "build" "captures"]
|
||||
set default_depth 4096
|
||||
+1
-1
@@ -33,7 +33,7 @@
|
||||
# ==============================================================================
|
||||
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
set project_root [file normalize [file join $script_dir ".."]]
|
||||
set project_root [file normalize [file join $script_dir "../.."]]
|
||||
set project_base [file join $project_root "build"]
|
||||
set synth_dcp "${project_base}/aeris10_radar.runs/synth_1/radar_system_top.dcp"
|
||||
set synth_xdc [file join $project_root "constraints" "xc7a200t_fbg484.xdc"]
|
||||
+1
-1
@@ -26,7 +26,7 @@
|
||||
set default_server "localhost"
|
||||
set default_port 3121
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
set project_root [file normalize [file join $script_dir ".."]]
|
||||
set project_root [file normalize [file join $script_dir "../.."]]
|
||||
set default_bit [file join $project_root "build" "bitstream" "radar_system_top_build21.bit"]
|
||||
set default_ltx [file join $project_root "build" "aeris10_radar.runs" "impl_ila" "radar_system_top.ltx"]
|
||||
set expected_part "xc7a200t"
|
||||
+1
-1
@@ -6,7 +6,7 @@
|
||||
# Usage: vivado -mode batch -source run_cdc_and_netlist.tcl
|
||||
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
set project_root [file normalize [file join $script_dir ".."]]
|
||||
set project_root [file normalize [file join $script_dir "../.."]]
|
||||
set project_dir [file join $project_root "build"]
|
||||
set report_dir "${project_dir}/reports_impl"
|
||||
file mkdir $report_dir
|
||||
Reference in New Issue
Block a user