From 849b32240bd1f8a4c1bf4a3ede899a07a8707153 Mon Sep 17 00:00:00 2001 From: Jason <83615043+JJassonn69@users.noreply.github.com> Date: Tue, 7 Apr 2026 15:13:13 +0300 Subject: [PATCH] fix(xdc): add hold false_path for ADC IDDR + reorganize build scripts by target - Add set_false_path -hold for source-synchronous ADC IDDR paths in adc_clk_mmcm.xdc (eliminates 8 hold violations from build 12) - Add DDR falling-edge input delay constraints to xc7a50t_ftg256.xdc (parity with 200T XDC) - Reorganize scripts/ into target subdirectories: 50t/, 200t/, te0712/, te0713/, utils/ so users can run the correct build for their hardware - Delete obsolete build scripts (build17-20) superseded by build_50t/200t - Update project_root paths in all moved scripts (.. -> ../..) --- .../9_2_FPGA/constraints/adc_clk_mmcm.xdc | 26 +- .../9_2_FPGA/constraints/xc7a50t_ftg256.xdc | 3 + .../build_200t.tcl} | 40 +- .../{build_50t_test.tcl => 50t/build_50t.tcl} | 8 +- .../9_2_FPGA/scripts/build17_production.tcl | 460 ---------------- .../9_2_FPGA/scripts/build18_production.tcl | 470 ---------------- 9_Firmware/9_2_FPGA/scripts/build19_mmcm.tcl | 493 ----------------- .../9_2_FPGA/scripts/build20_mmcm_creg.tcl | 501 ------------------ .../scripts/{ => te0712}/build_te0712_dev.tcl | 2 +- .../scripts/{ => te0713}/build_te0713_dev.tcl | 2 +- .../build_te0713_umft601x_dev.tcl | 2 +- .../scripts/{ => utils}/ila_capture.tcl | 2 +- .../scripts/{ => utils}/insert_ila_probes.tcl | 2 +- .../scripts/{ => utils}/program_fpga.tcl | 2 +- .../{ => utils}/run_cdc_and_netlist.tcl | 2 +- 15 files changed, 41 insertions(+), 1974 deletions(-) rename 9_Firmware/9_2_FPGA/scripts/{build21_fft_e2e.tcl => 200t/build_200t.tcl} (92%) rename 9_Firmware/9_2_FPGA/scripts/{build_50t_test.tcl => 50t/build_50t.tcl} (95%) delete mode 100644 9_Firmware/9_2_FPGA/scripts/build17_production.tcl delete mode 100644 9_Firmware/9_2_FPGA/scripts/build18_production.tcl delete mode 100644 9_Firmware/9_2_FPGA/scripts/build19_mmcm.tcl delete mode 100644 9_Firmware/9_2_FPGA/scripts/build20_mmcm_creg.tcl rename 9_Firmware/9_2_FPGA/scripts/{ => te0712}/build_te0712_dev.tcl (96%) rename 9_Firmware/9_2_FPGA/scripts/{ => te0713}/build_te0713_dev.tcl (96%) rename 9_Firmware/9_2_FPGA/scripts/{ => te0713}/build_te0713_umft601x_dev.tcl (97%) rename 9_Firmware/9_2_FPGA/scripts/{ => utils}/ila_capture.tcl (99%) rename 9_Firmware/9_2_FPGA/scripts/{ => utils}/insert_ila_probes.tcl (99%) rename 9_Firmware/9_2_FPGA/scripts/{ => utils}/program_fpga.tcl (99%) rename 9_Firmware/9_2_FPGA/scripts/{ => utils}/run_cdc_and_netlist.tcl (96%) diff --git a/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc b/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc index cb9651d..b581940 100644 --- a/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc +++ b/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc @@ -62,12 +62,24 @@ set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_mmcm_out0] set_false_path -through [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED] # -------------------------------------------------------------------------- -# Hold waiver for BUFIO→MMCM domain transfer (if Vivado flags hold violations) +# Hold waiver for source-synchronous ADC capture (BUFIO-clocked IDDR) # -------------------------------------------------------------------------- -# The existing hold waiver for BUFIO source-synchronous capture stays: -# set_false_path -hold -from [get_ports {adc_d_p[*]}] -to [get_clocks adc_dco_p] +# The AD9484 ADC provides a source-synchronous interface: data (adc_d_p/n) +# and clock (adc_dco_p/n) are output from the same chip with matched timing. +# On the PCB, data and DCO traces are length-matched. # -# The MMCM BUFG re-registration of IDDR outputs: since BUFIO and MMCM output -# are derived from the same IBUFDS source, hold is inherently met (MMCM adds -# insertion delay). If Vivado flags hold violations on this transfer, uncomment: -# set_false_path -hold -from [get_clocks adc_dco_p] -to [get_clocks clk_mmcm_out0] +# Inside the FPGA, the DCO clock path goes through IBUFDS → BUFIO, adding +# ~2.2ns of insertion delay (IBUFDS 0.9ns + routing 0.6ns + BUFIO 1.3ns). +# The data path goes through IBUFDS only (~0.85ns), arriving at the IDDR +# ~1.4ns before the clock. Vivado's hold analysis sees the data "changing" +# before the clock edge and reports WHS = -1.955ns. +# +# This is correct internal behavior: the BUFIO clock intentionally arrives +# after the data. The IDDR captures on the BUFIO edge, by which time the +# data is stable. Hold timing is guaranteed by the external PCB layout +# (ADC data valid window centered on DCO edge), not by FPGA clock tree +# delays. Vivado's STA model cannot account for this external relationship. +# +# Waiving hold on these 8 paths (adc_d_p[0..7] → IDDR) is standard practice +# for source-synchronous LVDS ADC interfaces using BUFIO capture. +set_false_path -hold -from [get_ports {adc_d_p[*]}] -to [get_clocks adc_dco_p] diff --git a/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc b/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc index 35c084b..43c922c 100644 --- a/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc +++ b/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc @@ -255,8 +255,11 @@ set_property IOSTANDARD LVDS_25 [get_ports {adc_d_n[*]}] set_property DIFF_TERM TRUE [get_ports {adc_d_p[*]}] # Input delay for ADC data relative to DCO (adjust based on PCB trace length) +# DDR interface: constrain both rising and falling clock edges set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 [get_ports {adc_d_p[*]}] set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_d_p[*]}] +set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_d_p[*]}] -add_delay +set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_d_p[*]}] -add_delay # ============================================================================ # FT601 USB 3.0 INTERFACE — ACTIVE: NO PHYSICAL CONNECTIONS diff --git a/9_Firmware/9_2_FPGA/scripts/build21_fft_e2e.tcl b/9_Firmware/9_2_FPGA/scripts/200t/build_200t.tcl similarity index 92% rename from 9_Firmware/9_2_FPGA/scripts/build21_fft_e2e.tcl rename to 9_Firmware/9_2_FPGA/scripts/200t/build_200t.tcl index f73ae11..2f2b876 100644 --- a/9_Firmware/9_2_FPGA/scripts/build21_fft_e2e.tcl +++ b/9_Firmware/9_2_FPGA/scripts/200t/build_200t.tcl @@ -1,42 +1,14 @@ ################################################################################ -# build21_fft_e2e.tcl +# build_200t.tcl — XC7A200T Dev Board Build +# AERIS-10 Build for the 200T development board (FBG484) # -# AERIS-10 Build 21: FFT Optimizations + E2E RTL Fixes # Target: XC7A200T-2FBG484I # Design: radar_system_top -# Base: Build 20 (v0.1.3-build20, WNS +0.426 ns) -# -# Changes vs Build 20: -# - fft_engine.v: merged SHIFT state into WRITE (5→4 cycle butterfly, -# 20% throughput gain). Twiddle index uses barrel-shift instead of -# multiplier (frees 1 DSP48). -# - plfm_chirp_controller.v: TX/RX mixer enables now mutually exclusive -# by FSM state (Fix #4). -# - usb_data_interface.v: stream control reset default 3'b001 (range-only), -# doppler/cfar data_pending sticky flags, write FSM triggers on -# range_valid only (Fix #5). -# - radar_receiver_final.v: STM32 toggle signal inputs for mode-00, -# dynamic frame detection via host_chirps_per_elev. -# - radar_system_top.v: STM32 toggle wiring to receiver instance. -# - chirp_memory_loader_param.v: explicit readmemh range for short chirp. -# -# Expected impact: -# - DSP48E1: 140 → 139 (−1 from barrel-shift twiddle, +0 net from -# FFT multiplier removal; CIC CREG DSPs unchanged) -# - LUT/FF: slight increase from USB data_pending logic + receiver -# toggle inputs. Slight decrease from FFT state removal. -# - Timing: should remain positive (Build 20 had +0.426 ns WNS). -# Gap 2 build (pre-FFT-opt) had +0.078 ns WNS with similar RTL. -# -# Generates ALL reports required for the 15-point Vivado TCL Build Report. # # Usage: -# vivado -mode batch -source build21_fft_e2e.tcl \ -# -log build/build21.log \ -# -journal build/build21.jou -# -# Author: auto-generated for Jason Stone -# Date: 2026-03-20 +# cd 9_Firmware/9_2_FPGA +# vivado -mode batch -source scripts/200t/build_200t.tcl \ +# -log build/build.log -journal build/build.jou ################################################################################ # ============================================================================== @@ -45,7 +17,7 @@ set project_name "aeris10_radar" set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] +set project_root [file normalize [file join $script_dir "../.."]] set project_dir [file join $project_root "build"] set rtl_dir $project_root set top_module "radar_system_top" diff --git a/9_Firmware/9_2_FPGA/scripts/build_50t_test.tcl b/9_Firmware/9_2_FPGA/scripts/50t/build_50t.tcl similarity index 95% rename from 9_Firmware/9_2_FPGA/scripts/build_50t_test.tcl rename to 9_Firmware/9_2_FPGA/scripts/50t/build_50t.tcl index f622d42..29d68b7 100644 --- a/9_Firmware/9_2_FPGA/scripts/build_50t_test.tcl +++ b/9_Firmware/9_2_FPGA/scripts/50t/build_50t.tcl @@ -1,11 +1,15 @@ ################################################################################ -# build_50t_test.tcl — XC7A50T Production Build +# build_50t.tcl — XC7A50T Production Build # Builds the AERIS-10 design targeting the production 50T (FTG256) board +# +# Usage: +# cd 9_Firmware/9_2_FPGA +# vivado -mode batch -source scripts/50t/build_50t.tcl 2>&1 | tee build_50t/vivado.log ################################################################################ set project_name "aeris10_radar_50t" set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] +set project_root [file normalize [file join $script_dir "../.."]] set project_dir [file join $project_root "build_50t"] set rtl_dir $project_root set fpga_part "xc7a50tftg256-2" diff --git a/9_Firmware/9_2_FPGA/scripts/build17_production.tcl b/9_Firmware/9_2_FPGA/scripts/build17_production.tcl deleted file mode 100644 index 91d4ef5..0000000 --- a/9_Firmware/9_2_FPGA/scripts/build17_production.tcl +++ /dev/null @@ -1,460 +0,0 @@ -################################################################################ -# build17_production.tcl -# -# AERIS-10 Build 17: Full Production Build + Comprehensive Report Suite -# Target: XC7A200T-2FBG484I -# Design: radar_system_top -# Tag: v0.1.0-bringup (commit 8ca6d99) -# -# Generates ALL reports required for the 15-point Vivado TCL Build Report -# Analysis Checklist: -# 1. Run Status (synth/opt/place/route completion) -# 2. Timing Summary (WNS/TNS/WHS) -# 3. Clock Analysis (report_clocks) -# 4. Utilization Report (LUT/FF/BRAM/DSP) -# 5. Power Report (dynamic/static/thermal) -# 6. DRC (Design Rule Check) -# 7. IO and Constraints (report_io, unconstrained ports) -# 8. Congestion Analysis (report_design_analysis -congestion) -# 9. Route Status (unrouted nets) -# 10. Critical Paths (report_timing -max_paths 20) -# 11. QoR Summary (report_qor_summary) -# 12. Incremental Compile comparison (timing vs Build 16) -# 13. Log File Scan (captured in build log) -# 14. Bitstream Generation (write_bitstream) -# 15. Final Signoff Criteria (all above combined) -# -# Usage: -# vivado -mode batch -source build17_production.tcl \ -# -log build/build17.log \ -# -journal build/build17.jou -# -# Author: auto-generated for Jason Stone -# Date: 2026-03-19 -################################################################################ - -# ============================================================================== -# 0. Configuration -# ============================================================================== - -set project_name "aeris10_radar" -set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] -set project_dir [file join $project_root "build"] -set rtl_dir $project_root -set top_module "radar_system_top" -set fpga_part "xc7a200tfbg484-2" -set report_dir "${project_dir}/reports_build17" -set sim_dir "${project_dir}/sim" -set bitstream_dir "${project_dir}/bitstream" -set build_tag "build17" - -file mkdir $report_dir -file mkdir $sim_dir -file mkdir $bitstream_dir - -# Record start time -set build_start [clock seconds] -set build_timestamp [clock format $build_start -format {%Y-%m-%d %H:%M:%S}] - -puts "================================================================" -puts " AERIS-10 Build 17: Full Production Build" -puts " Target: $fpga_part" -puts " Top: $top_module" -puts " Reports: $report_dir" -puts " Started: $build_timestamp" -puts "================================================================" - -# ============================================================================== -# 1. Project Creation + Source Files -# ============================================================================== - -create_project $project_name $project_dir -part $fpga_part -force -set_property target_language Verilog [current_project] - -# --- Add RTL sources --- -set rtl_files [list \ - "${rtl_dir}/ad9484_interface_400m.v" \ - "${rtl_dir}/cdc_modules.v" \ - "${rtl_dir}/chirp_memory_loader_param.v" \ - "${rtl_dir}/cic_decimator_4x_enhanced.v" \ - "${rtl_dir}/dac_interface_single.v" \ - "${rtl_dir}/ddc_400m.v" \ - "${rtl_dir}/ddc_input_interface.v" \ - "${rtl_dir}/doppler_processor.v" \ - "${rtl_dir}/edge_detector.v" \ - "${rtl_dir}/fir_lowpass.v" \ - "${rtl_dir}/frequency_matched_filter.v" \ - "${rtl_dir}/latency_buffer.v" \ - "${rtl_dir}/matched_filter_multi_segment.v" \ - "${rtl_dir}/matched_filter_processing_chain.v" \ - "${rtl_dir}/nco_400m_enhanced.v" \ - "${rtl_dir}/plfm_chirp_controller.v" \ - "${rtl_dir}/radar_mode_controller.v" \ - "${rtl_dir}/radar_receiver_final.v" \ - "${rtl_dir}/radar_system_top.v" \ - "${rtl_dir}/radar_transmitter.v" \ - "${rtl_dir}/range_bin_decimator.v" \ - "${rtl_dir}/rx_gain_control.v" \ - "${rtl_dir}/mti_canceller.v" \ - "${rtl_dir}/cfar_ca.v" \ - "${rtl_dir}/fpga_self_test.v" \ - "${rtl_dir}/usb_data_interface.v" \ - "${rtl_dir}/xfft_16.v" \ - "${rtl_dir}/fft_engine.v" \ - "${rtl_dir}/adc_clk_mmcm.v" \ -] - -set file_count 0 -foreach f $rtl_files { - if {[file exists $f]} { - add_files -norecurse $f - incr file_count - } else { - puts " WARNING: RTL file not found: $f" - } -} -puts " Added $file_count RTL files" - -# Add .mem files for BRAM initialization -set mem_files [glob -nocomplain "${rtl_dir}/*.mem"] -foreach f $mem_files { - add_files -norecurse $f - puts " Added MEM: [file tail $f]" -} - -# Add constraints -add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"] -set_property top $top_module [current_fileset] -set_property verilog_define {FFT_XPM_BRAM} [current_fileset] - -# ============================================================================== -# 2. Synthesis -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 1/5: Synthesis" -puts "================================================================" - -set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY rebuilt [get_runs synth_1] -set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_1] - -set synth_start [clock seconds] -launch_runs synth_1 -jobs 8 -wait_on_run synth_1 -set synth_elapsed [expr {[clock seconds] - $synth_start}] - -set synth_status [get_property STATUS [get_runs synth_1]] -puts " Synthesis status: $synth_status" -puts " Synthesis time: ${synth_elapsed}s ([expr {$synth_elapsed/60}]m [expr {$synth_elapsed%60}]s)" - -if {[string match "*ERROR*" $synth_status] || [string match "*FAILED*" $synth_status]} { - puts "CRITICAL: SYNTHESIS FAILED — aborting build" - close_project - exit 1 -} - -# Post-synth timing (for comparison) -open_run synth_1 -name synth_1 -report_timing_summary -delay_type min_max -max_paths 10 -file "${report_dir}/01_timing_post_synth.rpt" -report_utilization -file "${report_dir}/01_utilization_post_synth.rpt" -close_design - -# ============================================================================== -# 3. Implementation (opt → place → phys_opt → route → post_route_phys_opt) -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 2/5: Implementation" -puts "================================================================" - -# Aggressive directives for best timing -set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1] -set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE ExtraTimingOpt [get_runs impl_1] -set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] -set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] -set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] -set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] -set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] - -set impl_start [clock seconds] -launch_runs impl_1 -jobs 8 -wait_on_run impl_1 -set impl_elapsed [expr {[clock seconds] - $impl_start}] - -set impl_status [get_property STATUS [get_runs impl_1]] -puts " Implementation status: $impl_status" -puts " Implementation time: ${impl_elapsed}s ([expr {$impl_elapsed/60}]m [expr {$impl_elapsed%60}]s)" - -if {![string match "*Complete*" $impl_status] && ![string match "*write_bitstream*" $impl_status]} { - puts "CRITICAL: IMPLEMENTATION FAILED: $impl_status" - close_project - exit 1 -} - -# ============================================================================== -# 4. Bitstream Generation -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 3/5: Bitstream Generation" -puts "================================================================" - -set bit_start [clock seconds] -# Handle case where Vivado auto-proceeds to write_bitstream after impl -if {[catch {launch_runs impl_1 -to_step write_bitstream -jobs 8} launch_err]} { - puts " Note: write_bitstream may already be in progress: $launch_err" -} -wait_on_run impl_1 -set bit_elapsed [expr {[clock seconds] - $bit_start}] -puts " Bitstream time: ${bit_elapsed}s" - -# Copy bitstream to known location -set bit_src "${project_dir}/aeris10_radar.runs/impl_1/${top_module}.bit" -if {[file exists $bit_src]} { - file copy -force $bit_src "${bitstream_dir}/${top_module}_${build_tag}.bit" - puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit" - puts " Size: [file size $bit_src] bytes" -} else { - puts " WARNING: Bitstream file not found at $bit_src" -} - -# ============================================================================== -# 5. Comprehensive Report Generation -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 4/5: Report Generation (15-point checklist)" -puts "================================================================" - -# Open the routed design for reporting -open_run impl_1 -name impl_1 - -# --- Checklist Item 2: Timing Summary --- -puts " [2/15] Timing Summary..." -report_timing_summary -delay_type min_max -max_paths 100 \ - -report_unconstrained \ - -file "${report_dir}/02_timing_summary.rpt" - -# --- Checklist Item 3: Clock Analysis --- -puts " [3/15] Clock Analysis..." -report_clocks -file "${report_dir}/03_clocks.rpt" -report_clock_interaction -delay_type min_max \ - -file "${report_dir}/03_clock_interaction.rpt" -report_clock_networks -file "${report_dir}/03_clock_networks.rpt" - -# --- Checklist Item 4: Utilization --- -puts " [4/15] Utilization..." -report_utilization -file "${report_dir}/04_utilization.rpt" -report_utilization -hierarchical -file "${report_dir}/04_utilization_hierarchical.rpt" - -# --- Checklist Item 5: Power --- -puts " [5/15] Power Report..." -report_power -file "${report_dir}/05_power.rpt" - -# --- Checklist Item 6: DRC --- -puts " [6/15] DRC..." -report_drc -file "${report_dir}/06_drc.rpt" - -# --- Checklist Item 7: IO and Constraints --- -puts " [7/15] IO Report..." -report_io -file "${report_dir}/07_io.rpt" -report_timing -from [all_inputs] -to [all_outputs] -max_paths 20 \ - -file "${report_dir}/07_io_timing.rpt" - -# --- Checklist Item 8: Congestion Analysis --- -puts " [8/15] Congestion Analysis..." -report_design_analysis -congestion -file "${report_dir}/08_congestion.rpt" - -# --- Checklist Item 9: Route Status --- -puts " [9/15] Route Status..." -report_route_status -file "${report_dir}/09_route_status.rpt" - -# --- Checklist Item 10: Critical Paths --- -puts " [10/15] Critical Paths..." -report_timing -max_paths 20 -sort_by slack -nworst 5 \ - -file "${report_dir}/10_critical_paths_setup.rpt" -report_timing -delay_type min -max_paths 20 -sort_by slack -nworst 5 \ - -file "${report_dir}/10_critical_paths_hold.rpt" -report_high_fanout_nets -timing -load_type -max_nets 20 \ - -file "${report_dir}/10_high_fanout_nets.rpt" - -# --- Checklist Item 11: QoR Summary --- -puts " [11/15] QoR Summary..." -report_design_analysis -timing -file "${report_dir}/11_design_analysis_timing.rpt" -report_design_analysis -logic_level_distribution -file "${report_dir}/11_logic_level_dist.rpt" -report_methodology -file "${report_dir}/11_methodology.rpt" - -# --- Checklist Item 12: CDC Analysis --- -puts " [12/15] CDC Analysis..." -report_cdc -details -file "${report_dir}/12_cdc.rpt" - -# --- Checklist Item 13: Log Scan (captured separately in build log) --- -puts " [13/15] Log scan — see build17.log" - -# --- Additional reports --- -puts " \[extra\] Generating additional diagnostic reports..." - -# Check_timing for completeness -report_exceptions -file "${report_dir}/13_exceptions.rpt" -check_timing -verbose -file "${report_dir}/13_check_timing.rpt" - -# Compile configuration summary into a single text file -set summary_fh [open "${report_dir}/00_build17_summary.txt" w] -puts $summary_fh "================================================================" -puts $summary_fh " AERIS-10 Build 17 — Production Build Summary" -puts $summary_fh "================================================================" -puts $summary_fh "" -puts $summary_fh "Build Tag: $build_tag" -puts $summary_fh "Build Timestamp: $build_timestamp" -puts $summary_fh "FPGA Part: $fpga_part" -puts $summary_fh "Top Module: $top_module" -puts $summary_fh "RTL Files: $file_count" -puts $summary_fh "Synth Status: $synth_status" -puts $summary_fh "Synth Time: ${synth_elapsed}s" -puts $summary_fh "Impl Status: $impl_status" -puts $summary_fh "Impl Time: ${impl_elapsed}s" -puts $summary_fh "Bitstream Time: ${bit_elapsed}s" -puts $summary_fh "" - -# Extract key timing numbers — use catch to handle empty STATS properties -# (Vivado 2025.2 may return empty strings after write_bitstream auto-launch) -puts $summary_fh "--- Timing ---" -if {[catch {set wns [get_property STATS.WNS [current_design]]}] || $wns eq ""} { set wns "N/A" } -if {[catch {set tns [get_property STATS.TNS [current_design]]}] || $tns eq ""} { set tns "N/A" } -if {[catch {set whs [get_property STATS.WHS [current_design]]}] || $whs eq ""} { set whs "N/A" } -if {[catch {set ths [get_property STATS.THS [current_design]]}] || $ths eq ""} { set ths "N/A" } -if {[catch {set fail_ep [get_property STATS.TPWS [current_design]]}] || $fail_ep eq ""} { set fail_ep "N/A" } -puts $summary_fh " WNS: $wns ns" -puts $summary_fh " TNS: $tns ns" -puts $summary_fh " WHS: $whs ns" -puts $summary_fh " THS: $ths ns" -puts $summary_fh "" - -# Extract utilization -puts $summary_fh "--- Utilization ---" -set lut_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.LUT.*}]] -set ff_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.FF.*}]] -set bram_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ BMEM.*}]] -set dsp_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ MULT.DSP.*}]] -puts $summary_fh " LUTs: $lut_used / 134600" -puts $summary_fh " FFs: $ff_used / 269200" -puts $summary_fh " BRAM: $bram_used cells" -puts $summary_fh " DSP: $dsp_used cells" -puts $summary_fh "" - -# Route status -set unrouted [llength [get_nets -hierarchical -filter {ROUTE_STATUS == UNROUTED}]] -puts $summary_fh "--- Route ---" -puts $summary_fh " Unrouted nets: $unrouted" -puts $summary_fh "" - -# Bitstream -if {[file exists $bit_src]} { - puts $summary_fh "--- Bitstream ---" - puts $summary_fh " File: ${top_module}_${build_tag}.bit" - puts $summary_fh " Size: [file size $bit_src] bytes" -} else { - puts $summary_fh "--- Bitstream ---" - puts $summary_fh " WARNING: NOT GENERATED" -} -puts $summary_fh "" - -# Signoff -puts $summary_fh "--- Final Signoff ---" -set signoff_pass 1 -if {![string is double -strict $wns]} { - puts $summary_fh " WARN: WNS = N/A (timing stats unavailable — check reports)" -} elseif {$wns < 0} { - puts $summary_fh " FAIL: WNS = $wns (negative slack)" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: WNS = $wns ns (no setup violations)" -} -if {![string is double -strict $whs]} { - puts $summary_fh " WARN: WHS = N/A (timing stats unavailable — check reports)" -} elseif {$whs < 0} { - puts $summary_fh " FAIL: WHS = $whs (hold violation)" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: WHS = $whs ns (no hold violations)" -} -if {![string is double -strict $tns]} { - puts $summary_fh " WARN: TNS = N/A (timing stats unavailable — check reports)" -} elseif {$tns != 0} { - puts $summary_fh " FAIL: TNS = $tns (total negative slack)" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: TNS = 0 ns" -} -if {$unrouted > 0} { - puts $summary_fh " FAIL: $unrouted unrouted nets" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: All nets routed" -} -if {[file exists $bit_src]} { - puts $summary_fh " PASS: Bitstream generated" -} else { - puts $summary_fh " FAIL: No bitstream" - set signoff_pass 0 -} -puts $summary_fh "" -if {$signoff_pass} { - puts $summary_fh " *** SIGNOFF: PASS ***" -} else { - puts $summary_fh " *** SIGNOFF: FAIL ***" -} - -close $summary_fh -puts " Summary written to: ${report_dir}/00_build17_summary.txt" - -# ============================================================================== -# 6. SDF + Timing Netlist (for post-route simulation) -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 5/5: SDF + Timing Netlist" -puts "================================================================" - -write_verilog -force -mode timesim "${sim_dir}/post_impl_timesim.v" -write_sdf -force "${sim_dir}/post_impl_timesim.sdf" - -close_design -open_run synth_1 -name synth_1 -write_verilog -force -mode funcsim "${sim_dir}/post_synth_funcsim.v" - -# ============================================================================== -# Done -# ============================================================================== - -set build_total [expr {[clock seconds] - $build_start}] -set build_end [clock format [clock seconds] -format {%Y-%m-%d %H:%M:%S}] - -puts "" -puts "================================================================" -puts " BUILD 17 COMPLETE" -puts "================================================================" -puts " Started: $build_timestamp" -puts " Finished: $build_end" -puts " Total time: ${build_total}s ([expr {$build_total/60}]m [expr {$build_total%60}]s)" -puts " Synth: ${synth_elapsed}s" -puts " Impl: ${impl_elapsed}s" -puts " Bitstream: ${bit_elapsed}s" -puts " Reports: $report_dir" -puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit" -puts " WNS: $wns ns | WHS: $whs ns | TNS: $tns ns" -if {$signoff_pass} { - puts " SIGNOFF: PASS" -} else { - puts " SIGNOFF: FAIL" -} -puts "================================================================" - -close_project -puts "Done." diff --git a/9_Firmware/9_2_FPGA/scripts/build18_production.tcl b/9_Firmware/9_2_FPGA/scripts/build18_production.tcl deleted file mode 100644 index 18b0486..0000000 --- a/9_Firmware/9_2_FPGA/scripts/build18_production.tcl +++ /dev/null @@ -1,470 +0,0 @@ -################################################################################ -# build18_production.tcl -# -# AERIS-10 Build 18: Post-Optimization Production Build -# Target: XC7A200T-2FBG484I -# Design: radar_system_top -# Tag: v0.1.1-build17 + FIR DSP48 pipelining + matched filter BRAM migration -# -# Changes vs Build 17: -# - FIR DSP48 BREG+MREG pipelining (fixes 68 DPIP-1 + 35 DPOP-2 warnings) -# - Matched filter input buffer migrated from register arrays to BRAM -# (~33K FF savings expected, +2 BRAM18 used) -# - Fixed: report_exceptions Vivado 2025.2 syntax (catch block) -# -# Generates ALL reports required for the 15-point Vivado TCL Build Report -# Analysis Checklist: -# 1. Run Status (synth/opt/place/route completion) -# 2. Timing Summary (WNS/TNS/WHS) -# 3. Clock Analysis (report_clocks) -# 4. Utilization Report (LUT/FF/BRAM/DSP) -# 5. Power Report (dynamic/static/thermal) -# 6. DRC (Design Rule Check) -# 7. IO and Constraints (report_io, unconstrained ports) -# 8. Congestion Analysis (report_design_analysis -congestion) -# 9. Route Status (unrouted nets) -# 10. Critical Paths (report_timing -max_paths 20) -# 11. QoR Summary (report_qor_summary) -# 12. CDC Analysis -# 13. Log File Scan (captured in build log) -# 14. Bitstream Generation (write_bitstream) -# 15. Final Signoff Criteria (all above combined) -# -# Usage: -# vivado -mode batch -source build18_production.tcl \ -# -log build/build18.log \ -# -journal build/build18.jou -# -# Author: auto-generated for Jason Stone -# Date: 2026-03-19 -################################################################################ - -# ============================================================================== -# 0. Configuration -# ============================================================================== - -set project_name "aeris10_radar" -set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] -set project_dir [file join $project_root "build"] -set rtl_dir $project_root -set top_module "radar_system_top" -set fpga_part "xc7a200tfbg484-2" -set report_dir "${project_dir}/reports_build18" -set sim_dir "${project_dir}/sim" -set bitstream_dir "${project_dir}/bitstream" -set build_tag "build18" - -file mkdir $report_dir -file mkdir $sim_dir -file mkdir $bitstream_dir - -# Record start time -set build_start [clock seconds] -set build_timestamp [clock format $build_start -format {%Y-%m-%d %H:%M:%S}] - -puts "================================================================" -puts " AERIS-10 Build 18: Post-Optimization Production Build" -puts " Target: $fpga_part" -puts " Top: $top_module" -puts " Reports: $report_dir" -puts " Started: $build_timestamp" -puts "================================================================" - -# ============================================================================== -# 1. Project Creation + Source Files -# ============================================================================== - -create_project $project_name $project_dir -part $fpga_part -force -set_property target_language Verilog [current_project] - -# --- Add RTL sources --- -set rtl_files [list \ - "${rtl_dir}/ad9484_interface_400m.v" \ - "${rtl_dir}/cdc_modules.v" \ - "${rtl_dir}/chirp_memory_loader_param.v" \ - "${rtl_dir}/cic_decimator_4x_enhanced.v" \ - "${rtl_dir}/dac_interface_single.v" \ - "${rtl_dir}/ddc_400m.v" \ - "${rtl_dir}/ddc_input_interface.v" \ - "${rtl_dir}/doppler_processor.v" \ - "${rtl_dir}/edge_detector.v" \ - "${rtl_dir}/fir_lowpass.v" \ - "${rtl_dir}/frequency_matched_filter.v" \ - "${rtl_dir}/latency_buffer.v" \ - "${rtl_dir}/matched_filter_multi_segment.v" \ - "${rtl_dir}/matched_filter_processing_chain.v" \ - "${rtl_dir}/nco_400m_enhanced.v" \ - "${rtl_dir}/plfm_chirp_controller.v" \ - "${rtl_dir}/radar_mode_controller.v" \ - "${rtl_dir}/radar_receiver_final.v" \ - "${rtl_dir}/radar_system_top.v" \ - "${rtl_dir}/radar_transmitter.v" \ - "${rtl_dir}/range_bin_decimator.v" \ - "${rtl_dir}/rx_gain_control.v" \ - "${rtl_dir}/mti_canceller.v" \ - "${rtl_dir}/cfar_ca.v" \ - "${rtl_dir}/fpga_self_test.v" \ - "${rtl_dir}/usb_data_interface.v" \ - "${rtl_dir}/xfft_16.v" \ - "${rtl_dir}/fft_engine.v" \ - "${rtl_dir}/adc_clk_mmcm.v" \ -] - -set file_count 0 -foreach f $rtl_files { - if {[file exists $f]} { - add_files -norecurse $f - incr file_count - } else { - puts " WARNING: RTL file not found: $f" - } -} -puts " Added $file_count RTL files" - -# Add .mem files for BRAM initialization -set mem_files [glob -nocomplain "${rtl_dir}/*.mem"] -foreach f $mem_files { - add_files -norecurse $f - puts " Added MEM: [file tail $f]" -} - -# Add constraints -add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"] -set_property top $top_module [current_fileset] -set_property verilog_define {FFT_XPM_BRAM} [current_fileset] - -# ============================================================================== -# 2. Synthesis -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 1/5: Synthesis" -puts "================================================================" - -set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY rebuilt [get_runs synth_1] -set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_1] - -set synth_start [clock seconds] -launch_runs synth_1 -jobs 8 -wait_on_run synth_1 -set synth_elapsed [expr {[clock seconds] - $synth_start}] - -set synth_status [get_property STATUS [get_runs synth_1]] -puts " Synthesis status: $synth_status" -puts " Synthesis time: ${synth_elapsed}s ([expr {$synth_elapsed/60}]m [expr {$synth_elapsed%60}]s)" - -if {[string match "*ERROR*" $synth_status] || [string match "*FAILED*" $synth_status]} { - puts "CRITICAL: SYNTHESIS FAILED — aborting build" - close_project - exit 1 -} - -# Post-synth timing (for comparison) -open_run synth_1 -name synth_1 -report_timing_summary -delay_type min_max -max_paths 10 -file "${report_dir}/01_timing_post_synth.rpt" -report_utilization -file "${report_dir}/01_utilization_post_synth.rpt" -close_design - -# ============================================================================== -# 3. Implementation (opt → place → phys_opt → route → post_route_phys_opt) -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 2/5: Implementation" -puts "================================================================" - -# Aggressive directives for best timing -set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1] -set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE ExtraTimingOpt [get_runs impl_1] -set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] -set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] -set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] -set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] -set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] - -set impl_start [clock seconds] -launch_runs impl_1 -jobs 8 -wait_on_run impl_1 -set impl_elapsed [expr {[clock seconds] - $impl_start}] - -set impl_status [get_property STATUS [get_runs impl_1]] -puts " Implementation status: $impl_status" -puts " Implementation time: ${impl_elapsed}s ([expr {$impl_elapsed/60}]m [expr {$impl_elapsed%60}]s)" - -if {![string match "*Complete*" $impl_status] && ![string match "*write_bitstream*" $impl_status]} { - puts "CRITICAL: IMPLEMENTATION FAILED: $impl_status" - close_project - exit 1 -} - -# ============================================================================== -# 4. Bitstream Generation -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 3/5: Bitstream Generation" -puts "================================================================" - -set bit_start [clock seconds] -# Handle case where Vivado auto-proceeds to write_bitstream after impl -if {[catch {launch_runs impl_1 -to_step write_bitstream -jobs 8} launch_err]} { - puts " Note: write_bitstream may already be in progress: $launch_err" -} -wait_on_run impl_1 -set bit_elapsed [expr {[clock seconds] - $bit_start}] -puts " Bitstream time: ${bit_elapsed}s" - -# Copy bitstream to known location -set bit_src "${project_dir}/aeris10_radar.runs/impl_1/${top_module}.bit" -if {[file exists $bit_src]} { - file copy -force $bit_src "${bitstream_dir}/${top_module}_${build_tag}.bit" - puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit" - puts " Size: [file size $bit_src] bytes" -} else { - puts " WARNING: Bitstream file not found at $bit_src" -} - -# ============================================================================== -# 5. Comprehensive Report Generation -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 4/5: Report Generation (15-point checklist)" -puts "================================================================" - -# Open the routed design for reporting -open_run impl_1 -name impl_1 - -# --- Checklist Item 2: Timing Summary --- -puts " [2/15] Timing Summary..." -report_timing_summary -delay_type min_max -max_paths 100 \ - -report_unconstrained \ - -file "${report_dir}/02_timing_summary.rpt" - -# --- Checklist Item 3: Clock Analysis --- -puts " [3/15] Clock Analysis..." -report_clocks -file "${report_dir}/03_clocks.rpt" -report_clock_interaction -delay_type min_max \ - -file "${report_dir}/03_clock_interaction.rpt" -report_clock_networks -file "${report_dir}/03_clock_networks.rpt" - -# --- Checklist Item 4: Utilization --- -puts " [4/15] Utilization..." -report_utilization -file "${report_dir}/04_utilization.rpt" -report_utilization -hierarchical -file "${report_dir}/04_utilization_hierarchical.rpt" - -# --- Checklist Item 5: Power --- -puts " [5/15] Power Report..." -report_power -file "${report_dir}/05_power.rpt" - -# --- Checklist Item 6: DRC --- -puts " [6/15] DRC..." -report_drc -file "${report_dir}/06_drc.rpt" - -# --- Checklist Item 7: IO and Constraints --- -puts " [7/15] IO Report..." -report_io -file "${report_dir}/07_io.rpt" -report_timing -from [all_inputs] -to [all_outputs] -max_paths 20 \ - -file "${report_dir}/07_io_timing.rpt" - -# --- Checklist Item 8: Congestion Analysis --- -puts " [8/15] Congestion Analysis..." -report_design_analysis -congestion -file "${report_dir}/08_congestion.rpt" - -# --- Checklist Item 9: Route Status --- -puts " [9/15] Route Status..." -report_route_status -file "${report_dir}/09_route_status.rpt" - -# --- Checklist Item 10: Critical Paths --- -puts " [10/15] Critical Paths..." -report_timing -max_paths 20 -sort_by slack -nworst 5 \ - -file "${report_dir}/10_critical_paths_setup.rpt" -report_timing -delay_type min -max_paths 20 -sort_by slack -nworst 5 \ - -file "${report_dir}/10_critical_paths_hold.rpt" -report_high_fanout_nets -timing -load_type -max_nets 20 \ - -file "${report_dir}/10_high_fanout_nets.rpt" - -# --- Checklist Item 11: QoR Summary --- -puts " [11/15] QoR Summary..." -report_design_analysis -timing -file "${report_dir}/11_design_analysis_timing.rpt" -report_design_analysis -logic_level_distribution -file "${report_dir}/11_logic_level_dist.rpt" -report_methodology -file "${report_dir}/11_methodology.rpt" - -# --- Checklist Item 12: CDC Analysis --- -puts " [12/15] CDC Analysis..." -report_cdc -details -file "${report_dir}/12_cdc.rpt" - -# --- Checklist Item 13: Log Scan (captured separately in build log) --- -puts " [13/15] Log scan — see build18.log" - -# --- Additional reports --- -puts " \[extra\] Generating additional diagnostic reports..." - -# Check_timing for completeness -# report_exceptions can fail in Vivado 2025.2 — wrap in catch -if {[catch {report_exceptions -file "${report_dir}/13_exceptions.rpt"} err]} { - puts " WARNING: report_exceptions failed: $err" - puts " (Known Vivado 2025.2 issue — non-critical)" -} -check_timing -verbose -file "${report_dir}/13_check_timing.rpt" - -# Compile configuration summary into a single text file -set summary_fh [open "${report_dir}/00_build18_summary.txt" w] -puts $summary_fh "================================================================" -puts $summary_fh " AERIS-10 Build 18 — Post-Optimization Production Build Summary" -puts $summary_fh "================================================================" -puts $summary_fh "" -puts $summary_fh "Build Tag: $build_tag" -puts $summary_fh "Build Timestamp: $build_timestamp" -puts $summary_fh "FPGA Part: $fpga_part" -puts $summary_fh "Top Module: $top_module" -puts $summary_fh "RTL Files: $file_count" -puts $summary_fh "Synth Status: $synth_status" -puts $summary_fh "Synth Time: ${synth_elapsed}s" -puts $summary_fh "Impl Status: $impl_status" -puts $summary_fh "Impl Time: ${impl_elapsed}s" -puts $summary_fh "Bitstream Time: ${bit_elapsed}s" -puts $summary_fh "" - -# Extract key timing numbers — use catch to handle empty STATS properties -# (Vivado 2025.2 may return empty strings after write_bitstream auto-launch) -puts $summary_fh "--- Timing ---" -if {[catch {set wns [get_property STATS.WNS [current_design]]}] || $wns eq ""} { set wns "N/A" } -if {[catch {set tns [get_property STATS.TNS [current_design]]}] || $tns eq ""} { set tns "N/A" } -if {[catch {set whs [get_property STATS.WHS [current_design]]}] || $whs eq ""} { set whs "N/A" } -if {[catch {set ths [get_property STATS.THS [current_design]]}] || $ths eq ""} { set ths "N/A" } -if {[catch {set fail_ep [get_property STATS.TPWS [current_design]]}] || $fail_ep eq ""} { set fail_ep "N/A" } -puts $summary_fh " WNS: $wns ns" -puts $summary_fh " TNS: $tns ns" -puts $summary_fh " WHS: $whs ns" -puts $summary_fh " THS: $ths ns" -puts $summary_fh "" - -# Extract utilization -puts $summary_fh "--- Utilization ---" -set lut_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.LUT.*}]] -set ff_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.FF.*}]] -set bram_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ BMEM.*}]] -set dsp_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ MULT.DSP.*}]] -puts $summary_fh " LUTs: $lut_used / 134600" -puts $summary_fh " FFs: $ff_used / 269200" -puts $summary_fh " BRAM: $bram_used cells" -puts $summary_fh " DSP: $dsp_used cells" -puts $summary_fh "" - -# Route status -set unrouted [llength [get_nets -hierarchical -filter {ROUTE_STATUS == UNROUTED}]] -puts $summary_fh "--- Route ---" -puts $summary_fh " Unrouted nets: $unrouted" -puts $summary_fh "" - -# Bitstream -if {[file exists $bit_src]} { - puts $summary_fh "--- Bitstream ---" - puts $summary_fh " File: ${top_module}_${build_tag}.bit" - puts $summary_fh " Size: [file size $bit_src] bytes" -} else { - puts $summary_fh "--- Bitstream ---" - puts $summary_fh " WARNING: NOT GENERATED" -} -puts $summary_fh "" - -# Signoff -puts $summary_fh "--- Final Signoff ---" -set signoff_pass 1 -if {![string is double -strict $wns]} { - puts $summary_fh " WARN: WNS = N/A (timing stats unavailable — check reports)" -} elseif {$wns < 0} { - puts $summary_fh " FAIL: WNS = $wns (negative slack)" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: WNS = $wns ns (no setup violations)" -} -if {![string is double -strict $whs]} { - puts $summary_fh " WARN: WHS = N/A (timing stats unavailable — check reports)" -} elseif {$whs < 0} { - puts $summary_fh " FAIL: WHS = $whs (hold violation)" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: WHS = $whs ns (no hold violations)" -} -if {![string is double -strict $tns]} { - puts $summary_fh " WARN: TNS = N/A (timing stats unavailable — check reports)" -} elseif {$tns != 0} { - puts $summary_fh " FAIL: TNS = $tns (total negative slack)" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: TNS = 0 ns" -} -if {$unrouted > 0} { - puts $summary_fh " FAIL: $unrouted unrouted nets" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: All nets routed" -} -if {[file exists $bit_src]} { - puts $summary_fh " PASS: Bitstream generated" -} else { - puts $summary_fh " FAIL: No bitstream" - set signoff_pass 0 -} -puts $summary_fh "" -if {$signoff_pass} { - puts $summary_fh " *** SIGNOFF: PASS ***" -} else { - puts $summary_fh " *** SIGNOFF: FAIL ***" -} - -close $summary_fh -puts " Summary written to: ${report_dir}/00_build18_summary.txt" - -# ============================================================================== -# 6. SDF + Timing Netlist (for post-route simulation) -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 5/5: SDF + Timing Netlist" -puts "================================================================" - -write_verilog -force -mode timesim "${sim_dir}/post_impl_timesim.v" -write_sdf -force "${sim_dir}/post_impl_timesim.sdf" - -close_design -open_run synth_1 -name synth_1 -write_verilog -force -mode funcsim "${sim_dir}/post_synth_funcsim.v" - -# ============================================================================== -# Done -# ============================================================================== - -set build_total [expr {[clock seconds] - $build_start}] -set build_end [clock format [clock seconds] -format {%Y-%m-%d %H:%M:%S}] - -puts "" -puts "================================================================" -puts " BUILD 18 COMPLETE" -puts "================================================================" -puts " Started: $build_timestamp" -puts " Finished: $build_end" -puts " Total time: ${build_total}s ([expr {$build_total/60}]m [expr {$build_total%60}]s)" -puts " Synth: ${synth_elapsed}s" -puts " Impl: ${impl_elapsed}s" -puts " Bitstream: ${bit_elapsed}s" -puts " Reports: $report_dir" -puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit" -puts " WNS: $wns ns | WHS: $whs ns | TNS: $tns ns" -if {$signoff_pass} { - puts " SIGNOFF: PASS" -} else { - puts " SIGNOFF: FAIL" -} -puts "================================================================" - -close_project -puts "Done." diff --git a/9_Firmware/9_2_FPGA/scripts/build19_mmcm.tcl b/9_Firmware/9_2_FPGA/scripts/build19_mmcm.tcl deleted file mode 100644 index e23350b..0000000 --- a/9_Firmware/9_2_FPGA/scripts/build19_mmcm.tcl +++ /dev/null @@ -1,493 +0,0 @@ -################################################################################ -# build19_mmcm.tcl -# -# AERIS-10 Build 19: MMCM Jitter-Cleaning on ADC 400 MHz Clock (Gap 7) -# Target: XC7A200T-2FBG484I -# Design: radar_system_top -# Tag: v0.1.2-build18 + adc_clk_mmcm jitter cleaning wrapper -# -# Changes vs Build 18: -# - NEW MODULE: adc_clk_mmcm.v — MMCME2_ADV jitter-cleaning wrapper -# - MODIFIED: ad9484_interface_400m.v — BUFG replaced with MMCM path, -# reset gated on mmcm_locked -# - NEW XDC: adc_clk_mmcm.xdc — generated clock rename, CDC false paths -# -# Expected impact: -# - WNS improvement: +20-40 ps (reduced clock uncertainty from jitter cleaning) -# - MMCME2 usage: 0 → 1 (of 10 available) -# - BUFG usage: 4 → 5 (of 32 available; feedback BUFG inside MMCM wrapper) -# -# Generates ALL reports required for the 15-point Vivado TCL Build Report. -# -# Usage: -# vivado -mode batch -source build19_mmcm.tcl \ -# -log build/build19.log \ -# -journal build/build19.jou -# -# Author: auto-generated for Jason Stone -# Date: 2026-03-19 -################################################################################ - -# ============================================================================== -# 0. Configuration -# ============================================================================== - -set project_name "aeris10_radar" -set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] -set project_dir [file join $project_root "build"] -set rtl_dir $project_root -set top_module "radar_system_top" -set fpga_part "xc7a200tfbg484-2" -set report_dir "${project_dir}/reports_build19" -set sim_dir "${project_dir}/sim" -set bitstream_dir "${project_dir}/bitstream" -set build_tag "build19" - -file mkdir $report_dir -file mkdir $sim_dir -file mkdir $bitstream_dir - -# Record start time -set build_start [clock seconds] -set build_timestamp [clock format $build_start -format {%Y-%m-%d %H:%M:%S}] - -puts "================================================================" -puts " AERIS-10 Build 19: MMCM Jitter-Cleaning (Gap 7)" -puts " Target: $fpga_part" -puts " Top: $top_module" -puts " Reports: $report_dir" -puts " Started: $build_timestamp" -puts "================================================================" - -# ============================================================================== -# 1. Project Creation + Source Files -# ============================================================================== - -create_project $project_name $project_dir -part $fpga_part -force -set_property target_language Verilog [current_project] - -# --- Add RTL sources --- -# NOTE: adc_clk_mmcm.v is NEW for Build 19 (Gap 7 MMCM wrapper) -set rtl_files [list \ - "${rtl_dir}/adc_clk_mmcm.v" \ - "${rtl_dir}/ad9484_interface_400m.v" \ - "${rtl_dir}/cdc_modules.v" \ - "${rtl_dir}/chirp_memory_loader_param.v" \ - "${rtl_dir}/cic_decimator_4x_enhanced.v" \ - "${rtl_dir}/dac_interface_single.v" \ - "${rtl_dir}/ddc_400m.v" \ - "${rtl_dir}/ddc_input_interface.v" \ - "${rtl_dir}/doppler_processor.v" \ - "${rtl_dir}/edge_detector.v" \ - "${rtl_dir}/fir_lowpass.v" \ - "${rtl_dir}/frequency_matched_filter.v" \ - "${rtl_dir}/latency_buffer.v" \ - "${rtl_dir}/matched_filter_multi_segment.v" \ - "${rtl_dir}/matched_filter_processing_chain.v" \ - "${rtl_dir}/nco_400m_enhanced.v" \ - "${rtl_dir}/plfm_chirp_controller.v" \ - "${rtl_dir}/radar_mode_controller.v" \ - "${rtl_dir}/radar_receiver_final.v" \ - "${rtl_dir}/radar_system_top.v" \ - "${rtl_dir}/radar_transmitter.v" \ - "${rtl_dir}/range_bin_decimator.v" \ - "${rtl_dir}/rx_gain_control.v" \ - "${rtl_dir}/mti_canceller.v" \ - "${rtl_dir}/cfar_ca.v" \ - "${rtl_dir}/fpga_self_test.v" \ - "${rtl_dir}/usb_data_interface.v" \ - "${rtl_dir}/xfft_16.v" \ - "${rtl_dir}/fft_engine.v" \ -] - -set file_count 0 -foreach f $rtl_files { - if {[file exists $f]} { - add_files -norecurse $f - incr file_count - } else { - puts " WARNING: RTL file not found: $f" - } -} -puts " Added $file_count RTL files" - -# Add .mem files for BRAM initialization -set mem_files [glob -nocomplain "${rtl_dir}/*.mem"] -foreach f $mem_files { - add_files -norecurse $f - puts " Added MEM: [file tail $f]" -} - -# Add constraints — main production XDC + MMCM supplementary XDC -add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"] -add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "adc_clk_mmcm.xdc"] - -set_property top $top_module [current_fileset] -set_property verilog_define {FFT_XPM_BRAM} [current_fileset] - -# ============================================================================== -# 2. Synthesis -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 1/5: Synthesis" -puts "================================================================" - -set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY rebuilt [get_runs synth_1] -set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_1] - -set synth_start [clock seconds] -launch_runs synth_1 -jobs 8 -wait_on_run synth_1 -set synth_elapsed [expr {[clock seconds] - $synth_start}] - -set synth_status [get_property STATUS [get_runs synth_1]] -puts " Synthesis status: $synth_status" -puts " Synthesis time: ${synth_elapsed}s ([expr {$synth_elapsed/60}]m [expr {$synth_elapsed%60}]s)" - -if {[string match "*ERROR*" $synth_status] || [string match "*FAILED*" $synth_status]} { - puts "CRITICAL: SYNTHESIS FAILED — aborting build" - close_project - exit 1 -} - -# Post-synth timing (for comparison) -open_run synth_1 -name synth_1 -report_timing_summary -delay_type min_max -max_paths 10 -file "${report_dir}/01_timing_post_synth.rpt" -report_utilization -file "${report_dir}/01_utilization_post_synth.rpt" -close_design - -# ============================================================================== -# 3. Implementation (opt → place → phys_opt → route → post_route_phys_opt) -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 2/5: Implementation" -puts "================================================================" - -# Aggressive directives for best timing -set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1] -set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE ExtraTimingOpt [get_runs impl_1] -set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] -set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] -set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] -set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] -set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] - -set impl_start [clock seconds] -launch_runs impl_1 -jobs 8 -wait_on_run impl_1 -set impl_elapsed [expr {[clock seconds] - $impl_start}] - -set impl_status [get_property STATUS [get_runs impl_1]] -puts " Implementation status: $impl_status" -puts " Implementation time: ${impl_elapsed}s ([expr {$impl_elapsed/60}]m [expr {$impl_elapsed%60}]s)" - -if {![string match "*Complete*" $impl_status] && ![string match "*write_bitstream*" $impl_status]} { - puts "CRITICAL: IMPLEMENTATION FAILED: $impl_status" - close_project - exit 1 -} - -# ============================================================================== -# 4. Bitstream Generation -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 3/5: Bitstream Generation" -puts "================================================================" - -set bit_start [clock seconds] -# Handle case where Vivado auto-proceeds to write_bitstream after impl -if {[catch {launch_runs impl_1 -to_step write_bitstream -jobs 8} launch_err]} { - puts " Note: write_bitstream may already be in progress: $launch_err" -} -wait_on_run impl_1 -set bit_elapsed [expr {[clock seconds] - $bit_start}] -puts " Bitstream time: ${bit_elapsed}s" - -# Copy bitstream to known location -set bit_src "${project_dir}/aeris10_radar.runs/impl_1/${top_module}.bit" -if {[file exists $bit_src]} { - file copy -force $bit_src "${bitstream_dir}/${top_module}_${build_tag}.bit" - puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit" - puts " Size: [file size $bit_src] bytes" -} else { - puts " WARNING: Bitstream file not found at $bit_src" -} - -# ============================================================================== -# 5. Comprehensive Report Generation -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 4/5: Report Generation (15-point checklist)" -puts "================================================================" - -# Open the routed design for reporting -open_run impl_1 -name impl_1 - -# --- Checklist Item 2: Timing Summary --- -puts " [2/15] Timing Summary..." -report_timing_summary -delay_type min_max -max_paths 100 \ - -report_unconstrained \ - -file "${report_dir}/02_timing_summary.rpt" - -# --- Checklist Item 3: Clock Analysis --- -puts " [3/15] Clock Analysis..." -report_clocks -file "${report_dir}/03_clocks.rpt" -report_clock_interaction -delay_type min_max \ - -file "${report_dir}/03_clock_interaction.rpt" -report_clock_networks -file "${report_dir}/03_clock_networks.rpt" - -# --- Checklist Item 4: Utilization --- -puts " [4/15] Utilization..." -report_utilization -file "${report_dir}/04_utilization.rpt" -report_utilization -hierarchical -file "${report_dir}/04_utilization_hierarchical.rpt" - -# --- Checklist Item 5: Power --- -puts " [5/15] Power Report..." -report_power -file "${report_dir}/05_power.rpt" - -# --- Checklist Item 6: DRC --- -puts " [6/15] DRC..." -report_drc -file "${report_dir}/06_drc.rpt" - -# --- Checklist Item 7: IO and Constraints --- -puts " [7/15] IO Report..." -report_io -file "${report_dir}/07_io.rpt" -report_timing -from [all_inputs] -to [all_outputs] -max_paths 20 \ - -file "${report_dir}/07_io_timing.rpt" - -# --- Checklist Item 8: Congestion Analysis --- -puts " [8/15] Congestion Analysis..." -report_design_analysis -congestion -file "${report_dir}/08_congestion.rpt" - -# --- Checklist Item 9: Route Status --- -puts " [9/15] Route Status..." -report_route_status -file "${report_dir}/09_route_status.rpt" - -# --- Checklist Item 10: Critical Paths --- -puts " [10/15] Critical Paths..." -report_timing -max_paths 20 -sort_by slack -nworst 5 \ - -file "${report_dir}/10_critical_paths_setup.rpt" -report_timing -delay_type min -max_paths 20 -sort_by slack -nworst 5 \ - -file "${report_dir}/10_critical_paths_hold.rpt" -report_high_fanout_nets -timing -load_type -max_nets 20 \ - -file "${report_dir}/10_high_fanout_nets.rpt" - -# --- Checklist Item 11: QoR Summary --- -puts " [11/15] QoR Summary..." -report_design_analysis -timing -file "${report_dir}/11_design_analysis_timing.rpt" -report_design_analysis -logic_level_distribution -file "${report_dir}/11_logic_level_dist.rpt" -report_methodology -file "${report_dir}/11_methodology.rpt" - -# --- Checklist Item 12: CDC Analysis --- -puts " [12/15] CDC Analysis..." -report_cdc -details -file "${report_dir}/12_cdc.rpt" - -# --- Checklist Item 13: Log Scan (captured separately in build log) --- -puts " [13/15] Log scan — see build19.log" - -# --- Additional reports --- -puts " \[extra\] Generating additional diagnostic reports..." - -# report_exceptions can fail in Vivado 2025.2 — wrap in catch -if {[catch {report_exceptions -file "${report_dir}/13_exceptions.rpt"} err]} { - puts " WARNING: report_exceptions failed: $err" - puts " (Known Vivado 2025.2 issue — non-critical)" -} -check_timing -verbose -file "${report_dir}/13_check_timing.rpt" - -# Compile configuration summary into a single text file -set summary_fh [open "${report_dir}/00_build19_summary.txt" w] -puts $summary_fh "================================================================" -puts $summary_fh " AERIS-10 Build 19 — MMCM Jitter-Cleaning (Gap 7) Summary" -puts $summary_fh "================================================================" -puts $summary_fh "" -puts $summary_fh "Build Tag: $build_tag" -puts $summary_fh "Build Timestamp: $build_timestamp" -puts $summary_fh "FPGA Part: $fpga_part" -puts $summary_fh "Top Module: $top_module" -puts $summary_fh "RTL Files: $file_count" -puts $summary_fh "Synth Status: $synth_status" -puts $summary_fh "Synth Time: ${synth_elapsed}s" -puts $summary_fh "Impl Status: $impl_status" -puts $summary_fh "Impl Time: ${impl_elapsed}s" -puts $summary_fh "Bitstream Time: ${bit_elapsed}s" -puts $summary_fh "" - -# Extract key timing numbers — use catch to handle empty STATS properties -# (Vivado 2025.2 may return empty strings after write_bitstream auto-launch) -puts $summary_fh "--- Timing ---" -if {[catch {set wns [get_property STATS.WNS [current_design]]}] || $wns eq ""} { set wns "N/A" } -if {[catch {set tns [get_property STATS.TNS [current_design]]}] || $tns eq ""} { set tns "N/A" } -if {[catch {set whs [get_property STATS.WHS [current_design]]}] || $whs eq ""} { set whs "N/A" } -if {[catch {set ths [get_property STATS.THS [current_design]]}] || $ths eq ""} { set ths "N/A" } -if {[catch {set fail_ep [get_property STATS.TPWS [current_design]]}] || $fail_ep eq ""} { set fail_ep "N/A" } -puts $summary_fh " WNS: $wns ns" -puts $summary_fh " TNS: $tns ns" -puts $summary_fh " WHS: $whs ns" -puts $summary_fh " THS: $ths ns" -puts $summary_fh "" -puts $summary_fh " Build 18 Baseline: WNS = +0.062 ns, WHS = +0.059 ns" -if {[string is double -strict $wns]} { - puts $summary_fh " Delta WNS: [expr {$wns - 0.062}] ns" -} else { - puts $summary_fh " Delta WNS: N/A (timing stats unavailable)" -} -if {[string is double -strict $whs]} { - puts $summary_fh " Delta WHS: [expr {$whs - 0.059}] ns" -} else { - puts $summary_fh " Delta WHS: N/A (timing stats unavailable)" -} -puts $summary_fh "" - -# Extract utilization -puts $summary_fh "--- Utilization ---" -set lut_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.LUT.*}]] -set ff_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.FF.*}]] -set bram_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ BMEM.*}]] -set dsp_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ MULT.DSP.*}]] -puts $summary_fh " LUTs: $lut_used / 134600" -puts $summary_fh " FFs: $ff_used / 269200" -puts $summary_fh " BRAM: $bram_used cells" -puts $summary_fh " DSP: $dsp_used cells" -puts $summary_fh "" -puts $summary_fh " Build 18 Baseline: LUTs=6088, FFs=8946, BRAM=16, DSP=140" -puts $summary_fh "" - -# Route status -set unrouted [llength [get_nets -hierarchical -filter {ROUTE_STATUS == UNROUTED}]] -puts $summary_fh "--- Route ---" -puts $summary_fh " Unrouted nets: $unrouted" -puts $summary_fh "" - -# MMCM usage (new for Build 19) -puts $summary_fh "--- MMCM Usage (Gap 7) ---" -set mmcm_count [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLOCK.MMCM.*}]] -puts $summary_fh " MMCME2 used: $mmcm_count / 10" -puts $summary_fh " Expected: 1 (adc_clk_mmcm jitter cleaner)" -puts $summary_fh "" - -# Bitstream -if {[file exists $bit_src]} { - puts $summary_fh "--- Bitstream ---" - puts $summary_fh " File: ${top_module}_${build_tag}.bit" - puts $summary_fh " Size: [file size $bit_src] bytes" -} else { - puts $summary_fh "--- Bitstream ---" - puts $summary_fh " WARNING: NOT GENERATED" -} -puts $summary_fh "" - -# Signoff -puts $summary_fh "--- Final Signoff ---" -set signoff_pass 1 -if {![string is double -strict $wns]} { - puts $summary_fh " WARN: WNS = N/A (timing stats unavailable — check reports)" -} elseif {$wns < 0} { - puts $summary_fh " FAIL: WNS = $wns (negative slack)" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: WNS = $wns ns (no setup violations)" -} -if {![string is double -strict $whs]} { - puts $summary_fh " WARN: WHS = N/A (timing stats unavailable — check reports)" -} elseif {$whs < 0} { - puts $summary_fh " FAIL: WHS = $whs (hold violation)" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: WHS = $whs ns (no hold violations)" -} -if {![string is double -strict $tns]} { - puts $summary_fh " WARN: TNS = N/A (timing stats unavailable — check reports)" -} elseif {$tns != 0} { - puts $summary_fh " FAIL: TNS = $tns (total negative slack)" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: TNS = 0 ns" -} -if {$unrouted > 0} { - puts $summary_fh " FAIL: $unrouted unrouted nets" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: All nets routed" -} -if {[file exists $bit_src]} { - puts $summary_fh " PASS: Bitstream generated" -} else { - puts $summary_fh " FAIL: No bitstream" - set signoff_pass 0 -} -puts $summary_fh "" - -# Timing regression check vs Build 18 -if {[string is double -strict $wns] && $wns < 0.062} { - puts $summary_fh " *** WARNING: WNS REGRESSED vs Build 18 (was +0.062 ns, now $wns ns) ***" - puts $summary_fh " *** Consider reverting MMCM changes per revert-safety policy ***" -} -if {[string is double -strict $whs] && $whs < 0.059} { - puts $summary_fh " *** WARNING: WHS REGRESSED vs Build 18 (was +0.059 ns, now $whs ns) ***" -} - -if {$signoff_pass} { - puts $summary_fh " *** SIGNOFF: PASS ***" -} else { - puts $summary_fh " *** SIGNOFF: FAIL ***" -} - -close $summary_fh -puts " Summary written to: ${report_dir}/00_build19_summary.txt" - -# ============================================================================== -# 6. SDF + Timing Netlist (for post-route simulation) -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 5/5: SDF + Timing Netlist" -puts "================================================================" - -write_verilog -force -mode timesim "${sim_dir}/post_impl_timesim.v" -write_sdf -force "${sim_dir}/post_impl_timesim.sdf" - -close_design -open_run synth_1 -name synth_1 -write_verilog -force -mode funcsim "${sim_dir}/post_synth_funcsim.v" - -# ============================================================================== -# Done -# ============================================================================== - -set build_total [expr {[clock seconds] - $build_start}] -set build_end [clock format [clock seconds] -format {%Y-%m-%d %H:%M:%S}] - -puts "" -puts "================================================================" -puts " BUILD 19 COMPLETE" -puts "================================================================" -puts " Started: $build_timestamp" -puts " Finished: $build_end" -puts " Total time: ${build_total}s ([expr {$build_total/60}]m [expr {$build_total%60}]s)" -puts " Synth: ${synth_elapsed}s" -puts " Impl: ${impl_elapsed}s" -puts " Bitstream: ${bit_elapsed}s" -puts " Reports: $report_dir" -puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit" -puts " WNS: $wns ns | WHS: $whs ns | TNS: $tns ns" -puts " Build 18 baseline: WNS +0.062 | WHS +0.059" -if {$signoff_pass} { - puts " SIGNOFF: PASS" -} else { - puts " SIGNOFF: FAIL" -} -puts "================================================================" - -close_project -puts "Done." diff --git a/9_Firmware/9_2_FPGA/scripts/build20_mmcm_creg.tcl b/9_Firmware/9_2_FPGA/scripts/build20_mmcm_creg.tcl deleted file mode 100644 index 8b34da7..0000000 --- a/9_Firmware/9_2_FPGA/scripts/build20_mmcm_creg.tcl +++ /dev/null @@ -1,501 +0,0 @@ -################################################################################ -# build20_mmcm_creg.tcl -# -# AERIS-10 Build 20: MMCM XDC Clock-Name Fix + CIC Comb CREG Pipeline -# Target: XC7A200T-2FBG484I -# Design: radar_system_top -# Tag: v0.1.2-build18 + MMCM (Gap 7) + XDC fix + CIC CREG -# -# Changes vs Build 19: -# - FIX: adc_clk_mmcm.xdc — removed conflicting create_generated_clock -# (clk_400m_mmcm), replaced all references with Vivado auto-generated -# clk_mmcm_out0. This fixes the CDC false path that wasn't applying -# to the actual clk_mmcm_out0→clk_100m crossing (Build 19 WNS -0.011). -# - NEW: cic_decimator_4x_enhanced.v — explicit DSP48E1 for comb[0] with -# CREG=1/AREG=1/BREG=1/PREG=1. Absorbs the integrator_sampled_comb -# fabric register into DSP48 C-port pipeline, eliminating 0.643 ns -# fabric→DSP route delay (Build 18 tightest path, WNS +0.062). -# -# Expected impact: -# - WNS: should be >> +0.062 ns (CREG eliminates Build 18 critical path, -# XDC fix properly applies CDC false path) -# - DSP48E1: 140 → 142 (+2: one per CIC I/Q channel for comb_0_dsp) -# - LUT/FF: ~same (CREG replaces fabric FDREs with DSP internal registers) -# -# Generates ALL reports required for the 15-point Vivado TCL Build Report. -# -# Usage: -# vivado -mode batch -source build20_mmcm_creg.tcl \ -# -log build/build20.log \ -# -journal build/build20.jou -# -# Author: auto-generated for Jason Stone -# Date: 2026-03-19 -################################################################################ - -# ============================================================================== -# 0. Configuration -# ============================================================================== - -set project_name "aeris10_radar" -set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] -set project_dir [file join $project_root "build"] -set rtl_dir $project_root -set top_module "radar_system_top" -set fpga_part "xc7a200tfbg484-2" -set report_dir "${project_dir}/reports_build20" -set sim_dir "${project_dir}/sim" -set bitstream_dir "${project_dir}/bitstream" -set build_tag "build20" - -file mkdir $report_dir -file mkdir $sim_dir -file mkdir $bitstream_dir - -# Record start time -set build_start [clock seconds] -set build_timestamp [clock format $build_start -format {%Y-%m-%d %H:%M:%S}] - -puts "================================================================" -puts " AERIS-10 Build 20: MMCM XDC Fix + CIC CREG Pipeline" -puts " Target: $fpga_part" -puts " Top: $top_module" -puts " Reports: $report_dir" -puts " Started: $build_timestamp" -puts "================================================================" - -# ============================================================================== -# 1. Project Creation + Source Files -# ============================================================================== - -create_project $project_name $project_dir -part $fpga_part -force -set_property target_language Verilog [current_project] - -# --- Add RTL sources --- -set rtl_files [list \ - "${rtl_dir}/adc_clk_mmcm.v" \ - "${rtl_dir}/ad9484_interface_400m.v" \ - "${rtl_dir}/cdc_modules.v" \ - "${rtl_dir}/chirp_memory_loader_param.v" \ - "${rtl_dir}/cic_decimator_4x_enhanced.v" \ - "${rtl_dir}/dac_interface_single.v" \ - "${rtl_dir}/ddc_400m.v" \ - "${rtl_dir}/ddc_input_interface.v" \ - "${rtl_dir}/doppler_processor.v" \ - "${rtl_dir}/edge_detector.v" \ - "${rtl_dir}/fir_lowpass.v" \ - "${rtl_dir}/frequency_matched_filter.v" \ - "${rtl_dir}/latency_buffer.v" \ - "${rtl_dir}/matched_filter_multi_segment.v" \ - "${rtl_dir}/matched_filter_processing_chain.v" \ - "${rtl_dir}/nco_400m_enhanced.v" \ - "${rtl_dir}/plfm_chirp_controller.v" \ - "${rtl_dir}/radar_mode_controller.v" \ - "${rtl_dir}/radar_receiver_final.v" \ - "${rtl_dir}/radar_system_top.v" \ - "${rtl_dir}/radar_transmitter.v" \ - "${rtl_dir}/range_bin_decimator.v" \ - "${rtl_dir}/rx_gain_control.v" \ - "${rtl_dir}/mti_canceller.v" \ - "${rtl_dir}/cfar_ca.v" \ - "${rtl_dir}/fpga_self_test.v" \ - "${rtl_dir}/usb_data_interface.v" \ - "${rtl_dir}/xfft_16.v" \ - "${rtl_dir}/fft_engine.v" \ -] - -set file_count 0 -foreach f $rtl_files { - if {[file exists $f]} { - add_files -norecurse $f - incr file_count - } else { - puts " WARNING: RTL file not found: $f" - } -} -puts " Added $file_count RTL files" - -# Add .mem files for BRAM initialization -set mem_files [glob -nocomplain "${rtl_dir}/*.mem"] -foreach f $mem_files { - add_files -norecurse $f - puts " Added MEM: [file tail $f]" -} - -# Add constraints — main production XDC + MMCM supplementary XDC (FIXED) -add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"] -add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "adc_clk_mmcm.xdc"] - -set_property top $top_module [current_fileset] -set_property verilog_define {FFT_XPM_BRAM} [current_fileset] - -# ============================================================================== -# 2. Synthesis -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 1/5: Synthesis" -puts "================================================================" - -set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY rebuilt [get_runs synth_1] -set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_1] - -set synth_start [clock seconds] -launch_runs synth_1 -jobs 8 -wait_on_run synth_1 -set synth_elapsed [expr {[clock seconds] - $synth_start}] - -set synth_status [get_property STATUS [get_runs synth_1]] -puts " Synthesis status: $synth_status" -puts " Synthesis time: ${synth_elapsed}s ([expr {$synth_elapsed/60}]m [expr {$synth_elapsed%60}]s)" - -if {[string match "*ERROR*" $synth_status] || [string match "*FAILED*" $synth_status]} { - puts "CRITICAL: SYNTHESIS FAILED — aborting build" - close_project - exit 1 -} - -# Post-synth timing (for comparison) -open_run synth_1 -name synth_1 -report_timing_summary -delay_type min_max -max_paths 10 -file "${report_dir}/01_timing_post_synth.rpt" -report_utilization -file "${report_dir}/01_utilization_post_synth.rpt" -close_design - -# ============================================================================== -# 3. Implementation (opt → place → phys_opt → route → post_route_phys_opt) -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 2/5: Implementation" -puts "================================================================" - -# Aggressive directives for best timing -set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1] -set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE ExtraTimingOpt [get_runs impl_1] -set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] -set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] -set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] -set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] -set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1] - -set impl_start [clock seconds] -launch_runs impl_1 -jobs 8 -wait_on_run impl_1 -set impl_elapsed [expr {[clock seconds] - $impl_start}] - -set impl_status [get_property STATUS [get_runs impl_1]] -puts " Implementation status: $impl_status" -puts " Implementation time: ${impl_elapsed}s ([expr {$impl_elapsed/60}]m [expr {$impl_elapsed%60}]s)" - -if {![string match "*Complete*" $impl_status] && ![string match "*write_bitstream*" $impl_status]} { - puts "CRITICAL: IMPLEMENTATION FAILED: $impl_status" - close_project - exit 1 -} - -# ============================================================================== -# 4. Bitstream Generation -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 3/5: Bitstream Generation" -puts "================================================================" - -set bit_start [clock seconds] -# Handle case where Vivado auto-proceeds to write_bitstream after impl -if {[catch {launch_runs impl_1 -to_step write_bitstream -jobs 8} launch_err]} { - puts " Note: write_bitstream may already be in progress: $launch_err" -} -wait_on_run impl_1 -set bit_elapsed [expr {[clock seconds] - $bit_start}] -puts " Bitstream time: ${bit_elapsed}s" - -# Copy bitstream to known location -set bit_src "${project_dir}/aeris10_radar.runs/impl_1/${top_module}.bit" -if {[file exists $bit_src]} { - file copy -force $bit_src "${bitstream_dir}/${top_module}_${build_tag}.bit" - puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit" - puts " Size: [file size $bit_src] bytes" -} else { - puts " WARNING: Bitstream file not found at $bit_src" -} - -# ============================================================================== -# 5. Comprehensive Report Generation -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 4/5: Report Generation (15-point checklist)" -puts "================================================================" - -# Open the routed design for reporting -open_run impl_1 -name impl_1 - -# --- Checklist Item 2: Timing Summary --- -puts " [2/15] Timing Summary..." -report_timing_summary -delay_type min_max -max_paths 100 \ - -report_unconstrained \ - -file "${report_dir}/02_timing_summary.rpt" - -# --- Checklist Item 3: Clock Analysis --- -puts " [3/15] Clock Analysis..." -report_clocks -file "${report_dir}/03_clocks.rpt" -report_clock_interaction -delay_type min_max \ - -file "${report_dir}/03_clock_interaction.rpt" -report_clock_networks -file "${report_dir}/03_clock_networks.rpt" - -# --- Checklist Item 4: Utilization --- -puts " [4/15] Utilization..." -report_utilization -file "${report_dir}/04_utilization.rpt" -report_utilization -hierarchical -file "${report_dir}/04_utilization_hierarchical.rpt" - -# --- Checklist Item 5: Power --- -puts " [5/15] Power Report..." -report_power -file "${report_dir}/05_power.rpt" - -# --- Checklist Item 6: DRC --- -puts " [6/15] DRC..." -report_drc -file "${report_dir}/06_drc.rpt" - -# --- Checklist Item 7: IO and Constraints --- -puts " [7/15] IO Report..." -report_io -file "${report_dir}/07_io.rpt" -report_timing -from [all_inputs] -to [all_outputs] -max_paths 20 \ - -file "${report_dir}/07_io_timing.rpt" - -# --- Checklist Item 8: Congestion Analysis --- -puts " [8/15] Congestion Analysis..." -report_design_analysis -congestion -file "${report_dir}/08_congestion.rpt" - -# --- Checklist Item 9: Route Status --- -puts " [9/15] Route Status..." -report_route_status -file "${report_dir}/09_route_status.rpt" - -# --- Checklist Item 10: Critical Paths --- -puts " [10/15] Critical Paths..." -report_timing -max_paths 20 -sort_by slack -nworst 5 \ - -file "${report_dir}/10_critical_paths_setup.rpt" -report_timing -delay_type min -max_paths 20 -sort_by slack -nworst 5 \ - -file "${report_dir}/10_critical_paths_hold.rpt" -report_high_fanout_nets -timing -load_type -max_nets 20 \ - -file "${report_dir}/10_high_fanout_nets.rpt" - -# --- Checklist Item 11: QoR Summary --- -puts " [11/15] QoR Summary..." -report_design_analysis -timing -file "${report_dir}/11_design_analysis_timing.rpt" -report_design_analysis -logic_level_distribution -file "${report_dir}/11_logic_level_dist.rpt" -report_methodology -file "${report_dir}/11_methodology.rpt" - -# --- Checklist Item 12: CDC Analysis --- -puts " [12/15] CDC Analysis..." -report_cdc -details -file "${report_dir}/12_cdc.rpt" - -# --- Checklist Item 13: Log Scan (captured separately in build log) --- -puts " [13/15] Log scan — see build20.log" - -# --- Additional reports --- -puts " \[extra\] Generating additional diagnostic reports..." - -# report_exceptions can fail in Vivado 2025.2 — wrap in catch -if {[catch {report_exceptions -file "${report_dir}/13_exceptions.rpt"} err]} { - puts " WARNING: report_exceptions failed: $err" - puts " (Known Vivado 2025.2 issue — non-critical)" -} -check_timing -verbose -file "${report_dir}/13_check_timing.rpt" - -# Compile configuration summary into a single text file -set summary_fh [open "${report_dir}/00_build20_summary.txt" w] -puts $summary_fh "================================================================" -puts $summary_fh " AERIS-10 Build 20 — MMCM XDC Fix + CIC CREG Pipeline" -puts $summary_fh "================================================================" -puts $summary_fh "" -puts $summary_fh "Build Tag: $build_tag" -puts $summary_fh "Build Timestamp: $build_timestamp" -puts $summary_fh "FPGA Part: $fpga_part" -puts $summary_fh "Top Module: $top_module" -puts $summary_fh "RTL Files: $file_count" -puts $summary_fh "Synth Status: $synth_status" -puts $summary_fh "Synth Time: ${synth_elapsed}s" -puts $summary_fh "Impl Status: $impl_status" -puts $summary_fh "Impl Time: ${impl_elapsed}s" -puts $summary_fh "Bitstream Time: ${bit_elapsed}s" -puts $summary_fh "" - -# Extract key timing numbers — use catch to handle empty STATS properties -# (Vivado 2025.2 may return empty strings after write_bitstream auto-launch) -puts $summary_fh "--- Timing ---" -if {[catch {set wns [get_property STATS.WNS [current_design]]}] || $wns eq ""} { set wns "N/A" } -if {[catch {set tns [get_property STATS.TNS [current_design]]}] || $tns eq ""} { set tns "N/A" } -if {[catch {set whs [get_property STATS.WHS [current_design]]}] || $whs eq ""} { set whs "N/A" } -if {[catch {set ths [get_property STATS.THS [current_design]]}] || $ths eq ""} { set ths "N/A" } -if {[catch {set fail_ep [get_property STATS.TPWS [current_design]]}] || $fail_ep eq ""} { set fail_ep "N/A" } -puts $summary_fh " WNS: $wns ns" -puts $summary_fh " TNS: $tns ns" -puts $summary_fh " WHS: $whs ns" -puts $summary_fh " THS: $ths ns" -puts $summary_fh "" -puts $summary_fh " Build 18 Baseline: WNS = +0.062 ns, WHS = +0.059 ns" -puts $summary_fh " Build 19 (FAILED): WNS = -0.011 ns, WHS = +0.055 ns" -if {[string is double -strict $wns]} { - puts $summary_fh " Delta WNS vs B18: [expr {$wns - 0.062}] ns" -} else { - puts $summary_fh " Delta WNS vs B18: N/A (timing stats unavailable)" -} -if {[string is double -strict $whs]} { - puts $summary_fh " Delta WHS vs B18: [expr {$whs - 0.059}] ns" -} else { - puts $summary_fh " Delta WHS vs B18: N/A (timing stats unavailable)" -} -puts $summary_fh "" - -# Extract utilization -puts $summary_fh "--- Utilization ---" -set lut_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.LUT.*}]] -set ff_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.FF.*}]] -set bram_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ BMEM.*}]] -set dsp_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ MULT.DSP.*}]] -puts $summary_fh " LUTs: $lut_used / 134600" -puts $summary_fh " FFs: $ff_used / 269200" -puts $summary_fh " BRAM: $bram_used cells" -puts $summary_fh " DSP: $dsp_used cells" -puts $summary_fh "" -puts $summary_fh " Build 18 Baseline: LUTs=6088, FFs=8946, BRAM=16, DSP=140" -puts $summary_fh " Build 19: LUTs=6093, FFs=8949, BRAM=16, DSP=140" -puts $summary_fh " Expected Build 20: DSP=142 (+2 for comb_0_dsp I/Q)" -puts $summary_fh "" - -# Route status -set unrouted [llength [get_nets -hierarchical -filter {ROUTE_STATUS == UNROUTED}]] -puts $summary_fh "--- Route ---" -puts $summary_fh " Unrouted nets: $unrouted" -puts $summary_fh "" - -# MMCM usage -puts $summary_fh "--- MMCM Usage (Gap 7) ---" -set mmcm_count [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLOCK.MMCM.*}]] -puts $summary_fh " MMCME2 used: $mmcm_count / 10" -puts $summary_fh " Expected: 1 (adc_clk_mmcm jitter cleaner)" -puts $summary_fh "" - -# Bitstream -if {[file exists $bit_src]} { - puts $summary_fh "--- Bitstream ---" - puts $summary_fh " File: ${top_module}_${build_tag}.bit" - puts $summary_fh " Size: [file size $bit_src] bytes" -} else { - puts $summary_fh "--- Bitstream ---" - puts $summary_fh " WARNING: NOT GENERATED" -} -puts $summary_fh "" - -# Signoff -puts $summary_fh "--- Final Signoff ---" -set signoff_pass 1 -if {![string is double -strict $wns]} { - puts $summary_fh " WARN: WNS = N/A (timing stats unavailable — check reports)" -} elseif {$wns < 0} { - puts $summary_fh " FAIL: WNS = $wns (negative slack)" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: WNS = $wns ns (no setup violations)" -} -if {![string is double -strict $whs]} { - puts $summary_fh " WARN: WHS = N/A (timing stats unavailable — check reports)" -} elseif {$whs < 0} { - puts $summary_fh " FAIL: WHS = $whs (hold violation)" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: WHS = $whs ns (no hold violations)" -} -if {![string is double -strict $tns]} { - puts $summary_fh " WARN: TNS = N/A (timing stats unavailable — check reports)" -} elseif {$tns != 0} { - puts $summary_fh " FAIL: TNS = $tns (total negative slack)" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: TNS = 0 ns" -} -if {$unrouted > 0} { - puts $summary_fh " FAIL: $unrouted unrouted nets" - set signoff_pass 0 -} else { - puts $summary_fh " PASS: All nets routed" -} -if {[file exists $bit_src]} { - puts $summary_fh " PASS: Bitstream generated" -} else { - puts $summary_fh " FAIL: No bitstream" - set signoff_pass 0 -} -puts $summary_fh "" - -# Timing regression check vs Build 18 -if {[string is double -strict $wns] && $wns < 0.062} { - puts $summary_fh " *** WARNING: WNS REGRESSED vs Build 18 (was +0.062 ns, now $wns ns) ***" - puts $summary_fh " *** Review critical paths — CREG fix may not have helped ***" -} -if {[string is double -strict $whs] && $whs < 0.059} { - puts $summary_fh " *** WARNING: WHS REGRESSED vs Build 18 (was +0.059 ns, now $whs ns) ***" -} - -if {$signoff_pass} { - puts $summary_fh " *** SIGNOFF: PASS ***" -} else { - puts $summary_fh " *** SIGNOFF: FAIL ***" -} - -close $summary_fh -puts " Summary written to: ${report_dir}/00_build20_summary.txt" - -# ============================================================================== -# 6. SDF + Timing Netlist (for post-route simulation) -# ============================================================================== - -puts "" -puts "================================================================" -puts " Phase 5/5: SDF + Timing Netlist" -puts "================================================================" - -write_verilog -force -mode timesim "${sim_dir}/post_impl_timesim.v" -write_sdf -force "${sim_dir}/post_impl_timesim.sdf" - -close_design -open_run synth_1 -name synth_1 -write_verilog -force -mode funcsim "${sim_dir}/post_synth_funcsim.v" - -# ============================================================================== -# Done -# ============================================================================== - -set build_total [expr {[clock seconds] - $build_start}] -set build_end [clock format [clock seconds] -format {%Y-%m-%d %H:%M:%S}] - -puts "" -puts "================================================================" -puts " BUILD 20 COMPLETE" -puts "================================================================" -puts " Started: $build_timestamp" -puts " Finished: $build_end" -puts " Total time: ${build_total}s ([expr {$build_total/60}]m [expr {$build_total%60}]s)" -puts " Synth: ${synth_elapsed}s" -puts " Impl: ${impl_elapsed}s" -puts " Bitstream: ${bit_elapsed}s" -puts " Reports: $report_dir" -puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit" -puts " WNS: $wns ns | WHS: $whs ns | TNS: $tns ns" -puts " Build 18 baseline: WNS +0.062 | WHS +0.059" -puts " Build 19 (failed): WNS -0.011 | WHS +0.055" -if {$signoff_pass} { - puts " SIGNOFF: PASS" -} else { - puts " SIGNOFF: FAIL" -} -puts "================================================================" - -close_project -puts "Done." diff --git a/9_Firmware/9_2_FPGA/scripts/build_te0712_dev.tcl b/9_Firmware/9_2_FPGA/scripts/te0712/build_te0712_dev.tcl similarity index 96% rename from 9_Firmware/9_2_FPGA/scripts/build_te0712_dev.tcl rename to 9_Firmware/9_2_FPGA/scripts/te0712/build_te0712_dev.tcl index dcb7948..0c573fd 100644 --- a/9_Firmware/9_2_FPGA/scripts/build_te0712_dev.tcl +++ b/9_Firmware/9_2_FPGA/scripts/te0712/build_te0712_dev.tcl @@ -11,7 +11,7 @@ # pins and placeholder LED/status pins. set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] +set project_root [file normalize [file join $script_dir "../.."]] set project_name "aeris10_te0712_dev" set build_dir [file join $project_root "vivado_te0712_dev"] diff --git a/9_Firmware/9_2_FPGA/scripts/build_te0713_dev.tcl b/9_Firmware/9_2_FPGA/scripts/te0713/build_te0713_dev.tcl similarity index 96% rename from 9_Firmware/9_2_FPGA/scripts/build_te0713_dev.tcl rename to 9_Firmware/9_2_FPGA/scripts/te0713/build_te0713_dev.tcl index db5e314..db7f55f 100644 --- a/9_Firmware/9_2_FPGA/scripts/build_te0713_dev.tcl +++ b/9_Firmware/9_2_FPGA/scripts/te0713/build_te0713_dev.tcl @@ -6,7 +6,7 @@ # vivado -mode batch -source scripts/build_te0713_dev.tcl set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] +set project_root [file normalize [file join $script_dir "../.."]] set project_name "aeris10_te0713_dev" set build_dir [file join $project_root "vivado_te0713_dev"] diff --git a/9_Firmware/9_2_FPGA/scripts/build_te0713_umft601x_dev.tcl b/9_Firmware/9_2_FPGA/scripts/te0713/build_te0713_umft601x_dev.tcl similarity index 97% rename from 9_Firmware/9_2_FPGA/scripts/build_te0713_umft601x_dev.tcl rename to 9_Firmware/9_2_FPGA/scripts/te0713/build_te0713_umft601x_dev.tcl index f58cbe9..394bcdf 100644 --- a/9_Firmware/9_2_FPGA/scripts/build_te0713_umft601x_dev.tcl +++ b/9_Firmware/9_2_FPGA/scripts/te0713/build_te0713_umft601x_dev.tcl @@ -3,7 +3,7 @@ # Vivado batch build for Trenz TE0713/TE0701 with UMFT601X-B over FMC LPC. set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] +set project_root [file normalize [file join $script_dir "../.."]] set project_name "aeris10_te0713_umft601x_dev" set build_dir [file join $project_root "vivado_te0713_umft601x_dev"] diff --git a/9_Firmware/9_2_FPGA/scripts/ila_capture.tcl b/9_Firmware/9_2_FPGA/scripts/utils/ila_capture.tcl similarity index 99% rename from 9_Firmware/9_2_FPGA/scripts/ila_capture.tcl rename to 9_Firmware/9_2_FPGA/scripts/utils/ila_capture.tcl index 43276fd..2172df3 100644 --- a/9_Firmware/9_2_FPGA/scripts/ila_capture.tcl +++ b/9_Firmware/9_2_FPGA/scripts/utils/ila_capture.tcl @@ -35,7 +35,7 @@ set default_server "localhost" set default_port 3121 set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] +set project_root [file normalize [file join $script_dir "../.."]] set default_ltx [file join $project_root "build" "aeris10_radar.runs" "impl_ila" "radar_system_top.ltx"] set default_output_base [file join $project_root "build" "captures"] set default_depth 4096 diff --git a/9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl b/9_Firmware/9_2_FPGA/scripts/utils/insert_ila_probes.tcl similarity index 99% rename from 9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl rename to 9_Firmware/9_2_FPGA/scripts/utils/insert_ila_probes.tcl index beef869..f38a544 100644 --- a/9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl +++ b/9_Firmware/9_2_FPGA/scripts/utils/insert_ila_probes.tcl @@ -33,7 +33,7 @@ # ============================================================================== set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] +set project_root [file normalize [file join $script_dir "../.."]] set project_base [file join $project_root "build"] set synth_dcp "${project_base}/aeris10_radar.runs/synth_1/radar_system_top.dcp" set synth_xdc [file join $project_root "constraints" "xc7a200t_fbg484.xdc"] diff --git a/9_Firmware/9_2_FPGA/scripts/program_fpga.tcl b/9_Firmware/9_2_FPGA/scripts/utils/program_fpga.tcl similarity index 99% rename from 9_Firmware/9_2_FPGA/scripts/program_fpga.tcl rename to 9_Firmware/9_2_FPGA/scripts/utils/program_fpga.tcl index a88245e..c0170dc 100644 --- a/9_Firmware/9_2_FPGA/scripts/program_fpga.tcl +++ b/9_Firmware/9_2_FPGA/scripts/utils/program_fpga.tcl @@ -26,7 +26,7 @@ set default_server "localhost" set default_port 3121 set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] +set project_root [file normalize [file join $script_dir "../.."]] set default_bit [file join $project_root "build" "bitstream" "radar_system_top_build21.bit"] set default_ltx [file join $project_root "build" "aeris10_radar.runs" "impl_ila" "radar_system_top.ltx"] set expected_part "xc7a200t" diff --git a/9_Firmware/9_2_FPGA/scripts/run_cdc_and_netlist.tcl b/9_Firmware/9_2_FPGA/scripts/utils/run_cdc_and_netlist.tcl similarity index 96% rename from 9_Firmware/9_2_FPGA/scripts/run_cdc_and_netlist.tcl rename to 9_Firmware/9_2_FPGA/scripts/utils/run_cdc_and_netlist.tcl index 408f83a..3619454 100644 --- a/9_Firmware/9_2_FPGA/scripts/run_cdc_and_netlist.tcl +++ b/9_Firmware/9_2_FPGA/scripts/utils/run_cdc_and_netlist.tcl @@ -6,7 +6,7 @@ # Usage: vivado -mode batch -source run_cdc_and_netlist.tcl set script_dir [file dirname [file normalize [info script]]] -set project_root [file normalize [file join $script_dir ".."]] +set project_root [file normalize [file join $script_dir "../.."]] set project_dir [file join $project_root "build"] set report_dir "${project_dir}/reports_impl" file mkdir $report_dir