fix(xdc): add hold false_path for ADC IDDR + reorganize build scripts by target
- Add set_false_path -hold for source-synchronous ADC IDDR paths in adc_clk_mmcm.xdc (eliminates 8 hold violations from build 12) - Add DDR falling-edge input delay constraints to xc7a50t_ftg256.xdc (parity with 200T XDC) - Reorganize scripts/ into target subdirectories: 50t/, 200t/, te0712/, te0713/, utils/ so users can run the correct build for their hardware - Delete obsolete build scripts (build17-20) superseded by build_50t/200t - Update project_root paths in all moved scripts (.. -> ../..)
This commit is contained in:
Jason
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################################################################################
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# build_50t.tcl — XC7A50T Production Build
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# Builds the AERIS-10 design targeting the production 50T (FTG256) board
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#
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# Usage:
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# cd 9_Firmware/9_2_FPGA
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# vivado -mode batch -source scripts/50t/build_50t.tcl 2>&1 | tee build_50t/vivado.log
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################################################################################
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set project_name "aeris10_radar_50t"
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set script_dir [file dirname [file normalize [info script]]]
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set project_root [file normalize [file join $script_dir "../.."]]
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set project_dir [file join $project_root "build_50t"]
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set rtl_dir $project_root
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set fpga_part "xc7a50tftg256-2"
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set top_module "radar_system_top_50t"
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puts "================================================================"
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puts " AERIS-10 — XC7A50T Production Build"
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puts " Target: $fpga_part"
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puts " Project: $project_dir"
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puts "================================================================"
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file mkdir $project_dir
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set report_dir [file join $project_dir "reports_50t"]
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file mkdir $report_dir
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set bit_dir [file join $project_dir "bitstream"]
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file mkdir $bit_dir
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create_project $project_name $project_dir -part $fpga_part -force
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# Add ALL RTL files in the project root (avoid stale/dev tops)
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set skip_patterns {*_te0712_* *_te0713_*}
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foreach f [glob -directory $rtl_dir *.v] {
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set skip 0
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foreach pat $skip_patterns {
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if {[string match $pat [file tail $f]]} { set skip 1; break }
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}
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if {!$skip} {
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add_files -norecurse $f
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puts " Added: [file tail $f]"
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}
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}
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set_property top $top_module [current_fileset]
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set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
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# Constraints — 50T XDC + MMCM supplement
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add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a50t_ftg256.xdc"]
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add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "adc_clk_mmcm.xdc"]
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# ============================================================================
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# DRC SEVERITY WAIVERS — 50T Hardware-Specific
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# ============================================================================
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# NOTE: DRC severity waivers are set both before synthesis and after open_run
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# synth_1. Implementation uses direct commands (opt_design, place_design, etc.)
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# rather than launch_runs/wait_on_run, so all commands share the same Vivado
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# context where the waivers are active.
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#
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# The top module is radar_system_top_50t — a thin wrapper that exposes only
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# the 64 physically-connected ports on the FTG256 board. Unconstrained ports
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# (FT601, debug, status) are tied off internally, keeping the full radar
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# pipeline intact while fitting within the 69 available IO pins.
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#
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# BIVC-1: Bank 14 VCCO=2.5V (enforced by LVDS_25) with LVCMOS25 adc_pwdn.
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# This should no longer fire now that adc_pwdn is LVCMOS25, but we keep
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# the waiver as a safety net in case future XDC changes re-introduce the
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# conflict.
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set_property SEVERITY {Warning} [get_drc_checks BIVC-1]
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# NSTD-1 / UCIO-1: 118 unconstrained port bits — FT601 USB 3.0 (chip unwired
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# on 50T board), dac_clk (DAC clock from AD9523, not FPGA), and all
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# status/debug outputs (no physical pins on FTG256 package).
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set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
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set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
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# ===== SYNTHESIS =====
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set synth_start [clock seconds]
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launch_runs synth_1 -jobs 8
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wait_on_run synth_1
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set synth_elapsed [expr {[clock seconds] - $synth_start}]
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set synth_status [get_property STATUS [get_runs synth_1]]
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puts " Synthesis status: $synth_status"
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puts " Synthesis time: ${synth_elapsed}s"
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if {![string match "*Complete*" $synth_status]} {
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puts "CRITICAL: SYNTHESIS FAILED: $synth_status"
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close_project
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exit 1
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}
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open_run synth_1
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report_timing_summary -file "${report_dir}/01_timing_post_synth.rpt"
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report_utilization -file "${report_dir}/01_utilization_post_synth.rpt"
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# ===== IMPLEMENTATION (non-project-mode style) =====
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# We run implementation steps directly in the parent process instead of
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# using launch_runs/wait_on_run. This ensures DRC waivers are active in
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# the same Vivado context as place_design.
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set impl_start [clock seconds]
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# Re-apply DRC waivers in this context (parent process)
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set_property SEVERITY {Warning} [get_drc_checks BIVC-1]
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set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
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set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
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# ---- Run implementation steps ----
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opt_design -directive Explore
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place_design -directive Explore
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phys_opt_design -directive AggressiveExplore
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route_design -directive Explore
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phys_opt_design -directive AggressiveExplore
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set impl_elapsed [expr {[clock seconds] - $impl_start}]
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puts " Implementation time: ${impl_elapsed}s"
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# ===== BITSTREAM =====
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set bit_start [clock seconds]
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set dst_bit [file join $bit_dir "radar_system_top_50t.bit"]
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write_bitstream -force $dst_bit
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set bit_elapsed [expr {[clock seconds] - $bit_start}]
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if {[file exists $dst_bit]} {
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puts " Bitstream: $dst_bit ([expr {[file size $dst_bit] / 1024}] KB)"
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} else {
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puts " WARNING: Bitstream not generated!"
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}
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# ===== REPORTS =====
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report_timing_summary -file "${report_dir}/02_timing_summary.rpt"
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report_utilization -file "${report_dir}/04_utilization.rpt"
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report_drc -file "${report_dir}/06_drc.rpt"
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report_io -file "${report_dir}/07_io.rpt"
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puts "================================================================"
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puts " XC7A50T Build Complete"
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puts " Synth: ${synth_elapsed}s"
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puts " Impl: ${impl_elapsed}s"
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puts " Bit: ${bit_elapsed}s"
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set wns_val "N/A"
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set whs_val "N/A"
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catch {set wns_val [get_property STATS.WNS [current_design]]}
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catch {set whs_val [get_property STATS.WHS [current_design]]}
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puts " WNS: $wns_val ns"
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puts " WHS: $whs_val ns"
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puts "================================================================"
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close_project
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exit 0
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