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fix(xdc): add hold false_path for ADC IDDR + reorganize build scripts by target

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- Add set_false_path -hold for source-synchronous ADC IDDR paths in
  adc_clk_mmcm.xdc (eliminates 8 hold violations from build 12)
- Add DDR falling-edge input delay constraints to xc7a50t_ftg256.xdc
  (parity with 200T XDC)
- Reorganize scripts/ into target subdirectories: 50t/, 200t/, te0712/,
  te0713/, utils/ so users can run the correct build for their hardware
- Delete obsolete build scripts (build17-20) superseded by build_50t/200t
- Update project_root paths in all moved scripts (.. -> ../..)
This commit is contained in:
Jason
2026-04-07 15:13:13 +03:00
parent 8d7b6e04a0
commit 849b32240b
15 changed files with 41 additions and 1974 deletions
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9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc
+3
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@@ -255,8 +255,11 @@ set_property IOSTANDARD LVDS_25 [get_ports {adc_d_n[*]}]
set_property DIFF_TERM TRUE [get_ports {adc_d_p[*]}]
# Input delay for ADC data relative to DCO (adjust based on PCB trace length)
# DDR interface: constrain both rising and falling clock edges
set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 [get_ports {adc_d_p[*]}]
set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_d_p[*]}]
set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
# ============================================================================
# FT601 USB 3.0 INTERFACE — ACTIVE: NO PHYSICAL CONNECTIONS