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Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments

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- Changed user_led/system_status IOSTANDARD from LVCMOS25 to LVCMOS33
  to match VIOTB=3.3V needed for FT601 on Bank 16
- Added register init value for hb_counter
- Added comments documenting clock source (50 MHz FIFO0CLK at U20, Bank 14)
  and expected LED toggle rates
This commit is contained in:
Jason
2026-03-19 16:47:59 +02:00
parent e78e36a635
commit 683e70e784
2 changed files with 22 additions and 9 deletions
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9_Firmware/9_2_FPGA/constraints/te0713_te0701_minimal.xdc
+3 -3
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@@ -23,9 +23,9 @@ set_property IOSTANDARD LVCMOS15 [get_ports {clk_100m}]
# Status/output IO standards
# These outputs are exported to TE0701 FMC LA lines (not onboard LEDs).
# Assumption: FMC VADJ/VCCIO16 is set for 2.5V signaling.
set_property IOSTANDARD LVCMOS25 [get_ports {user_led[*]}]
set_property IOSTANDARD LVCMOS25 [get_ports {system_status[*]}]
# Bank 16 VCCO = VIOTB on TE0701, set to 3.3V for FT601 compatibility.
set_property IOSTANDARD LVCMOS33 [get_ports {user_led[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {system_status[*]}]
# Clock constraint (TE0713 FIFO0CLK source observed as 50 MHz)
create_clock -name clk_100m -period 20.000 [get_ports {clk_100m}]