diff --git a/9_Firmware/9_2_FPGA/constraints/te0713_te0701_minimal.xdc b/9_Firmware/9_2_FPGA/constraints/te0713_te0701_minimal.xdc
index e87c131..7a8f1d8 100644
--- a/9_Firmware/9_2_FPGA/constraints/te0713_te0701_minimal.xdc
+++ b/9_Firmware/9_2_FPGA/constraints/te0713_te0701_minimal.xdc
@@ -23,9 +23,9 @@ set_property IOSTANDARD LVCMOS15 [get_ports {clk_100m}]
 
 # Status/output IO standards
 # These outputs are exported to TE0701 FMC LA lines (not onboard LEDs).
-# Assumption: FMC VADJ/VCCIO16 is set for 2.5V signaling.
-set_property IOSTANDARD LVCMOS25 [get_ports {user_led[*]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {system_status[*]}]
+# Bank 16 VCCO = VIOTB on TE0701, set to 3.3V for FT601 compatibility.
+set_property IOSTANDARD LVCMOS33 [get_ports {user_led[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {system_status[*]}]
 
 # Clock constraint (TE0713 FIFO0CLK source observed as 50 MHz)
 create_clock -name clk_100m -period 20.000 [get_ports {clk_100m}]
diff --git a/9_Firmware/9_2_FPGA/radar_system_top_te0713_dev.v b/9_Firmware/9_2_FPGA/radar_system_top_te0713_dev.v
index ffa167e..11057d3 100644
--- a/9_Firmware/9_2_FPGA/radar_system_top_te0713_dev.v
+++ b/9_Firmware/9_2_FPGA/radar_system_top_te0713_dev.v
@@ -1,20 +1,33 @@
 `timescale 1ns / 1ps
+//
+// AERIS-10 TE0713+TE0701 Dev Heartbeat
+//
+// Minimal design to verify FPGA configuration and clock.
+// Uses TE0713 FIFO0CLK (50 MHz, Bank 14, LVCMOS15) at pin U20.
+// LEDs and status outputs on Bank 16 FMC LA pins (LVCMOS33).
+//
+// At 50 MHz:
+//   user_led[0] toggles at ~1.49 Hz  (bit 24)
+//   user_led[1] toggles at ~0.75 Hz  (bit 25)
+//   user_led[2] toggles at ~0.37 Hz  (bit 26)
+//   user_led[3] toggles at ~0.19 Hz  (bit 27)
+//
 
 module radar_system_top_te0713_dev (
-    input wire clk_100m,
+    input wire clk_100m,        // TE0713 FIFO0CLK (actually 50 MHz)
     output wire [3:0] user_led,
     output wire [3:0] system_status
 );
 
-wire clk_100m_buf;
-reg [31:0] hb_counter;
+wire clk_buf;
+reg [31:0] hb_counter = 32'd0;
 
-BUFG bufg_100m (
+BUFG bufg_clk (
     .I(clk_100m),
-    .O(clk_100m_buf)
+    .O(clk_buf)
 );
 
-always @(posedge clk_100m_buf) begin
+always @(posedge clk_buf) begin
     hb_counter <= hb_counter + 1'b1;
 end