Update docs for Gap 2 GUI Settings completion (5 of 7 gaps closed)
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Jason
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<section class="card" style="margin-top:0.8rem;">
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<h2>Recent milestone timeline</h2>
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<div class="timeline">
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<article>
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<h3>Gap 2: GUI Settings — runtime chirp timing, stream control, status readback (7cdfa48)</h3>
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<p class="muted">Radar chirp timing parameters (long/short chirp, listen, guard cycles, chirps-per-elevation) are now runtime-configurable via 6 new USB opcodes (0x10-0x15). Stream control (opcode 0x04) gates the USB write FSM per-stream. CFAR threshold (opcode 0x03) is wired to actual comparison logic (was hardcoded). Status readback (opcode 0xFF) returns a 7-word packet with all current settings. CDC handled via per-bit 2-stage synchronizers (stream control) and toggle CDC (status request). 4 new testbench groups added. 18/18 FPGA, 20/20 MCU.</p>
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</article>
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<article>
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<h3>Gap 4: USB Read Path wired with toggle CDC (e5d1b3c)</h3>
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<p class="muted">FT601 read FSM cmd_* outputs connected through toggle CDC to clk_100m command decode registers in radar_system_top.v. Host can now set radar mode, trigger chirps, set CFAR threshold, and control data streaming via USB. 3 new testbench groups (55 total checks). 18/18 FPGA regression.</p>
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<ul>
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<li>FPGA regression: 18/18 passing suites covering matched filter, Doppler, CIC, CDC, USB (with read path), FFT, NCO, FIR, range decimator, mode controller, and system-top integration.</li>
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<li>MCU regression: 20/20 passing tests (15 bug-fix + 5 Gap-3 safety tests).</li>
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<li>Architectural gaps 3, 4, 5, 7 closed with full test coverage. Gaps 1, 2, 6 deferred to post-bring-up or pre-tuning.</li>
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<li>USB host-to-FPGA command path fully wired: read FSM, toggle CDC, command decode for mode/trigger/CFAR/stream control.</li>
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<li>Architectural gaps 2, 3, 4, 5, 7 closed with full test coverage. Gaps 1 and 6 deferred to post-bring-up.</li>
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<li>USB host-to-FPGA command path fully wired: read FSM, toggle CDC, command decode for mode/trigger/CFAR/stream control. GUI settings (chirp timing, stream gating, status readback) fully operational.</li>
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<li>Safety architecture: IWDG watchdog, emergency stop PA cutoff, temperature guard, IDQ re-read, state ordering.</li>
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</ul>
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</article>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td><code>7cdfa48</code></td>
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<td>Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback</td>
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<td>Runtime-configurable chirp timing (6 new opcodes 0x10-0x15), stream control gating (opcode 0x04 now gates USB write FSM), CFAR threshold wiring (opcode 0x03 replaces hardcoded value), status readback (opcode 0xFF returns 7-word packet). 4 new TB test groups. 18/18 FPGA, 20/20 MCU regression.</td>
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</tr>
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<tr>
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<td><code>e5d1b3c</code></td>
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<td>Gap 4 USB Read Path: host-to-FPGA command path with toggle CDC</td>
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<tr><td>5</td><td>BRAM Async Reset</td><td>Done (c87dce0)</td></tr>
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<tr><td>7</td><td>400 MHz MMCM</td><td>Done (c6103b3, Build 20)</td></tr>
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<tr><td>4</td><td>USB Read Path</td><td>Done (e5d1b3c)</td></tr>
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<tr><td>2</td><td>GUI Settings</td><td>Next</td></tr>
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<tr><td>2</td><td>GUI Settings</td><td>Done (7cdfa48)</td></tr>
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<tr><td>6</td><td>CDC-15 USB Buses</td><td>Post-bring-up</td></tr>
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<tr><td>1</td><td>CFAR Real Implementation</td><td>Post-bring-up</td></tr>
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</tbody>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Open in GitHub</h2>
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<ul>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/7cdfa48" target="_blank" rel="noopener">7cdfa48</a> Gap 2 GUI Settings</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/e5d1b3c" target="_blank" rel="noopener">e5d1b3c</a> Gap 4 USB Read Path</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c6103b3" target="_blank" rel="noopener">c6103b3</a> Gap 7 MMCM + CREG (v0.1.3-build20)</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/f3bbf77" target="_blank" rel="noopener">f3bbf77</a> Gap 3 Safety Architecture</li>
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+1
-1
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<h2>Report Currency Notice</h2>
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<ul>
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<li>The current routed production-target baseline is <strong>Build 20 (v0.1.3-build20)</strong> with all timing constraints met and 7x setup slack improvement over Build 18.</li>
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<li>Architectural gaps 3 (Safety), 4 (USB Read Path), 5 (BRAM Reset), and 7 (MMCM) are closed. Gaps 1 (CFAR), 2 (GUI), and 6 (CDC-15) remain for post-bring-up or pre-tuning.</li>
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<li>Architectural gaps 2 (GUI Settings), 3 (Safety), 4 (USB Read Path), 5 (BRAM Reset), and 7 (MMCM) are closed. Gaps 1 (CFAR) and 6 (CDC-15) remain for post-bring-up.</li>
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<li>FPGA regression: 18/18 pass. MCU regression: 20/20 pass (15 bug-fix + 5 Gap-3 safety).</li>
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<li>Detailed Build 20 engineering reports are on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build20/</code>.</li>
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<li>The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.</li>
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