+
+ Gap 2: GUI Settings — runtime chirp timing, stream control, status readback (7cdfa48)
+ Radar chirp timing parameters (long/short chirp, listen, guard cycles, chirps-per-elevation) are now runtime-configurable via 6 new USB opcodes (0x10-0x15). Stream control (opcode 0x04) gates the USB write FSM per-stream. CFAR threshold (opcode 0x03) is wired to actual comparison logic (was hardcoded). Status readback (opcode 0xFF) returns a 7-word packet with all current settings. CDC handled via per-bit 2-stage synchronizers (stream control) and toggle CDC (status request). 4 new testbench groups added. 18/18 FPGA, 20/20 MCU.
+
Gap 4: USB Read Path wired with toggle CDC (e5d1b3c)
FT601 read FSM cmd_* outputs connected through toggle CDC to clk_100m command decode registers in radar_system_top.v. Host can now set radar mode, trigger chirps, set CFAR threshold, and control data streaming via USB. 3 new testbench groups (55 total checks). 18/18 FPGA regression.
@@ -71,8 +75,8 @@
- FPGA regression: 18/18 passing suites covering matched filter, Doppler, CIC, CDC, USB (with read path), FFT, NCO, FIR, range decimator, mode controller, and system-top integration.
- MCU regression: 20/20 passing tests (15 bug-fix + 5 Gap-3 safety tests).
- - Architectural gaps 3, 4, 5, 7 closed with full test coverage. Gaps 1, 2, 6 deferred to post-bring-up or pre-tuning.
- - USB host-to-FPGA command path fully wired: read FSM, toggle CDC, command decode for mode/trigger/CFAR/stream control.
+ - Architectural gaps 2, 3, 4, 5, 7 closed with full test coverage. Gaps 1 and 6 deferred to post-bring-up.
+ - USB host-to-FPGA command path fully wired: read FSM, toggle CDC, command decode for mode/trigger/CFAR/stream control. GUI settings (chirp timing, stream gating, status readback) fully operational.
- Safety architecture: IWDG watchdog, emergency stop PA cutoff, temperature guard, IDQ re-read, state ordering.
diff --git a/docs/release-notes.html b/docs/release-notes.html
index 2ac4db1..730a938 100644
--- a/docs/release-notes.html
+++ b/docs/release-notes.html
@@ -39,6 +39,11 @@
+
+ 7cdfa48 |
+ Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback |
+ Runtime-configurable chirp timing (6 new opcodes 0x10-0x15), stream control gating (opcode 0x04 now gates USB write FSM), CFAR threshold wiring (opcode 0x03 replaces hardcoded value), status readback (opcode 0xFF returns 7-word packet). 4 new TB test groups. 18/18 FPGA, 20/20 MCU regression. |
+
e5d1b3c |
Gap 4 USB Read Path: host-to-FPGA command path with toggle CDC |
@@ -114,7 +119,7 @@
| 5 | BRAM Async Reset | Done (c87dce0) |
| 7 | 400 MHz MMCM | Done (c6103b3, Build 20) |
| 4 | USB Read Path | Done (e5d1b3c) |
- | 2 | GUI Settings | Next |
+ | 2 | GUI Settings | Done (7cdfa48) |
| 6 | CDC-15 USB Buses | Post-bring-up |
| 1 | CFAR Real Implementation | Post-bring-up |
@@ -125,6 +130,7 @@
Open in GitHub
+ - 7cdfa48 Gap 2 GUI Settings
- e5d1b3c Gap 4 USB Read Path
- c6103b3 Gap 7 MMCM + CREG (v0.1.3-build20)
- f3bbf77 Gap 3 Safety Architecture
diff --git a/docs/reports.html b/docs/reports.html
index 024cd52..bf09d24 100644
--- a/docs/reports.html
+++ b/docs/reports.html
@@ -112,7 +112,7 @@
Report Currency Notice
- The current routed production-target baseline is Build 20 (v0.1.3-build20) with all timing constraints met and 7x setup slack improvement over Build 18.
- - Architectural gaps 3 (Safety), 4 (USB Read Path), 5 (BRAM Reset), and 7 (MMCM) are closed. Gaps 1 (CFAR), 2 (GUI), and 6 (CDC-15) remain for post-bring-up or pre-tuning.
+ - Architectural gaps 2 (GUI Settings), 3 (Safety), 4 (USB Read Path), 5 (BRAM Reset), and 7 (MMCM) are closed. Gaps 1 (CFAR) and 6 (CDC-15) remain for post-bring-up.
- FPGA regression: 18/18 pass. MCU regression: 20/20 pass (15 bug-fix + 5 Gap-3 safety).
- Detailed Build 20 engineering reports are on the remote Vivado host at
~/PLFM_RADAR_work/vivado_project/reports_build20/.
- The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.