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fix(fpga): wire F-0.1 adc_or_p/n through 50T wrapper + remove xdc control-flow

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Build-blocking fixes surfaced by gpu-server synth:

1. radar_system_top_50t.v wrapper was missing adc_or_p/n ports and the
   u_core instantiation left them unconnected. Every XDC line in the 50T
   anchor block (PACKAGE_PIN M6/N6, IOSTANDARD, DIFF_TERM, set_input_delay)
   therefore matched no ports and emitted CRITICAL WARNINGs, leaving the
   overrange pin effectively tied off. Added the two inputs and wired them
   through to the core.

2. adc_clk_mmcm.xdc used foreach / unset — Vivado's XDC parser only
   accepts a restricted Tcl subset and rejected them as
   [Designutils 20-1307]. Moved the clk_mmcm_out0 ↔ USB-clock false paths
   into each board XDC (ft_clkout for 50T, ft601_clk_in for 200T) where
   the clock name is already known.
This commit is contained in:
Jason
2026-04-20 16:08:13 +05:45
parent 51740fd6f5
commit 0067969ee7
4 changed files with 18 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc
+4
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@@ -463,6 +463,10 @@ set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_100m]
set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks ft_clkout]
set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_120m_dac]
# MMCM 400 MHz domain ↔ FT2232H USB clock (see adc_clk_mmcm.xdc for rationale)
set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft_clkout]
set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_mmcm_out0]
# ============================================================================
# PHYSICAL CONSTRAINTS
# ============================================================================