From 0067969ee7290d22588e528b42faaf3ced522aee Mon Sep 17 00:00:00 2001
From: Jason <83615043+JJassonn69@users.noreply.github.com>
Date: Mon, 20 Apr 2026 16:08:13 +0545
Subject: [PATCH] fix(fpga): wire F-0.1 adc_or_p/n through 50T wrapper + remove
 xdc control-flow
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Build-blocking fixes surfaced by gpu-server synth:

1. radar_system_top_50t.v wrapper was missing adc_or_p/n ports and the
   u_core instantiation left them unconnected. Every XDC line in the 50T
   anchor block (PACKAGE_PIN M6/N6, IOSTANDARD, DIFF_TERM, set_input_delay)
   therefore matched no ports and emitted CRITICAL WARNINGs, leaving the
   overrange pin effectively tied off. Added the two inputs and wired them
   through to the core.

2. adc_clk_mmcm.xdc used foreach / unset — Vivado's XDC parser only
   accepts a restricted Tcl subset and rejected them as
   [Designutils 20-1307]. Moved the clk_mmcm_out0 ↔ USB-clock false paths
   into each board XDC (ft_clkout for 50T, ft601_clk_in for 200T) where
   the clock name is already known.
---
 9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc | 16 ++++++----------
 .../9_2_FPGA/constraints/xc7a200t_fbg484.xdc     |  4 ++++
 .../9_2_FPGA/constraints/xc7a50t_ftg256.xdc      |  4 ++++
 9_Firmware/9_2_FPGA/radar_system_top_50t.v       |  4 ++++
 4 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc b/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
index c3c1254..cd30508 100644
--- a/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
+++ b/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
@@ -47,16 +47,12 @@ set_max_delay -datapath_only -from [get_clocks clk_mmcm_out0] \
 set_false_path -from [get_clocks clk_100m] -to [get_clocks clk_mmcm_out0]
 set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks clk_100m]
 
-# Audit F-0.6: the clock name `ft601_clk_in` does not exist on either 50T
-# (FT2232H, clock is `ft_clkout`) or 200T builds in the current RTL. Waive
-# against whichever USB-domain clock is actually defined in the build.
-foreach _usb_clk {ft_clkout ft601_clk ft601_clk_in} {
-    if {[llength [get_clocks -quiet $_usb_clk]] > 0} {
-        set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks $_usb_clk]
-        set_false_path -from [get_clocks $_usb_clk] -to [get_clocks clk_mmcm_out0]
-    }
-}
-unset _usb_clk
+# Audit F-0.6: the USB-domain clock name differs per board
+# (50T: ft_clkout, 200T: ft601_clk_in). XDC files only support a
+# restricted Tcl subset — `foreach`/`unset` trigger CRITICAL WARNING
+# [Designutils 20-1307]. The clk_mmcm_out0 ↔ USB-clock false paths
+# are declared in the per-board XDC (xc7a50t_ftg256.xdc and
+# xc7a200t_fbg484.xdc) where the USB clock name is already known.
 
 set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks clk_120m_dac]
 set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_mmcm_out0]
diff --git a/9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc b/9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc
index 6290737..2290f42 100644
--- a/9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc
+++ b/9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc
@@ -637,6 +637,10 @@ set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_120m_dac]
 set_false_path -from [get_clocks adc_dco_p] -to [get_clocks ft601_clk_in]
 set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks adc_dco_p]
 
+# MMCM 400 MHz domain ↔ FT601 USB clock (see adc_clk_mmcm.xdc for rationale)
+set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft601_clk_in]
+set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_mmcm_out0]
+
 # Generated clock cross-domain paths:
 # dac_clk_fwd and ft601_clk_fwd are generated from their respective source
 # clocks. Vivado automatically inherits the source clock false paths for
diff --git a/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc b/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc
index 4696edd..2c3f999 100644
--- a/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc
+++ b/9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc
@@ -463,6 +463,10 @@ set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_100m]
 set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks ft_clkout]
 set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_120m_dac]
 
+# MMCM 400 MHz domain ↔ FT2232H USB clock (see adc_clk_mmcm.xdc for rationale)
+set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft_clkout]
+set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_mmcm_out0]
+
 # ============================================================================
 # PHYSICAL CONSTRAINTS
 # ============================================================================
diff --git a/9_Firmware/9_2_FPGA/radar_system_top_50t.v b/9_Firmware/9_2_FPGA/radar_system_top_50t.v
index fc3585a..1842f96 100644
--- a/9_Firmware/9_2_FPGA/radar_system_top_50t.v
+++ b/9_Firmware/9_2_FPGA/radar_system_top_50t.v
@@ -60,6 +60,8 @@ module radar_system_top_50t (
     input wire [7:0] adc_d_n,
     input wire adc_dco_p,
     input wire adc_dco_n,
+    input wire adc_or_p,
+    input wire adc_or_n,
     output wire adc_pwdn,
 
     // ===== STM32 Control (Bank 15: 3.3V) =====
@@ -171,6 +173,8 @@ module radar_system_top_50t (
         .adc_d_n                (adc_d_n),
         .adc_dco_p              (adc_dco_p),
         .adc_dco_n              (adc_dco_n),
+        .adc_or_p               (adc_or_p),
+        .adc_or_n               (adc_or_n),
         .adc_pwdn               (adc_pwdn),
 
         // ----- STM32 Control -----