Jason
eefaf94e9e
Resolves all synthesis errors across attempts 3-11, achieving clean Vivado 2025.2 synthesis on XC7A100T (0 errors, 831 LUTs, 320 FFs, 2 DSPs). radar_receiver_final.v: - reg clk_400m -> wire; output reg -> output wire (x4) - Replace ad9484_lvds_to_cmos_400m with ad9484_interface_400m - Remove duplicate IBUFDS lvds_to_cmos_400m instantiation - Remove non-existent ref_i/ref_q port connections on matched filter - Connect adc_dco_bufg as 400MHz clock source ad9484_interface_400m.v: - Add adc_dco_bufg output port with BUFG instance - Route all internal logic through buffered DCO clock cic_decimator_4x_enhanced.v: - Move reset_monitors handling inside else branch (fixes Vivado ambiguous clock error in both integrator and comb always blocks) - Add separate comb_overflow_latched/comb_saturation_detected regs to eliminate multi-driven nets between integrator and comb blocks - Remove standalone always @(posedge reset_monitors) block - Add output_counter to async reset branch matched_filter_processing_chain.v: - Wrap behavioral FFT body (uses $cos/$sin/$rtoi) in ifdef SIMULATION - Add synthesis stub tying outputs to safe defaults chirp_memory_loader_param.v: - Replace hardcoded Windows paths with relative filenames for all 10 $readmem default parameters latency_buffer_2159.v: - Split single always block into separate BRAM write (synchronous only) and control logic (with async reset) blocks - Fixes Vivado Synth 8-3391: BRAM cannot infer with async reset xfft_32.v (NEW): - Synthesis stub for Xilinx 32-point FFT IP core - AXI-Stream interface with pass-through and 1-cycle latency - Placeholder until real xfft IP is generated
72 lines
2.6 KiB
Verilog
72 lines
2.6 KiB
Verilog
`timescale 1ns / 1ps
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// ============================================================================
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// xfft_32.v — Synthesis stub for Xilinx 32-point FFT IP core
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// ============================================================================
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// This is a PLACEHOLDER module that provides the port interface expected by
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// doppler_processor.v. It does NOT perform an actual FFT — it simply passes
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// input data through with a one-cycle latency and generates proper AXI-Stream
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// handshake signals.
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//
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// For real hardware, replace this stub with either:
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// (a) A Xilinx FFT IP core generated via Vivado IP Catalog, or
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// (b) A custom synthesizable radix-2 DIT 32-point FFT in Verilog.
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//
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// Port interface matches the Xilinx LogiCORE IP Fast Fourier Transform
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// (AXI-Stream variant) as instantiated in doppler_processor.v.
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// ============================================================================
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module xfft_32 (
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input wire aclk,
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input wire aresetn,
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// Configuration channel (AXI-Stream slave)
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input wire [7:0] s_axis_config_tdata,
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input wire s_axis_config_tvalid,
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output wire s_axis_config_tready,
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// Data input channel (AXI-Stream slave)
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input wire [31:0] s_axis_data_tdata,
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input wire s_axis_data_tvalid,
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input wire s_axis_data_tlast,
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// Data output channel (AXI-Stream master)
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output wire [31:0] m_axis_data_tdata,
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output wire m_axis_data_tvalid,
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output wire m_axis_data_tlast,
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input wire m_axis_data_tready
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);
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// ----------------------------------------------------------------------------
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// Synthesis stub: pass-through with one-cycle latency
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// ----------------------------------------------------------------------------
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// This gives Vivado a real module to synthesize so it can check port
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// connectivity, infer timing paths, and estimate utilization. The actual
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// FFT computation is deferred to IP integration or a custom RTL FFT.
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// ----------------------------------------------------------------------------
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// Always accept config
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assign s_axis_config_tready = 1'b1;
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// Pipeline registers for data pass-through
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reg [31:0] data_reg;
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reg valid_reg;
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reg last_reg;
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always @(posedge aclk) begin
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if (!aresetn) begin
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data_reg <= 32'd0;
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valid_reg <= 1'b0;
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last_reg <= 1'b0;
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end else begin
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data_reg <= s_axis_data_tdata;
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valid_reg <= s_axis_data_tvalid;
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last_reg <= s_axis_data_tlast;
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end
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end
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assign m_axis_data_tdata = data_reg;
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assign m_axis_data_tvalid = valid_reg;
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assign m_axis_data_tlast = last_reg;
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endmodule
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