Jason
ffed7c1623
Resolve all 4 inter-clock timing violations found in Vivado synthesis attempt #11 (WNS was -2.552 ns). Changes: - Add reset synchronizer for clk_120m_dac domain (2-FF chain) - Add Gray-code CDC for chirp_counter (6-bit, 120MHz->100MHz) - Add single-bit CDC for new_chirp_frame (3-stage, 120MHz->100MHz) - Add 2-stage input synchronizers for valid signals in USB module (clk_100m->ft601_clk_in) with data capture on rising edge - Fix ft601_clk_out multi-driven net (removed duplicate assignment) - Update XDC: set_max_delay -datapath_only for CDC, false_path for reset Result: Vivado attempt #12 passes with 0 errors, 0 timing violations, and 'All user specified timing constraints are met.' (WNS +0.983 ns)
235 lines
8.9 KiB
Verilog
235 lines
8.9 KiB
Verilog
module usb_data_interface (
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input wire clk, // Main clock (100MHz recommended)
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input wire reset_n,
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// Radar data inputs
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input wire [31:0] range_profile,
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input wire range_valid,
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input wire [15:0] doppler_real,
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input wire [15:0] doppler_imag,
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input wire doppler_valid,
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input wire cfar_detection,
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input wire cfar_valid,
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// FT601 Interface (Slave FIFO mode)
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// Data bus
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inout wire [31:0] ft601_data, // 32-bit bidirectional data bus
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output reg [1:0] ft601_be, // Byte enable (for 32-bit mode)
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// Control signals
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output reg ft601_txe_n, // Transmit enable (active low)
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output reg ft601_rxf_n, // Receive enable (active low)
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input wire ft601_txe, // Transmit FIFO empty
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input wire ft601_rxf, // Receive FIFO full
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output reg ft601_wr_n, // Write strobe (active low)
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output reg ft601_rd_n, // Read strobe (active low)
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output reg ft601_oe_n, // Output enable (active low)
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output reg ft601_siwu_n, // Send immediate / Wakeup
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// FIFO flags
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input wire [1:0] ft601_srb, // Selected read buffer
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input wire [1:0] ft601_swb, // Selected write buffer
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// Clock
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output reg ft601_clk_out, // Output clock to FT601 (optional)
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input wire ft601_clk_in // Clock from FT601 (60/100MHz)
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);
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// USB packet structure (same as before)
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localparam HEADER = 8'hAA;
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localparam FOOTER = 8'h55;
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// FT601 configuration
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localparam FT601_DATA_WIDTH = 32;
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localparam FT601_BURST_SIZE = 512; // Max burst size in bytes
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// State definitions (Verilog-2001 compatible)
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localparam [2:0] IDLE = 3'd0,
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SEND_HEADER = 3'd1,
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SEND_RANGE_DATA = 3'd2,
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SEND_DOPPLER_DATA = 3'd3,
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SEND_DETECTION_DATA = 3'd4,
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SEND_FOOTER = 3'd5,
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WAIT_ACK = 3'd6;
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reg [2:0] current_state;
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reg [7:0] byte_counter;
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reg [31:0] data_buffer;
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reg [31:0] ft601_data_out;
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reg ft601_data_oe; // Output enable for bidirectional data bus
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// ========== CDC INPUT SYNCHRONIZERS (clk domain -> ft601_clk_in domain) ==========
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// The valid signals arrive from clk_100m but the state machine runs on ft601_clk_in.
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// Even though both are 100 MHz, they are asynchronous clocks and need synchronization.
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// 2-stage synchronizers for valid signals
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reg [1:0] range_valid_sync;
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reg [1:0] doppler_valid_sync;
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reg [1:0] cfar_valid_sync;
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// Synchronized data captures (registered in ft601_clk_in domain)
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reg [31:0] range_profile_cap;
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reg [15:0] doppler_real_cap;
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reg [15:0] doppler_imag_cap;
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reg cfar_detection_cap;
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wire range_valid_ft;
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wire doppler_valid_ft;
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wire cfar_valid_ft;
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always @(posedge ft601_clk_in or negedge reset_n) begin
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if (!reset_n) begin
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range_valid_sync <= 2'b00;
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doppler_valid_sync <= 2'b00;
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cfar_valid_sync <= 2'b00;
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range_profile_cap <= 32'd0;
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doppler_real_cap <= 16'd0;
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doppler_imag_cap <= 16'd0;
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cfar_detection_cap <= 1'b0;
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end else begin
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// Synchronize valid strobes
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range_valid_sync <= {range_valid_sync[0], range_valid};
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doppler_valid_sync <= {doppler_valid_sync[0], doppler_valid};
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cfar_valid_sync <= {cfar_valid_sync[0], cfar_valid};
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// Capture data on rising edge of synchronized valid
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if (range_valid_sync[0] && !range_valid_sync[1])
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range_profile_cap <= range_profile;
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if (doppler_valid_sync[0] && !doppler_valid_sync[1]) begin
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doppler_real_cap <= doppler_real;
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doppler_imag_cap <= doppler_imag;
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end
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if (cfar_valid_sync[0] && !cfar_valid_sync[1])
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cfar_detection_cap <= cfar_detection;
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end
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end
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// Rising-edge detect on synchronized valid (pulse in ft601_clk_in domain)
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assign range_valid_ft = range_valid_sync[0] && !range_valid_sync[1];
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assign doppler_valid_ft = doppler_valid_sync[0] && !doppler_valid_sync[1];
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assign cfar_valid_ft = cfar_valid_sync[0] && !cfar_valid_sync[1];
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// FT601 data bus direction control
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assign ft601_data = ft601_data_oe ? ft601_data_out : 32'hzzzz_zzzz;
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always @(posedge ft601_clk_in or negedge reset_n) begin
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if (!reset_n) begin
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current_state <= IDLE;
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byte_counter <= 0;
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ft601_data_out <= 0;
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ft601_data_oe <= 0;
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ft601_be <= 2'b11; // Both bytes enabled for 32-bit mode
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ft601_txe_n <= 1;
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ft601_rxf_n <= 1;
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ft601_wr_n <= 1;
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ft601_rd_n <= 1;
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ft601_oe_n <= 1;
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ft601_siwu_n <= 1;
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// NOTE: ft601_clk_out is driven by the clk-domain always block below.
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// Do NOT assign it here (ft601_clk_in domain) — causes multi-driven net.
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end else begin
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case (current_state)
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IDLE: begin
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ft601_wr_n <= 1;
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ft601_data_oe <= 0; // Release data bus
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if (range_valid_ft || doppler_valid_ft || cfar_valid_ft) begin
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current_state <= SEND_HEADER;
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byte_counter <= 0;
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end
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end
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SEND_HEADER: begin
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if (!ft601_txe) begin // FT601 TX FIFO not empty
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ft601_data_oe <= 1;
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ft601_data_out <= {24'b0, HEADER};
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ft601_be <= 2'b01; // Only lower byte valid
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ft601_wr_n <= 0; // Assert write strobe
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current_state <= SEND_RANGE_DATA;
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end
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end
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SEND_RANGE_DATA: begin
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if (!ft601_txe) begin
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ft601_data_oe <= 1;
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ft601_be <= 2'b11; // All bytes valid for 32-bit word
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case (byte_counter)
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0: ft601_data_out <= range_profile_cap;
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1: ft601_data_out <= {range_profile_cap[23:0], 8'h00};
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2: ft601_data_out <= {range_profile_cap[15:0], 16'h0000};
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3: ft601_data_out <= {range_profile_cap[7:0], 24'h000000};
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endcase
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ft601_wr_n <= 0;
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if (byte_counter == 3) begin
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byte_counter <= 0;
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current_state <= SEND_DOPPLER_DATA;
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end else begin
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byte_counter <= byte_counter + 1;
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end
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end
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end
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SEND_DOPPLER_DATA: begin
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if (!ft601_txe && doppler_valid_ft) begin
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ft601_data_oe <= 1;
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ft601_be <= 2'b11;
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case (byte_counter)
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0: ft601_data_out <= {doppler_real_cap, doppler_imag_cap};
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1: ft601_data_out <= {doppler_imag_cap, doppler_real_cap[15:8], 8'h00};
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2: ft601_data_out <= {doppler_real_cap[7:0], doppler_imag_cap[15:8], 16'h0000};
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3: ft601_data_out <= {doppler_imag_cap[7:0], 24'h000000};
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endcase
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ft601_wr_n <= 0;
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if (byte_counter == 3) begin
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byte_counter <= 0;
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current_state <= SEND_DETECTION_DATA;
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end else begin
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byte_counter <= byte_counter + 1;
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end
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end
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end
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SEND_DETECTION_DATA: begin
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if (!ft601_txe && cfar_valid_ft) begin
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ft601_data_oe <= 1;
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ft601_be <= 2'b01;
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ft601_data_out <= {24'b0, 7'b0, cfar_detection_cap};
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ft601_wr_n <= 0;
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current_state <= SEND_FOOTER;
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end
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end
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SEND_FOOTER: begin
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if (!ft601_txe) begin
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ft601_data_oe <= 1;
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ft601_be <= 2'b01;
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ft601_data_out <= {24'b0, FOOTER};
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ft601_wr_n <= 0;
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current_state <= WAIT_ACK;
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end
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end
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WAIT_ACK: begin
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ft601_wr_n <= 1;
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ft601_data_oe <= 0; // Release data bus
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current_state <= IDLE;
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end
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endcase
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end
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end
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// Generate clock for FT601 if needed (optional)
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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ft601_clk_out <= 0;
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end else begin
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ft601_clk_out <= ~ft601_clk_out; // Divide by 2 from main clock
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end
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end
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endmodule |