Jason
c983a3c705
Phase 0+ timing optimization (attempts #13-22 + implementation): NCO (nco_400m_enhanced.v): - 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX - DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain) - Registered phase_inc_dithered to break cascaded 32-bit add path DDC (ddc_400m.v): - Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1) - CEP=1, RSTP=!reset_n for proper pipeline control - 3-stage dsp_valid_pipe for PREG=1 latency - Behavioral sim model under ifdef SIMULATION for Icarus compatibility CIC (cic_decimator_4x_enhanced.v): - 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28 - Removed integrator/comb saturation (CIC uses wrapping arithmetic by design) - Pipelined output saturation comparison CDC/ASYNC_REG: - ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v, radar_system_top.v, usb_data_interface.v) - Sync reset in generate blocks (cdc_modules.v) Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints, 850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t. All testbenches pass: 241/244 (3 known stub failures).
237 lines
7.4 KiB
Verilog
237 lines
7.4 KiB
Verilog
`timescale 1ns / 1ps
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// ============================================================================
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// CDC FOR MULTI-BIT DATA (ADVANCED)
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// Uses Gray-code encoding with synchronous reset on sync chain to avoid
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// latch inference. ASYNC_REG attributes ensure Vivado places synchronizer
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// FFs in the same slice for optimal MTBF.
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// ============================================================================
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module cdc_adc_to_processing #(
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parameter WIDTH = 8,
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parameter STAGES = 3
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)(
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input wire src_clk,
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input wire dst_clk,
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input wire reset_n,
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input wire [WIDTH-1:0] src_data,
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input wire src_valid,
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output wire [WIDTH-1:0] dst_data,
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output wire dst_valid
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);
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// Gray encoding for safe CDC
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function [WIDTH-1:0] binary_to_gray;
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input [WIDTH-1:0] binary;
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binary_to_gray = binary ^ (binary >> 1);
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endfunction
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function [WIDTH-1:0] gray_to_binary;
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input [WIDTH-1:0] gray;
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reg [WIDTH-1:0] binary;
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integer i;
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begin
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binary[WIDTH-1] = gray[WIDTH-1];
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for (i = WIDTH-2; i >= 0; i = i - 1) begin
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binary[i] = binary[i+1] ^ gray[i];
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end
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gray_to_binary = binary;
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end
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endfunction
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// Source domain registers
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reg [WIDTH-1:0] src_data_reg;
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reg [1:0] src_toggle = 2'b00;
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// Destination domain synchronizer registers
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// ASYNC_REG on memory arrays applies to all elements
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(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] dst_data_gray [0:STAGES-1];
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(* ASYNC_REG = "TRUE" *) reg [1:0] dst_toggle_sync [0:STAGES-1];
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reg [WIDTH-1:0] dst_data_reg;
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reg dst_valid_reg = 0;
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reg [1:0] prev_dst_toggle = 2'b00;
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// Source domain: capture data and toggle
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always @(posedge src_clk or negedge reset_n) begin
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if (!reset_n) begin
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src_data_reg <= 0;
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src_toggle <= 2'b00;
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end else if (src_valid) begin
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src_data_reg <= src_data;
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src_toggle <= src_toggle + 1;
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end
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end
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// CDC synchronization chain for data — SYNCHRONOUS RESET
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// Using synchronous reset avoids latch inference in Vivado.
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// For CDC synchronizers, synchronous reset is preferred because
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// the reset value is sampled safely within the clock domain.
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genvar i;
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generate
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for (i = 0; i < STAGES; i = i + 1) begin : data_sync_chain
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always @(posedge dst_clk) begin
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if (!reset_n) begin
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dst_data_gray[i] <= 0;
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end else begin
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if (i == 0) begin
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// Convert to gray code at domain crossing
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dst_data_gray[i] <= binary_to_gray(src_data_reg);
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end else begin
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dst_data_gray[i] <= dst_data_gray[i-1];
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end
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end
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end
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end
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for (i = 0; i < STAGES; i = i + 1) begin : toggle_sync_chain
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always @(posedge dst_clk) begin
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if (!reset_n) begin
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dst_toggle_sync[i] <= 2'b00;
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end else begin
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if (i == 0) begin
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dst_toggle_sync[i] <= src_toggle;
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end else begin
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dst_toggle_sync[i] <= dst_toggle_sync[i-1];
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end
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end
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end
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end
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endgenerate
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// Detect new data
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always @(posedge dst_clk or negedge reset_n) begin
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if (!reset_n) begin
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dst_data_reg <= 0;
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dst_valid_reg <= 0;
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prev_dst_toggle <= 2'b00;
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end else begin
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// Convert from gray code
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dst_data_reg <= gray_to_binary(dst_data_gray[STAGES-1]);
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// Check if toggle changed (new data)
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if (dst_toggle_sync[STAGES-1] != prev_dst_toggle) begin
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dst_valid_reg <= 1'b1;
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prev_dst_toggle <= dst_toggle_sync[STAGES-1];
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end else begin
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dst_valid_reg <= 1'b0;
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end
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end
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end
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assign dst_data = dst_data_reg;
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assign dst_valid = dst_valid_reg;
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endmodule
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// ============================================================================
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// CDC FOR SINGLE BIT SIGNALS
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// ============================================================================
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module cdc_single_bit #(
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parameter STAGES = 3
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)(
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input wire src_clk,
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input wire dst_clk,
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input wire reset_n,
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input wire src_signal,
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output wire dst_signal
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);
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(* ASYNC_REG = "TRUE" *) reg [STAGES-1:0] sync_chain;
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always @(posedge dst_clk or negedge reset_n) begin
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if (!reset_n) begin
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sync_chain <= 0;
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end else begin
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sync_chain <= {sync_chain[STAGES-2:0], src_signal};
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end
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end
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assign dst_signal = sync_chain[STAGES-1];
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endmodule
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// ============================================================================
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// CDC FOR MULTI-BIT WITH HANDSHAKE
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// ============================================================================
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module cdc_handshake #(
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parameter WIDTH = 32
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)(
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input wire src_clk,
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input wire dst_clk,
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input wire reset_n,
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input wire [WIDTH-1:0] src_data,
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input wire src_valid,
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output wire src_ready,
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output wire [WIDTH-1:0] dst_data,
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output wire dst_valid,
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input wire dst_ready
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);
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// Source domain
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reg [WIDTH-1:0] src_data_reg;
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reg src_busy = 0;
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reg src_ack_sync = 0;
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(* ASYNC_REG = "TRUE" *) reg [1:0] src_ack_sync_chain = 2'b00;
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// Destination domain
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reg [WIDTH-1:0] dst_data_reg;
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reg dst_valid_reg = 0;
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reg dst_req_sync = 0;
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(* ASYNC_REG = "TRUE" *) reg [1:0] dst_req_sync_chain = 2'b00;
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reg dst_ack = 0;
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// Source clock domain
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always @(posedge src_clk or negedge reset_n) begin
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if (!reset_n) begin
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src_data_reg <= 0;
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src_busy <= 0;
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src_ack_sync <= 0;
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src_ack_sync_chain <= 2'b00;
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end else begin
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// Sync acknowledge from destination
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src_ack_sync_chain <= {src_ack_sync_chain[0], dst_ack};
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src_ack_sync <= src_ack_sync_chain[1];
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if (!src_busy && src_valid) begin
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src_data_reg <= src_data;
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src_busy <= 1'b1;
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end else if (src_busy && src_ack_sync) begin
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src_busy <= 1'b0;
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end
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end
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end
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// Destination clock domain
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always @(posedge dst_clk or negedge reset_n) begin
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if (!reset_n) begin
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dst_data_reg <= 0;
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dst_valid_reg <= 0;
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dst_req_sync <= 0;
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dst_req_sync_chain <= 2'b00;
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dst_ack <= 0;
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end else begin
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// Sync request from source
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dst_req_sync_chain <= {dst_req_sync_chain[0], src_busy};
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dst_req_sync <= dst_req_sync_chain[1];
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// Capture data when request arrives
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if (dst_req_sync && !dst_valid_reg) begin
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dst_data_reg <= src_data_reg;
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dst_valid_reg <= 1'b1;
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dst_ack <= 1'b1;
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end else if (dst_valid_reg && dst_ready) begin
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dst_valid_reg <= 1'b0;
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end
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// Clear acknowledge after source sees it
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if (dst_ack && !dst_req_sync) begin
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dst_ack <= 1'b0;
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end
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end
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end
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assign src_ready = !src_busy;
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assign dst_data = dst_data_reg;
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assign dst_valid = dst_valid_reg;
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endmodule
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