FlintyLemming/PLFM_RADAR
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eefaf94e9e062752370601b977f43147776ac061
PLFM_RADAR/9_Firmware/9_2_FPGA
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Jason eefaf94e9e Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis 
Resolves all synthesis errors across attempts 3-11, achieving clean
Vivado 2025.2 synthesis on XC7A100T (0 errors, 831 LUTs, 320 FFs, 2 DSPs).

radar_receiver_final.v:
- reg clk_400m -> wire; output reg -> output wire (x4)
- Replace ad9484_lvds_to_cmos_400m with ad9484_interface_400m
- Remove duplicate IBUFDS lvds_to_cmos_400m instantiation
- Remove non-existent ref_i/ref_q port connections on matched filter
- Connect adc_dco_bufg as 400MHz clock source

ad9484_interface_400m.v:
- Add adc_dco_bufg output port with BUFG instance
- Route all internal logic through buffered DCO clock

cic_decimator_4x_enhanced.v:
- Move reset_monitors handling inside else branch (fixes Vivado
  ambiguous clock error in both integrator and comb always blocks)
- Add separate comb_overflow_latched/comb_saturation_detected regs
  to eliminate multi-driven nets between integrator and comb blocks
- Remove standalone always @(posedge reset_monitors) block
- Add output_counter to async reset branch

matched_filter_processing_chain.v:
- Wrap behavioral FFT body (uses $cos/$sin/$rtoi) in ifdef SIMULATION
- Add synthesis stub tying outputs to safe defaults

chirp_memory_loader_param.v:
- Replace hardcoded Windows paths with relative filenames for all
  10 $readmem default parameters

latency_buffer_2159.v:
- Split single always block into separate BRAM write (synchronous
  only) and control logic (with async reset) blocks
- Fixes Vivado Synth 8-3391: BRAM cannot infer with async reset

xfft_32.v (NEW):
- Synthesis stub for Xilinx 32-point FFT IP core
- AXI-Stream interface with pass-through and 1-cycle latency
- Placeholder until real xfft IP is generated
2026-03-15 17:37:59 +02:00
..
tb
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
ad9484_interface_400m.v
Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis
2026-03-15 17:37:59 +02:00
cdc_modules.v
Add files via upload
2026-03-09 00:17:39 +00:00
chirp_lut_init.v
Add files via upload
2026-03-09 00:17:39 +00:00
chirp_memory_loader_param.v
Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis
2026-03-15 17:37:59 +02:00
cic_decimator_4x_enhanced.v
Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis
2026-03-15 17:37:59 +02:00
cntrt.xdc
Create cntrt.xdc
2026-03-10 02:42:15 +00:00
dac_interface_single.v
Add files via upload
2026-03-09 00:17:39 +00:00
ddc_400m.v
Fix synthesis blockers in 9 RTL files for Vivado compatibility
2026-03-15 14:53:35 +02:00
ddc_input_interface.v
Add files via upload
2026-03-09 00:17:39 +00:00
doppler_processor.v
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2026-03-09 00:17:39 +00:00
edge_detector.v
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2026-03-09 00:17:39 +00:00
fft_1024_forward.v
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2026-03-09 00:17:39 +00:00
fft_1024_inverse.v
Fix synthesis blockers in 9 RTL files for Vivado compatibility
2026-03-15 14:53:35 +02:00
fir_lowpass.v
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2026-03-09 00:17:39 +00:00
frequency_matched_filter.v
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2026-03-09 00:17:39 +00:00
latency_buffer_2159.v
Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis
2026-03-15 17:37:59 +02:00
level_shifter_interface.v
Add files via upload
2026-03-10 01:31:50 +00:00
long_chirp_seg0_i.mem
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2026-03-09 00:17:39 +00:00
long_chirp_seg0_q.mem
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2026-03-09 00:17:39 +00:00
long_chirp_seg1_i.mem
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2026-03-09 00:17:39 +00:00
long_chirp_seg1_q.mem
Add files via upload
2026-03-09 00:17:39 +00:00
long_chirp_seg2_i.mem
Add files via upload
2026-03-09 00:17:39 +00:00
long_chirp_seg2_q.mem
Add files via upload
2026-03-09 00:17:39 +00:00
lvds_to_cmos_400m.v
Add files via upload
2026-03-09 00:17:39 +00:00
matched_filter_multi_segment.v
Fix synthesis blockers in 9 RTL files for Vivado compatibility
2026-03-15 14:53:35 +02:00
matched_filter_processing_chain.v
Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis
2026-03-15 17:37:59 +02:00
nco_400m_enhanced.v
Fix synthesis blockers in 9 RTL files for Vivado compatibility
2026-03-15 14:53:35 +02:00
plfm_chirp_controller.v
Fix 6 RTL bugs in FPGA signal processing chain
2026-03-15 06:14:04 +02:00
radar_mode_controller.v
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
radar_receiver_final.v
Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis
2026-03-15 17:37:59 +02:00
radar_system_tb.v
Create radar_system_tb.v
2026-03-10 01:35:26 +00:00
radar_system_top.v
Fix 6 RTL bugs in FPGA signal processing chain
2026-03-15 06:14:04 +02:00
radar_transmitter.v
Add files via upload
2026-03-09 00:17:39 +00:00
range_bin_decimator.v
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
short_chirp_i.mem
Add files via upload
2026-03-09 00:17:39 +00:00
short_chirp_q.mem
Add files via upload
2026-03-09 00:17:39 +00:00
usb_data_interface.v
Fix synthesis blockers in 9 RTL files for Vivado compatibility
2026-03-15 14:53:35 +02:00
usb_packet_analyzer.v
Fix synthesis blockers in 9 RTL files for Vivado compatibility
2026-03-15 14:53:35 +02:00
xfft_32.v
Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis
2026-03-15 17:37:59 +02:00