Jason
49c9aa28ad
Bug #11: platform_noos_stm32.c used HAL_SPI_Transmit instead of HAL_SPI_TransmitReceive — reads returned garbage. Changed to in-place full-duplex. Dead code (never called), fixed per audit recommendation. Test added: test_bug11_platform_spi_transmit_only.c. Mock infrastructure updated with SPI spy types. All 11 firmware tests pass. FPGA B2: Migrated long_chirp_lut[0:3599] from ~700 lines of hardcoded assignments to BRAM with (* ram_style = "block" *) attribute and $readmemh("long_chirp_lut.mem"). Added sync-only read block for proper BRAM inference. 1-cycle read latency introduced. short_chirp_lut left as distributed RAM (60 entries, too small for BRAM). FPGA B3: Added BREG (window_val_reg) and MREG (mult_i_raw/mult_q_raw) pipeline stages to doppler_processor.v. Eliminates DPIP-1 and DPOP-2 DRC warnings. S_LOAD_FFT retimed: fft_input_valid starts at sub=2, +1 cycle total latency. BREG primed in S_PRE_READ at no extra cost. Both FPGA files compile clean with Icarus Verilog.
521 lines
21 KiB
Verilog
521 lines
21 KiB
Verilog
`timescale 1ns / 1ps
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module doppler_processor_optimized #(
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parameter DOPPLER_FFT_SIZE = 32,
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parameter RANGE_BINS = 64,
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parameter CHIRPS_PER_FRAME = 32,
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parameter WINDOW_TYPE = 0, // 0=Hamming, 1=Rectangular
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parameter DATA_WIDTH = 16
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)(
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input wire clk,
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input wire reset_n,
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input wire [31:0] range_data,
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input wire data_valid,
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input wire new_chirp_frame,
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output reg [31:0] doppler_output,
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output reg doppler_valid,
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output reg [4:0] doppler_bin,
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output reg [5:0] range_bin,
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output wire processing_active,
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output wire frame_complete,
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output reg [3:0] status
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`ifdef FORMAL
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,
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output wire [2:0] fv_state,
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output wire [10:0] fv_mem_write_addr,
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output wire [10:0] fv_mem_read_addr,
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output wire [5:0] fv_write_range_bin,
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output wire [4:0] fv_write_chirp_index,
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output wire [5:0] fv_read_range_bin,
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output wire [4:0] fv_read_doppler_index,
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output wire [9:0] fv_processing_timeout,
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output wire fv_frame_buffer_full,
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output wire fv_mem_we,
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output wire [10:0] fv_mem_waddr_r
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`endif
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);
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// ==============================================
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// Window Coefficients (Simple Implementation)
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// ==============================================
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reg [DATA_WIDTH-1:0] window_coeff [0:31];
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// Generate window coefficients
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integer w;
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initial begin
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if (WINDOW_TYPE == 0) begin
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// Pre-calculated Hamming window (Q15 format)
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window_coeff[0] = 16'h0800; window_coeff[1] = 16'h0862;
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window_coeff[2] = 16'h09CB; window_coeff[3] = 16'h0C3B;
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window_coeff[4] = 16'h0FB2; window_coeff[5] = 16'h142F;
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window_coeff[6] = 16'h19B2; window_coeff[7] = 16'h2039;
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window_coeff[8] = 16'h27C4; window_coeff[9] = 16'h3050;
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window_coeff[10] = 16'h39DB; window_coeff[11] = 16'h4462;
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window_coeff[12] = 16'h4FE3; window_coeff[13] = 16'h5C5A;
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window_coeff[14] = 16'h69C4; window_coeff[15] = 16'h781D;
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window_coeff[16] = 16'h7FFF; // Peak
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window_coeff[17] = 16'h781D; window_coeff[18] = 16'h69C4;
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window_coeff[19] = 16'h5C5A; window_coeff[20] = 16'h4FE3;
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window_coeff[21] = 16'h4462; window_coeff[22] = 16'h39DB;
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window_coeff[23] = 16'h3050; window_coeff[24] = 16'h27C4;
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window_coeff[25] = 16'h2039; window_coeff[26] = 16'h19B2;
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window_coeff[27] = 16'h142F; window_coeff[28] = 16'h0FB2;
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window_coeff[29] = 16'h0C3B; window_coeff[30] = 16'h09CB;
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window_coeff[31] = 16'h0862;
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end else begin
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// Rectangular window (all ones)
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for (w = 0; w < 32; w = w + 1) begin
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window_coeff[w] = 16'h7FFF;
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end
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end
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end
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// ==============================================
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// Memory Declaration - FIXED SIZE
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// ==============================================
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localparam MEM_DEPTH = RANGE_BINS * CHIRPS_PER_FRAME;
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(* ram_style = "block" *) reg [DATA_WIDTH-1:0] doppler_i_mem [0:MEM_DEPTH-1];
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(* ram_style = "block" *) reg [DATA_WIDTH-1:0] doppler_q_mem [0:MEM_DEPTH-1];
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// ==============================================
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// Control Registers
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// ==============================================
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reg [5:0] write_range_bin; // Changed to match RANGE_BINS width
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reg [4:0] write_chirp_index; // Changed to match CHIRPS_PER_FRAME width
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reg [5:0] read_range_bin;
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reg [4:0] read_doppler_index; // Changed name for clarity
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reg frame_buffer_full;
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reg [9:0] chirps_received; // Enough for up to 1024 chirps
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reg [1:0] chirp_state; // Track chirp accumulation state
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// ==============================================
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// FFT Interface
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// ==============================================
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reg fft_start;
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wire fft_ready;
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reg [DATA_WIDTH-1:0] fft_input_i;
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reg [DATA_WIDTH-1:0] fft_input_q;
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reg signed [31:0] mult_i, mult_q; // 32-bit to avoid overflow
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reg signed [DATA_WIDTH-1:0] window_val_reg; // BREG pipeline stage
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reg signed [31:0] mult_i_raw, mult_q_raw; // MREG pipeline stage
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reg fft_input_valid;
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reg fft_input_last;
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wire [DATA_WIDTH-1:0] fft_output_i;
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wire [DATA_WIDTH-1:0] fft_output_q;
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wire fft_output_valid;
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wire fft_output_last;
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// ==============================================
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// Addressing
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// ==============================================
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wire [10:0] mem_write_addr;
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wire [10:0] mem_read_addr;
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// Proper address calculation using parameters
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assign mem_write_addr = (write_chirp_index * RANGE_BINS) + write_range_bin;
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assign mem_read_addr = (read_doppler_index * RANGE_BINS) + read_range_bin;
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// Alternative organization (choose one):
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// If you want range-major organization (all chirps for one range bin together):
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// assign mem_write_addr = (write_range_bin * CHIRPS_PER_FRAME) + write_chirp_index;
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// assign mem_read_addr = (read_range_bin * CHIRPS_PER_FRAME) + read_doppler_index;
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// ==============================================
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// State Machine
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// ==============================================
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reg [2:0] state;
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localparam S_IDLE = 3'b000;
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localparam S_ACCUMULATE = 3'b001;
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localparam S_PRE_READ = 3'b101; // Prime BRAM pipeline before FFT load
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localparam S_LOAD_FFT = 3'b010;
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localparam S_FFT_WAIT = 3'b011;
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localparam S_OUTPUT = 3'b100;
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// Frame sync detection
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reg new_chirp_frame_d1;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) new_chirp_frame_d1 <= 0;
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else new_chirp_frame_d1 <= new_chirp_frame;
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end
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wire frame_start_pulse = new_chirp_frame & ~new_chirp_frame_d1;
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// ==============================================
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// Main State Machine - FIXED
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// ==============================================
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reg [5:0] fft_sample_counter;
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reg [9:0] processing_timeout;
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// Memory write enable and data signals (extracted for BRAM inference)
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reg mem_we;
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reg [10:0] mem_waddr_r;
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reg [DATA_WIDTH-1:0] mem_wdata_i, mem_wdata_q;
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// Memory read data (registered for BRAM read latency)
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reg [DATA_WIDTH-1:0] mem_rdata_i, mem_rdata_q;
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`ifdef FORMAL
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assign fv_state = state;
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assign fv_mem_write_addr = mem_write_addr;
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assign fv_mem_read_addr = mem_read_addr;
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assign fv_write_range_bin = write_range_bin;
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assign fv_write_chirp_index = write_chirp_index;
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assign fv_read_range_bin = read_range_bin;
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assign fv_read_doppler_index = read_doppler_index;
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assign fv_processing_timeout = processing_timeout;
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assign fv_frame_buffer_full = frame_buffer_full;
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assign fv_mem_we = mem_we;
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assign fv_mem_waddr_r = mem_waddr_r;
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`endif
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// ----------------------------------------------------------
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// Separate always block for memory writes — NO async reset
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// in sensitivity list, so Vivado can infer Block RAM.
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// ----------------------------------------------------------
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always @(posedge clk) begin
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if (mem_we) begin
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doppler_i_mem[mem_waddr_r] <= mem_wdata_i;
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doppler_q_mem[mem_waddr_r] <= mem_wdata_q;
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end
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// Registered read — address driven by mem_read_addr from FSM
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mem_rdata_i <= doppler_i_mem[mem_read_addr];
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mem_rdata_q <= doppler_q_mem[mem_read_addr];
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end
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// ----------------------------------------------------------
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// Block 1: FSM / Control — async reset (posedge clk or negedge reset_n).
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// Only state-machine and control registers live here.
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// BRAM-driving and DSP datapath registers are intentionally
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// excluded to avoid Vivado REQP-1839 (async-reset on BRAM
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// address) and DPOR-1/DPIP-1 (async-reset blocking DSP48
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// absorption) DRC warnings.
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// ----------------------------------------------------------
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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state <= S_IDLE;
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write_range_bin <= 0;
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write_chirp_index <= 0;
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// read_range_bin, read_doppler_index moved to Block 2 (sync reset)
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// to enable BRAM address register absorption (REQP-1839 fix)
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frame_buffer_full <= 0;
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doppler_valid <= 0;
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fft_start <= 0;
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fft_input_valid <= 0;
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fft_input_last <= 0;
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fft_sample_counter <= 0;
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processing_timeout <= 0;
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status <= 0;
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chirps_received <= 0;
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chirp_state <= 0;
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doppler_output <= 0;
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doppler_bin <= 0;
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range_bin <= 0;
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end else begin
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doppler_valid <= 0;
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fft_input_valid <= 0;
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fft_input_last <= 0;
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if (processing_timeout > 0) begin
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processing_timeout <= processing_timeout - 1;
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end
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case (state)
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S_IDLE: begin
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if (frame_start_pulse) begin
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// Start new frame
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write_chirp_index <= 0;
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write_range_bin <= 0;
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frame_buffer_full <= 0;
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chirps_received <= 0;
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end
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if (data_valid && !frame_buffer_full) begin
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state <= S_ACCUMULATE;
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write_range_bin <= 1;
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end
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end
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S_ACCUMULATE: begin
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if (data_valid) begin
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// Increment range bin
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if (write_range_bin < RANGE_BINS - 1) begin
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write_range_bin <= write_range_bin + 1;
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end else begin
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// Completed one chirp
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write_range_bin <= 0;
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write_chirp_index <= write_chirp_index + 1;
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chirps_received <= chirps_received + 1;
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// Check if frame is complete
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if (write_chirp_index >= CHIRPS_PER_FRAME - 1) begin
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frame_buffer_full <= 1;
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chirp_state <= 0;
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state <= S_PRE_READ;
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// read_range_bin/read_doppler_index zeroed in Block 2
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fft_sample_counter <= 0;
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// Reset write pointers — no longer needed for
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// this frame, and prevents stale overflow of
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// write_chirp_index (which was just incremented
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// past CHIRPS_PER_FRAME-1 above).
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write_chirp_index <= 0;
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write_range_bin <= 0;
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end
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end
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end
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end
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S_PRE_READ: begin
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// Prime the BRAM pipeline: present addr for chirp 0 of
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// current read_range_bin. read_doppler_index is already 0.
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// mem_read_addr = 0 * RANGE_BINS + read_range_bin.
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// After this cycle, mem_rdata_i will hold data[chirp=0][rbin].
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// Advance read_doppler_index to 1 so the NEXT BRAM read
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// (which happens every cycle in the memory block) will
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// fetch chirp 1.
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// read_doppler_index <= 1 moved to Block 2
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fft_start <= 1;
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state <= S_LOAD_FFT;
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end
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S_LOAD_FFT: begin
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fft_start <= 0;
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// Pipeline alignment (after S_PRE_READ primed the BRAM
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// and pre-registered window_val_reg = window_coeff[0]):
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//
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// With DSP48 BREG+MREG pipelining, data flows through:
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// sub=0: multiply mem_rdata * window_val_reg -> mult_i_raw
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// pre-register window_coeff[1] into window_val_reg
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// sub=1: MREG capture mult_i_raw -> mult_i (sample 0)
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// new multiply for sample 1
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// sub=2..DOPPLER_FFT_SIZE+1: steady state —
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// fft_input = rounding(mult_i), mult_i = mult_i_raw,
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// mult_i_raw = new multiply, window_val_reg = next coeff
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//
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// fft_input_valid asserted at sub=2..DOPPLER_FFT_SIZE+1
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// fft_input_last asserted at sub=DOPPLER_FFT_SIZE+1
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// read_doppler_index updates moved to Block 2 (sync reset)
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if (fft_sample_counter <= 1) begin
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// Sub 0..1: pipeline priming — no valid FFT data yet
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fft_sample_counter <= fft_sample_counter + 1;
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end else if (fft_sample_counter <= DOPPLER_FFT_SIZE + 1) begin
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// Sub 2..DOPPLER_FFT_SIZE+1: steady state
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// (fft_input_i/fft_input_q captured in Block 2)
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fft_input_valid <= 1;
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if (fft_sample_counter == DOPPLER_FFT_SIZE + 1) begin
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// Last sample: flush
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fft_input_last <= 1;
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state <= S_FFT_WAIT;
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fft_sample_counter <= 0;
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processing_timeout <= 1000;
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end else begin
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fft_sample_counter <= fft_sample_counter + 1;
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end
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end
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end
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S_FFT_WAIT: begin
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if (fft_output_valid) begin
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doppler_output <= {fft_output_q[15:0], fft_output_i[15:0]};
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doppler_bin <= fft_sample_counter;
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range_bin <= read_range_bin;
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doppler_valid <= 1;
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fft_sample_counter <= fft_sample_counter + 1;
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if (fft_output_last) begin
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state <= S_OUTPUT;
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fft_sample_counter <= 0;
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end
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end
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if (processing_timeout == 0) begin
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state <= S_OUTPUT;
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end
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end
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S_OUTPUT: begin
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if (read_range_bin < RANGE_BINS - 1) begin
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// read_range_bin/read_doppler_index updated in Block 2
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fft_sample_counter <= 0;
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state <= S_PRE_READ;
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end else begin
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state <= S_IDLE;
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frame_buffer_full <= 0;
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end
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end
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endcase
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status <= {state, frame_buffer_full};
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end
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end
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// ----------------------------------------------------------
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// Block 2: BRAM address/data & DSP datapath — synchronous reset only.
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// Uses always @(posedge clk) so Vivado can absorb multipliers
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// into DSP48 primitives and does not flag REQP-1839/1840 on
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// BRAM address registers. Replicates the same state/condition
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// structure as Block 1 for the registers:
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// mem_we, mem_waddr_r, mem_wdata_i, mem_wdata_q,
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// mult_i, mult_q, fft_input_i, fft_input_q,
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// read_range_bin, read_doppler_index
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// ----------------------------------------------------------
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always @(posedge clk) begin
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if (!reset_n) begin
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mem_we <= 0;
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mem_waddr_r <= 0;
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mem_wdata_i <= 0;
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mem_wdata_q <= 0;
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mult_i <= 0;
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mult_q <= 0;
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mult_i_raw <= 0;
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mult_q_raw <= 0;
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window_val_reg <= 0;
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fft_input_i <= 0;
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fft_input_q <= 0;
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read_range_bin <= 0;
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read_doppler_index <= 0;
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end else begin
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mem_we <= 0;
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case (state)
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S_IDLE: begin
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if (data_valid && !frame_buffer_full) begin
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// Write the first sample immediately (Bug #3 fix:
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// previously this transition consumed data_valid
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// without writing to BRAM)
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mem_we <= 1;
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mem_waddr_r <= mem_write_addr;
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mem_wdata_i <= range_data[15:0];
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mem_wdata_q <= range_data[31:16];
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end
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end
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S_ACCUMULATE: begin
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if (data_valid) begin
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// Drive memory write signals (actual write in separate block)
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mem_we <= 1;
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mem_waddr_r <= mem_write_addr;
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mem_wdata_i <= range_data[15:0];
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mem_wdata_q <= range_data[31:16];
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// Transition to S_PRE_READ when frame complete
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if (write_range_bin >= RANGE_BINS - 1 &&
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write_chirp_index >= CHIRPS_PER_FRAME - 1) begin
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read_range_bin <= 0;
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read_doppler_index <= 0;
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end
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end
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end
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S_PRE_READ: begin
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// Advance read_doppler_index to 1 so next BRAM read
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// fetches chirp 1
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read_doppler_index <= 1;
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// BREG priming: pre-register window coeff for sample 0
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// so it is ready when S_LOAD_FFT sub=0 performs the multiply
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window_val_reg <= $signed(window_coeff[0]);
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end
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S_LOAD_FFT: begin
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if (fft_sample_counter == 0) begin
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// Pipe stage 1: multiply using pre-registered BREG value
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// mem_rdata_i = data[chirp=0][rbin] (primed by S_PRE_READ)
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mult_i_raw <= $signed(mem_rdata_i) * window_val_reg;
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mult_q_raw <= $signed(mem_rdata_q) * window_val_reg;
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// Pre-register next window coeff (sample 1)
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window_val_reg <= $signed(window_coeff[1]);
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// Present BRAM addr for chirp 2
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read_doppler_index <= (2 < DOPPLER_FFT_SIZE) ? 2
|
|
: DOPPLER_FFT_SIZE - 1;
|
|
end else if (fft_sample_counter == 1) begin
|
|
// Pipe stage 2 (MREG): capture sample 0 multiply result
|
|
mult_i <= mult_i_raw;
|
|
mult_q <= mult_q_raw;
|
|
// Multiply sample 1 using registered window value
|
|
mult_i_raw <= $signed(mem_rdata_i) * window_val_reg;
|
|
mult_q_raw <= $signed(mem_rdata_q) * window_val_reg;
|
|
// Pre-register next window coeff (sample 2)
|
|
if (2 < DOPPLER_FFT_SIZE)
|
|
window_val_reg <= $signed(window_coeff[2]);
|
|
// Advance BRAM read to chirp 3
|
|
if (3 < DOPPLER_FFT_SIZE)
|
|
read_doppler_index <= 3;
|
|
else
|
|
read_doppler_index <= DOPPLER_FFT_SIZE - 1;
|
|
end else if (fft_sample_counter <= DOPPLER_FFT_SIZE + 1) begin
|
|
// Sub 2..DOPPLER_FFT_SIZE+1: steady state
|
|
// Capture rounding into fft_input from MREG output
|
|
fft_input_i <= (mult_i + (1 << 14)) >>> 15;
|
|
fft_input_q <= (mult_q + (1 << 14)) >>> 15;
|
|
// MREG: capture multiply result
|
|
mult_i <= mult_i_raw;
|
|
mult_q <= mult_q_raw;
|
|
|
|
if (fft_sample_counter <= DOPPLER_FFT_SIZE - 1) begin
|
|
// New multiply from current BRAM data
|
|
mult_i_raw <= $signed(mem_rdata_i) * window_val_reg;
|
|
mult_q_raw <= $signed(mem_rdata_q) * window_val_reg;
|
|
// Pre-register next window coeff (clamped)
|
|
if (fft_sample_counter + 1 < DOPPLER_FFT_SIZE)
|
|
window_val_reg <= $signed(window_coeff[fft_sample_counter + 1]);
|
|
// Advance BRAM read
|
|
if (fft_sample_counter + 2 < DOPPLER_FFT_SIZE)
|
|
read_doppler_index <= fft_sample_counter + 2;
|
|
else
|
|
read_doppler_index <= DOPPLER_FFT_SIZE - 1;
|
|
end
|
|
|
|
if (fft_sample_counter == DOPPLER_FFT_SIZE + 1) begin
|
|
// Flush complete — reset read index
|
|
read_doppler_index <= 0;
|
|
end
|
|
end
|
|
end
|
|
|
|
S_OUTPUT: begin
|
|
if (read_range_bin < RANGE_BINS - 1) begin
|
|
read_range_bin <= read_range_bin + 1;
|
|
read_doppler_index <= 0;
|
|
end
|
|
end
|
|
|
|
default: begin
|
|
// S_IDLE, S_FFT_WAIT:
|
|
// no BRAM-write, DSP, or read-address operations needed
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
// ==============================================
|
|
// FFT Module
|
|
// ==============================================
|
|
xfft_32 fft_inst (
|
|
.aclk(clk),
|
|
.aresetn(reset_n),
|
|
.s_axis_config_tdata(8'h01),
|
|
.s_axis_config_tvalid(fft_start),
|
|
.s_axis_config_tready(fft_ready),
|
|
.s_axis_data_tdata({fft_input_q, fft_input_i}),
|
|
.s_axis_data_tvalid(fft_input_valid),
|
|
.s_axis_data_tlast(fft_input_last),
|
|
.m_axis_data_tdata({fft_output_q, fft_output_i}),
|
|
.m_axis_data_tvalid(fft_output_valid),
|
|
.m_axis_data_tlast(fft_output_last),
|
|
.m_axis_data_tready(1'b1)
|
|
);
|
|
|
|
// ==============================================
|
|
// Status Outputs
|
|
// ==============================================
|
|
assign processing_active = (state != S_IDLE);
|
|
assign frame_complete = (state == S_IDLE && frame_buffer_full == 0);
|
|
|
|
|
|
endmodule |