NawfalMotii79
426 lines
13 KiB
Verilog
426 lines
13 KiB
Verilog
`timescale 1ns / 1ps
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module ddc_400m_enhanced (
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input wire clk_400m, // 400MHz clock from ADC DCO
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input wire clk_100m, // 100MHz system clock
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input wire reset_n,
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input wire mixers_enable,
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input wire [7:0] adc_data, // ADC data at 400MHz
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input wire adc_data_valid_i, // Valid at 400MHz
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input wire adc_data_valid_q,
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output wire signed [17:0] baseband_i,
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output wire signed [17:0] baseband_q,
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output wire baseband_valid_i,
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output wire baseband_valid_q,
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output wire [1:0] ddc_status,
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// Enhanced interfaces
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output wire [7:0] ddc_diagnostics,
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output wire mixer_saturation,
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output wire filter_overflow,
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input wire bypass_mode, // Test mode
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input wire [1:0] test_mode,
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input wire [15:0] test_phase_inc,
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input wire force_saturation,
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input wire reset_monitors,
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output wire [31:0] debug_sample_count,
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output wire [17:0] debug_internal_i,
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output wire [17:0] debug_internal_q
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);
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// Parameters for numerical precision
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parameter ADC_WIDTH = 8;
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parameter NCO_WIDTH = 16;
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parameter MIXER_WIDTH = 18;
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parameter OUTPUT_WIDTH = 18;
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// IF frequency parameters
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parameter IF_FREQ = 120000000;
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parameter FS = 400000000;
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parameter PHASE_WIDTH = 32;
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// Internal signals
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wire signed [15:0] sin_out, cos_out;
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wire nco_ready;
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wire cic_valid;
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wire fir_valid;
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wire [17:0] cic_i_out, cic_q_out;
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wire signed [17:0] fir_i_out, fir_q_out;
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// Diagnostic registers
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reg [2:0] saturation_count;
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reg overflow_detected;
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reg [7:0] error_counter;
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// CDC synchronization for control signals
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reg mixers_enable_sync;
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reg bypass_mode_sync;
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// Debug monitoring signals
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reg [31:0] sample_counter;
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wire signed [17:0] debug_mixed_i_trunc;
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wire signed [17:0] debug_mixed_q_trunc;
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// Real-time status monitoring
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reg [7:0] signal_power_i, signal_power_q;
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// Enhanced saturation injection for testing
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reg force_saturation_sync;
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// Internal mixing signals
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reg signed [MIXER_WIDTH-1:0] adc_signed;
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reg signed [MIXER_WIDTH + NCO_WIDTH -1:0] mixed_i, mixed_q;
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reg mixed_valid;
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reg mixer_overflow_i, mixer_overflow_q;
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// Output stage registers
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reg signed [17:0] baseband_i_reg, baseband_q_reg;
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reg baseband_valid_reg;
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// ============================================================================
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// Phase Dithering Signals
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// ============================================================================
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wire [7:0] phase_dither_bits;
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wire [31:0] phase_inc_dithered;
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// ============================================================================
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// Debug Signal Assignments
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// ============================================================================
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assign debug_internal_i = mixed_i[25:8];
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assign debug_internal_q = mixed_q[25:8];
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assign debug_sample_count = sample_counter;
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assign debug_mixed_i_trunc = mixed_i[25:8];
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assign debug_mixed_q_trunc = mixed_q[25:8];
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// ============================================================================
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// Clock Domain Crossing for Control Signals
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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mixers_enable_sync <= 1'b0;
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bypass_mode_sync <= 1'b0;
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force_saturation_sync <= 1'b0;
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end else begin
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mixers_enable_sync <= mixers_enable;
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bypass_mode_sync <= bypass_mode;
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force_saturation_sync <= force_saturation;
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end
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end
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// ============================================================================
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// Sample Counter and Debug Monitoring
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n || reset_monitors) begin
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sample_counter <= 0;
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saturation_count <= 0;
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error_counter <= 0;
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end else if (adc_data_valid_i && adc_data_valid_q ) begin
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sample_counter <= sample_counter + 1;
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end
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end
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// ============================================================================
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// Enhanced Phase Dithering Instance
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// ============================================================================
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lfsr_dither_enhanced #(
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.DITHER_WIDTH(8)
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) phase_dither_gen (
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.clk(clk_400m),
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.reset_n(reset_n),
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.enable(nco_ready),
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.dither_out(phase_dither_bits)
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);
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// ============================================================================
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// Phase Increment Calculation with Dithering
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// ============================================================================
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// Calculate phase increment for 120MHz IF at 400MHz sampling
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localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
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// Apply dithering to reduce spurious tones
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assign phase_inc_dithered = PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
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// ============================================================================
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// Enhanced NCO with Diagnostics
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// ============================================================================
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nco_400m_enhanced nco_core (
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.clk_400m(clk_400m),
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.reset_n(reset_n),
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.frequency_tuning_word(phase_inc_dithered),
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.phase_valid(mixers_enable),
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.phase_offset(16'h0000),
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.sin_out(sin_out),
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.cos_out(cos_out),
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.dds_ready(nco_ready)
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);
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// ============================================================================
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// Enhanced Mixing Stage with AGC
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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adc_signed <= 0;
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mixed_i <= 0;
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mixed_q <= 0;
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mixed_valid <= 0;
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mixer_overflow_i <= 0;
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mixer_overflow_q <= 0;
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saturation_count <= 0;
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overflow_detected <= 0;
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end else if (nco_ready && adc_data_valid_i && adc_data_valid_q) begin
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// Convert ADC data to signed with extended precision
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adc_signed <= {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
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{1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
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// Force saturation for testing
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if (force_saturation_sync) begin
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mixed_i <= 34'h1FFFFFFFF; // Force positive saturation
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mixed_q <= 34'h200000000; // Force negative saturation
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mixer_overflow_i <= 1'b1;
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mixer_overflow_q <= 1'b1;
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end else begin
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// Normal mixing
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mixed_i <= $signed(adc_signed) * $signed(cos_out);
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mixed_q <= $signed(adc_signed) * $signed(sin_out);
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// Enhanced overflow detection with counting
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mixer_overflow_i <= (mixed_i > (2**(MIXER_WIDTH+NCO_WIDTH-2)-1)) ||
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(mixed_i < -(2**(MIXER_WIDTH+NCO_WIDTH-2)));
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mixer_overflow_q <= (mixed_q > (2**(MIXER_WIDTH+NCO_WIDTH-2)-1)) ||
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(mixed_q < -(2**(MIXER_WIDTH+NCO_WIDTH-2)));
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end
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mixed_valid <= 1;
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if (mixer_overflow_i || mixer_overflow_q) begin
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saturation_count <= saturation_count + 1;
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overflow_detected <= 1'b1;
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end else begin
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overflow_detected <= 1'b0;
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end
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end else begin
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mixed_valid <= 0;
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mixer_overflow_i <= 0;
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mixer_overflow_q <= 0;
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overflow_detected <= 1'b0;
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end
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end
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// ============================================================================
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// Enhanced CIC Decimators
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// ============================================================================
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wire cic_valid_i, cic_valid_q;
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cic_decimator_4x_enhanced cic_i_inst (
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.clk(clk_400m),
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.reset_n(reset_n),
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.data_in(mixed_i[33:16]),
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.data_valid(mixed_valid),
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.data_out(cic_i_out),
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.data_out_valid(cic_valid_i)
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);
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cic_decimator_4x_enhanced cic_q_inst (
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.clk(clk_400m),
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.reset_n(reset_n),
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.data_in(mixed_q[33:16]),
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.data_valid(mixed_valid),
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.data_out(cic_q_out),
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.data_out_valid(cic_valid_q)
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);
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assign cic_valid = cic_valid_i & cic_valid_q;
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cdc_adc_to_processing #(
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.WIDTH(18),
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.STAGES(3)
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)CDC_FIR_i(
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.src_clk(clk_400m),
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.dst_clk(clk_100m),
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.reset_n(reset_n),
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.src_data(cic_i_out),
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.src_valid(cic_valid_i),
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.dst_data(fir_d_in_i),
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.dst_valid(fir_in_valid_i)
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);
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cdc_adc_to_processing #(
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.WIDTH(18),
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.STAGES(3)
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)CDC_FIR_q(
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.src_clk(clk_400m),
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.dst_clk(clk_100m),
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.reset_n(reset_n),
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.src_data(cic_q_out),
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.src_valid(cic_valid_q),
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.dst_data(fir_d_in_q),
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.dst_valid(fir_in_valid_q)
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);
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// ============================================================================
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// Enhanced FIR Filters with FIXED valid signal handling
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// ============================================================================
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wire fir_in_valid_i, fir_in_valid_q;
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wire fir_valid_i, fir_valid_q;
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wire fir_i_ready, fir_q_ready;
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wire [17:0] fir_d_in_i, fir_d_in_q;
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// FIR I channel
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fir_lowpass_parallel_enhanced fir_i_inst (
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.clk(clk_100m),
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.reset_n(reset_n),
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.data_in(fir_d_in_i), // Use synchronized data
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.data_valid(fir_in_valid_i), // Use synchronized valid
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.data_out(fir_i_out),
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.data_out_valid(fir_valid_i),
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.fir_ready(fir_i_ready),
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.filter_overflow()
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);
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// FIR Q channel
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fir_lowpass_parallel_enhanced fir_q_inst (
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.clk(clk_100m),
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.reset_n(reset_n),
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.data_in(fir_d_in_q), // Use synchronized data
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.data_valid(fir_in_valid_q), // Use synchronized valid
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.data_out(fir_q_out),
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.data_out_valid(fir_valid_q),
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.fir_ready(fir_q_ready),
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.filter_overflow()
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);
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assign fir_valid = fir_valid_i & fir_valid_q;
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// ============================================================================
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// Enhanced Output Stage
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// ============================================================================
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always @(negedge clk_100m or negedge reset_n) begin
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if (!reset_n) begin
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baseband_i_reg <= 0;
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baseband_q_reg <= 0;
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baseband_valid_reg <= 0;
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end else if (fir_valid) begin
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baseband_i_reg <= fir_i_out;
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baseband_q_reg <= fir_q_out;
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baseband_valid_reg <= 1;
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end else begin
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baseband_valid_reg <= 0;
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end
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end
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// ============================================================================
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// Output Assignments
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// ============================================================================
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assign baseband_i = baseband_i_reg;
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assign baseband_q = baseband_q_reg;
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assign baseband_valid_i = baseband_valid_reg;
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assign baseband_valid_q = baseband_valid_reg;
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assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
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assign mixer_saturation = overflow_detected;
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assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
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// ============================================================================
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// Enhanced Debug and Monitoring
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// ============================================================================
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reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;
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always @(posedge clk_100m) begin
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if (fir_valid_i && debug_fir_count < 20) begin
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debug_fir_count <= debug_fir_count + 1;
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$display("FIR_OUTPUT: fir_i=%6d, fir_q=%6d", fir_i_out, fir_q_out);
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end
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if (adc_data_valid_i && adc_data_valid_q && debug_bb_count < 20) begin
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debug_bb_count <= debug_bb_count + 1;
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$display("BASEBAND_OUT: i=%6d, q=%6d, count=%0d",
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baseband_i, baseband_q, debug_bb_count);
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end
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end
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// In ddc_400m.v, add these debug signals:
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// Debug monitoring
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reg [31:0] debug_adc_count = 0;
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reg [31:0] debug_baseband_count = 0;
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always @(posedge clk_400m) begin
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if (adc_data_valid_i && adc_data_valid_q && debug_adc_count < 10) begin
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debug_adc_count <= debug_adc_count + 1;
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$display("DDC_ADC: data=%0d, count=%0d, time=%t",
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adc_data, debug_adc_count, $time);
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end
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end
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always @(posedge clk_100m) begin
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if (baseband_valid_i && baseband_valid_q && debug_baseband_count < 10) begin
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debug_baseband_count <= debug_baseband_count + 1;
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$display("DDC_BASEBAND: i=%0d, q=%0d, count=%0d, time=%t",
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baseband_i, baseband_q, debug_baseband_count, $time);
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end
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end
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endmodule
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// ============================================================================
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// Enhanced Phase Dithering Module
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// ============================================================================
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`timescale 1ns / 1ps
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module lfsr_dither_enhanced #(
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parameter DITHER_WIDTH = 8 // Increased for better dithering
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)(
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input wire clk,
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input wire reset_n,
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input wire enable,
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output wire [DITHER_WIDTH-1:0] dither_out
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);
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reg [DITHER_WIDTH-1:0] lfsr_reg;
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reg [15:0] cycle_counter;
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reg lock_detected;
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// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
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wire feedback;
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generate
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if (DITHER_WIDTH == 4) begin
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assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
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end else if (DITHER_WIDTH == 8) begin
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assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
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end else begin
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assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
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end
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endgenerate
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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lfsr_reg <= {DITHER_WIDTH{1'b1}}; // Non-zero initial state
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cycle_counter <= 0;
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lock_detected <= 0;
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end else if (enable) begin
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lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
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cycle_counter <= cycle_counter + 1;
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// Detect LFSR lock after sufficient cycles
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if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
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lock_detected <= 1'b1;
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end
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end
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end
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assign dither_out = lfsr_reg;
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endmodule
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