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Jason 5499827ab7 add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean)

FMC LPC dev build for TE0713/TE0701 + UMFT601X-B stack. Fixed timing
closure: replaced set_output_delay with set_max_delay -datapath_only
to eliminate false IBUF+BUFG clock skew penalty on source-synchronous
outputs. Removed erroneous set_input_delay on output-only ft601_be[*].
Added IOB packing for siwu_n, false paths for async GPIO/reset/wakeup.
Strategy: Performance_ExplorePostRoutePhysOpt.

Results: WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors, 0 failing endpoints.
Bitstream: docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit

2026-03-21 20:43:52 +02:00

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AERIS-10 FT601 Integration Dev Bitstream

File: te0713-te0701-umft601x-dev-2026-03-21.bit
Tag: v0.1.8-te0713-ft601-dev
Date: 2026-03-21
Target: XC7A200T-2FBG484C (TE0713-03) on TE0701-06 carrier + UMFT601X-B FMC LPC

Build Summary

Metric	Value
WNS (setup)	+0.059 ns
WHS (hold)	+0.121 ns
WPWS (pulse width)	+4.500 ns
Failing endpoints	0
DRC errors	0
Clock	ft601_clk_in 100 MHz (10 ns period)
Strategy	Performance_ExplorePostRoutePhysOpt
Vivado	2025.2

What This Bitstream Does

Instantiates usb_data_interface.v (full FT601 USB data path) via a thin wrapper (radar_system_top_te0713_umft601x_dev.v)
Generates synthetic test data: range profile packets (counter XOR pattern), optional Doppler and CFAR packets, controlled by host commands
Responds to USB host commands (stream control 0x04, status request 0xFF)
Drives ft601_gpio0 with a ~6 Hz heartbeat (counter bit 24)
Drives ft601_chip_reset_n after power-on reset (32k clock cycles)
ft601_wakeup_n held high (inactive)

Hardware Setup

TE0713-03 mounted on TE0701-06 carrier
UMFT601X-B plugged into TE0701 J10 (FMC LPC connector)
TE0701 VIOTB = 3.3V (jumper configuration)
UMFT601X-B jumpers: JP1=open, JP2=2-3, JP3=open, JP6=short (3.3V), JP4=2-3, JP5=2-3 (245 Sync FIFO mode)
USB 3.0 Micro-B cable from UMFT601X-B to host PC
Trenz programming USB for JTAG

Programming

# Open Vivado Hardware Manager
open_hw_manager
connect_hw_server
open_hw_target
set_property PROGRAM.FILE {te0713-te0701-umft601x-dev-2026-03-21.bit} [current_hw_device]
program_hw_devices [current_hw_device]

Verification Steps

After programming, check ft601_gpio0 toggles (~6 Hz) — confirms FPGA running
On host PC, FT601 should enumerate as USB 3.0 device (VID 0x0403, PID 0x601F)
Use FTDI D3XX driver / ftd3xx Python library to read data:
- Open device, set pipe to channel 0
- Read should return 32-bit words with test pattern packets
- Packet header: 0xAE10xxxx where xxxx = packet type

Timing Closure Notes

Previous builds failed setup timing due to source-synchronous clock skew:

The FT601 clock enters via IBUF+BUFG (~5 ns insertion delay)
set_output_delay referenced to ft601_clk_in created a false ~5 ns skew penalty (source has insertion, destination at port has 0)
Fixed by using set_max_delay -datapath_only for output constraints, which constrains the register-to-pad path directly (7.5 ns budget)
Input delays still use set_input_delay referenced to ft601_clk_in (correct direction: FT601 drives data, FPGA samples after IBUF+BUFG)

Source Files

9_Firmware/9_2_FPGA/radar_system_top_te0713_umft601x_dev.v — wrapper top
9_Firmware/9_2_FPGA/usb_data_interface.v — FT601 USB data interface
9_Firmware/9_2_FPGA/constraints/te0713_te0701_umft601x.xdc — FMC LPC constraints
9_Firmware/9_2_FPGA/scripts/build_te0713_umft601x_dev.tcl — build script

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