Jason
19284ac277
Build 21 Vivado results extracted and documented: - WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns (all timing met) - 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%) - Total power: 0.732 W - Barrel-shift twiddle freed 1 DSP (140 -> 139) as expected - TCL script fix: wrap check_timing in catch (Vivado 2025.2 bug) - Updated release-notes.html, implementation-log.html, reports.html
134 lines
8.7 KiB
HTML
134 lines
8.7 KiB
HTML
<!doctype html>
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<html lang="en">
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<head>
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<meta charset="utf-8">
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<meta name="viewport" content="width=device-width, initial-scale=1">
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<title>AERIS-10 Docs | Reports</title>
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<link rel="stylesheet" href="assets/style.css">
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</head>
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<body>
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<header class="topbar">
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<div class="container nav">
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<a class="brand" href="index.html">AERIS-10 Docs</a>
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<nav>
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<a href="architecture.html">Architecture</a>
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<a href="implementation-log.html">Implementation Log</a>
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<a href="bring-up.html">Bring-Up</a>
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<a href="reports.html">Reports</a>
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<a href="release-notes.html">Release Notes</a>
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</nav>
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</div>
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</header>
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<main class="container page">
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<section class="hero">
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<p class="eyebrow">Artifacts</p>
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<h1>Published Reports and Visuals</h1>
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<p>Central access point for antenna simulations, implementation summaries, timing baselines, and board-day artifact references.</p>
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<div class="cta-row">
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<a class="button" href="board-day-worksheet.html">Open Board-Day Worksheet</a>
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<a class="button ghost" href="bring-up.html">Open Bring-Up Plan</a>
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</div>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Current FPGA implementation status</h2>
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<ul>
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<li><strong>Build 21 (v0.1.4-build21)</strong> is the current production baseline for the XC7A200T target. All timing constraints met: WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns.</li>
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<li>Utilization: 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%), 0.732 W total power.</li>
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<li>Key improvements over Build 20: FFT 4-cycle butterfly (20% throughput gain), barrel-shift twiddle index (-1 DSP48), Gap 2 GUI Settings (runtime chirp timing, stream control, status readback), E2E RTL fixes, Vivado DRC multiple-driver fix, MMCM LOCKED XDC false_path correction.</li>
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<li>Build 21 reports are available on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build21/</code>.</li>
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</ul>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Board-day artifact inventory</h2>
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<div class="table-wrap">
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<table>
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<thead>
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<tr>
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<th>Artifact</th>
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<th>Source path</th>
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<th>Day-0 use</th>
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<th>Status / note</th>
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</tr>
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</thead>
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<tbody>
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<tr><td>Production-target XDC</td><td><code>9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc</code></td><td>Constraint source of truth for the production FPGA target</td><td>Tracked and validated after Build 16 cleanup port</td></tr>
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<tr><td>FPGA programming flow</td><td><code>9_Firmware/9_2_FPGA/scripts/program_fpga.tcl</code></td><td>Programs the device and reports DONE / INIT_COMPLETE / probes presence</td><td>Primary operator-facing programming script</td></tr>
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<tr><td>Debug probe insertion flow</td><td><code>9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl</code></td><td>Used when generating or refreshing debug-capable images</td><td>Keep matched with the selected debug bitstream</td></tr>
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<tr><td>FPGA regression runner</td><td><code>9_Firmware/9_2_FPGA/run_regression.sh</code></td><td>Pre-arrival regression evidence for the tracked FPGA baseline</td><td>19 / 19 passing on the current tracked branch (includes E2E test)</td></tr>
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<tr><td>MCU regression harness</td><td><code>9_Firmware/9_1_Microcontroller/tests/Makefile</code></td><td>Pre-arrival firmware regression evidence before flashing hardware</td><td>20 / 20 passing on the current tracked branch</td></tr>
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<tr><td>Bring-up logging macros</td><td><code>9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h</code></td><td>Defines the main first-power-on log vocabulary used over USART3</td><td>Observation-only instrumentation layer</td></tr>
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<tr><td>Board-day worksheet</td><td><code>docs/board-day-worksheet.html</code></td><td>Record pass/fail, measurements, and blockers during first sessions</td><td>Use with this page and the bring-up plan</td></tr>
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<tr><td>Bring-up execution plan</td><td><code>docs/bring-up.html</code></td><td>Operator checklist, abort criteria, observability targets, and open risks</td><td>Primary readiness document</td></tr>
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</tbody>
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</table>
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</div>
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</section>
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<section class="grid-2" style="margin-top:0.8rem;">
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<article class="card">
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<h2>Antenna Simulation Report</h2>
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<p><span class="chip">Status: Mostly current (historical Phase-0 context)</span></p>
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<p class="muted">File: <code>AERIS_Antenna_Report.pdf</code></p>
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<p class="muted">Notes: Valid for 10.5 GHz patch-element simulation and array projection context. Treat as element-level evidence, not full current hardware bring-up sign-off.</p>
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<p>
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<a class="button" href="AERIS_Antenna_Report.pdf" target="_blank" rel="noopener">Open PDF</a>
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<a class="button ghost" href="AERIS_Antenna_Report.pdf" download>Download</a>
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</p>
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</article>
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<article class="card">
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<h2>Python Simulation Report</h2>
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<p><span class="chip">Status: Legacy (needs refresh)</span></p>
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<p class="muted">File: <code>AERIS_Simulation_Report.pdf</code></p>
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<p class="muted">Notes: Contains older architecture assumptions (e.g., XC7A100T-centric narrative). Use as historical reference only until Simulation Report v2 is published.</p>
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<p>
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<a class="button" href="AERIS_Simulation_Report.pdf" target="_blank" rel="noopener">Open PDF</a>
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<a class="button ghost" href="AERIS_Simulation_Report.pdf" download>Download</a>
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</p>
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</article>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>FPGA implementation analysis</h2>
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<p><span class="chip">Status: Current engineering baseline — Build 21 (v0.1.4-build21)</span></p>
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<p class="muted">Build 21 is the current production baseline. Full timing, utilization, power, DRC, methodology, CDC, and route reports are available on the remote Vivado host. Setup slack is +0.156 ns (tighter than Build 20's +0.426 ns due to Gap 2 register map additions, but comfortable and better than the intermediate Gap 2 build at +0.078 ns). Hold slack improved to +0.064 ns. DSP count dropped from 140 to 139 via barrel-shift twiddle optimization.</p>
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<p class="muted">Build 20 (v0.1.3-build20) retained as prior reference. Build 19 failed timing (WNS -0.011 ns) due to conflicting XDC generated clock, root-caused and fixed in Build 20.</p>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Latest Simulation Report (Recommended)</h2>
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<p><span class="chip">Status: Current baseline (v2)</span></p>
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<p class="muted">File: <code>AERIS_Simulation_Report_v2.pdf</code></p>
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<p class="muted">Aligned to the active project baseline: XC7A200T target, firmware regression closure, FPGA regression/timing gates, USB range-profile integration, and TE0712/TE0713 split-target flow.</p>
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<p>
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<a class="button" href="AERIS_Simulation_Report_v2.pdf" target="_blank" rel="noopener">Open PDF</a>
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<a class="button ghost" href="AERIS_Simulation_Report_v2.pdf" download>Download</a>
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</p>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Report Currency Notice</h2>
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<ul>
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<li>The current routed production-target baseline is <strong>Build 21 (v0.1.4-build21)</strong> with all timing constraints met. WNS +0.156 ns, WHS +0.064 ns, 139 DSP48E1, 0.732 W.</li>
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<li>Architectural gaps 2 (GUI Settings), 3 (Safety), 4 (USB Read Path), 5 (BRAM Reset), and 7 (MMCM) are closed. Gaps 1 (CFAR) and 6 (CDC-15) remain for post-bring-up.</li>
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<li>FPGA regression: 19/19 pass (includes new E2E integration test). MCU regression: 20/20 pass (15 bug-fix + 5 Gap-3 safety).</li>
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<li>FFT engine optimized and Vivado-verified in Build 21: 4-cycle butterfly (20% throughput gain) + barrel-shift twiddle index (freed 1 DSP48, 140 → 139).</li>
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<li>Detailed Build 21 engineering reports are on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build21/</code>.</li>
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<li>The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.</li>
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</ul>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Antenna concept snapshot</h2>
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<img class="diagram" src="assets/img/Antenna_Array.jpg" alt="Antenna array concept">
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</section>
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</main>
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<footer class="footer">
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<div class="container"><p>Add future report artifacts here to keep public references stable.</p></div>
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