Jason c983a3c705 Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG ...

Phase 0+ timing optimization (attempts #13-22 + implementation):

NCO (nco_400m_enhanced.v):
- 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX
- DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain)
- Registered phase_inc_dithered to break cascaded 32-bit add path

DDC (ddc_400m.v):
- Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1)
- CEP=1, RSTP=!reset_n for proper pipeline control
- 3-stage dsp_valid_pipe for PREG=1 latency
- Behavioral sim model under ifdef SIMULATION for Icarus compatibility

CIC (cic_decimator_4x_enhanced.v):
- 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28
- Removed integrator/comb saturation (CIC uses wrapping arithmetic by design)
- Pipelined output saturation comparison

CDC/ASYNC_REG:
- ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v,
  radar_system_top.v, usb_data_interface.v)
- Sync reset in generate blocks (cdc_modules.v)

Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints,
850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t.
All testbenches pass: 241/244 (3 known stub failures).

2026-03-16 01:02:07 +02:00

..

tb

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

ad9484_interface_400m.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cdc_modules.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

chirp_lut_init.v

Add files via upload

2026-03-09 00:17:39 +00:00

chirp_memory_loader_param.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cic_decimator_4x_enhanced.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

cntrt.xdc

Create cntrt.xdc

2026-03-10 02:42:15 +00:00

dac_interface_single.v

Add files via upload

2026-03-09 00:17:39 +00:00

ddc_400m.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

ddc_input_interface.v

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2026-03-09 00:17:39 +00:00

doppler_processor.v

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2026-03-09 00:17:39 +00:00

edge_detector.v

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2026-03-09 00:17:39 +00:00

fft_1024_forward.v

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2026-03-09 00:17:39 +00:00

fft_1024_inverse.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

fir_lowpass.v

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2026-03-09 00:17:39 +00:00

frequency_matched_filter.v

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2026-03-09 00:17:39 +00:00

latency_buffer_2159.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

level_shifter_interface.v

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2026-03-10 01:31:50 +00:00

long_chirp_seg0_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg0_q.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg1_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg1_q.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg2_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg2_q.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg3_i.mem

Add missing long_chirp_seg3 memory files for complete chirp waveform

2026-03-15 18:06:35 +02:00

long_chirp_seg3_q.mem

Add missing long_chirp_seg3 memory files for complete chirp waveform

2026-03-15 18:06:35 +02:00

lvds_to_cmos_400m.v

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2026-03-09 00:17:39 +00:00

matched_filter_multi_segment.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

matched_filter_processing_chain.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

nco_400m_enhanced.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

plfm_chirp_controller.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

radar_mode_controller.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

radar_receiver_final.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

radar_system_tb.v

Create radar_system_tb.v

2026-03-10 01:35:26 +00:00

radar_system_top.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

radar_transmitter.v

Add files via upload

2026-03-09 00:17:39 +00:00

range_bin_decimator.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

short_chirp_i.mem

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2026-03-09 00:17:39 +00:00

short_chirp_q.mem

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2026-03-09 00:17:39 +00:00

usb_data_interface.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

usb_packet_analyzer.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

xfft_32.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00